--! @file
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--! @file
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--! @brief Register File unit http://en.wikipedia.org/wiki/Register_file
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--! @brief Register File unit http://en.wikipedia.org/wiki/Register_file
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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--! A register file is an array of processor registers in a central processing unit (CPU).
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--! A register file is an array of processor registers in a central processing unit (CPU).
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--! A register file is an array of processor registers in a central processing unit (CPU).\n
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--! A register file is an array of processor registers in a central processing unit (CPU).\n
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--! Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports.\n
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--! Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports.\n
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--! Such RAMs are distinguished by having dedicated read and write ports, whereas ordinary multiported SRAMs will usually read and write\n
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--! Such RAMs are distinguished by having dedicated read and write ports, whereas ordinary multiported SRAMs will usually read and write\n
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--! through the same ports.
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--! through the same ports.
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entity RegisterFile is
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entity RegisterFile is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the registers)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the registers)
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Port ( clk : in STD_LOGIC; --! Clock signal
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Port ( clk : in STD_LOGIC; --! Clock signal
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writeEn : in STD_LOGIC; --! Write enable
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writeEn : in STD_LOGIC; --! Write enable
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writeAddr : in generalRegisters; --! Write Adress
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writeAddr : in generalRegisters; --! Write Adress
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input : in STD_LOGIC_VECTOR (n downto 0); --! Input
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input : in STD_LOGIC_VECTOR (n downto 0); --! Input
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Read_A_En : in STD_LOGIC; --! Enable read A
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Read_A_En : in STD_LOGIC; --! Enable read A
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Read_A_Addr : in generalRegisters; --! Read A adress
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Read_A_Addr : in generalRegisters; --! Read A adress
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Read_B_En : in STD_LOGIC; --! Enable read A
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Read_B_En : in STD_LOGIC; --! Enable read A
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Read_B_Addr : in generalRegisters; --! Read B adress
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Read_B_Addr : in generalRegisters; --! Read B adress
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A_Out : out STD_LOGIC_VECTOR (n downto 0); --! Output A
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A_Out : out STD_LOGIC_VECTOR (n downto 0); --! Output A
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B_Out : out STD_LOGIC_VECTOR (n downto 0)); --! Output B
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B_Out : out STD_LOGIC_VECTOR (n downto 0)); --! Output B
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end RegisterFile;
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end RegisterFile;
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--! @brief This register file will have one input and two ouputs.
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--! @brief This register file will have one input and two ouputs.
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--! @details This will permit to read two registers on the same clock, but will need n clock cicles for n register assignments...
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--! @details This will permit to read two registers on the same clock, but will need n clock cicles for n register assignments...
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architecture Behavioral of RegisterFile is
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architecture Behavioral of RegisterFile is
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subtype reg is STD_LOGIC_VECTOR (n downto 0); -- Define register type
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subtype reg is STD_LOGIC_VECTOR (n downto 0); -- Define register type
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type regArray is array (0 to (numGenRegs-1)) of reg; -- Define register type array
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type regArray is array (0 to (numGenRegs-1)) of reg; -- Define register type array
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signal regFile : regArray; -- This signal will infer an FF array if assigned by a clock edge...
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signal regFile : regArray; -- This signal will infer an FF array if assigned by a clock edge...
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begin
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begin
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-- Write some register value...
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-- Write some register value...
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writeProcess: process (clk)
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writeProcess: process (clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if (writeEn = '1') then
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if (writeEn = '1') then
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regFile(CONV_INTEGER(reg2Num(writeAddr))) <= input;
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regFile(CONV_INTEGER(reg2Num(writeAddr))) <= input;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Read some register in port A
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-- Read some register in port A
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readAProcess : process(Read_A_En,Read_A_Addr)
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readAProcess : process(Read_A_En,Read_A_Addr)
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begin
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begin
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if (Read_A_En = '1') then
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if (Read_A_En = '1') then
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A_Out <= regFile(CONV_INTEGER(reg2Num(writeAddr)));
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A_Out <= regFile(CONV_INTEGER(reg2Num(Read_A_Addr)));
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else
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else
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A_Out <= (others => 'Z');
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A_Out <= (others => 'Z');
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end if;
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end if;
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end process;
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end process;
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-- Read some register in port B
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-- Read some register in port B
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readBProcess : process(Read_B_En,Read_B_Addr)
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readBProcess : process(Read_B_En,Read_B_Addr)
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begin
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begin
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if (Read_B_En = '1') then
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if (Read_B_En = '1') then
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B_Out <= regFile(CONV_INTEGER(reg2Num(writeAddr)));
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B_Out <= regFile(CONV_INTEGER(reg2Num(Read_B_Addr)));
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else
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else
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B_Out <= (others => 'Z');
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B_Out <= (others => 'Z');
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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