--! @file
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--! @file
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--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit
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--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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--! Cpu top level file
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--! Cpu top level file
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--! Include the Control Unit and datapath
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--! Include the Control Unit and datapath
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entity openCpu is
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entity openCpu is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( rst : in STD_LOGIC; --! Reset signal
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Port ( rst : in STD_LOGIC; --! Reset signal
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clk : in STD_LOGIC; --! Clock signal
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clk : in STD_LOGIC; --! Clock signal
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mem_rd : out STD_LOGIC; --! Main memory Read enable
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mem_rd : out STD_LOGIC; --! Main memory Read enable
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mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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mem_wr : out STD_LOGIC; --! Main memory Write enable
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mem_wr : out STD_LOGIC; --! Main memory Write enable
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mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory
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mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory
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mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory
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mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory
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);
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);
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end openCpu;
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end openCpu;
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--! @brief Cpu http://en.wikipedia.org/wiki/Central_processing_unit
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--! @brief Cpu http://en.wikipedia.org/wiki/Central_processing_unit
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--! @details This description will instantiate the components ControlUnit and DataPath
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--! @details This description will instantiate the components ControlUnit and DataPath
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architecture Behavioral of openCpu is
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architecture Behavioral of openCpu is
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COMPONENT DataPath is
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COMPONENT DataPath is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
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Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
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inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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clk : in STD_LOGIC; --! Clock signal
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clk : in STD_LOGIC; --! Clock signal
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outEn : in typeEnDis; --! Enable/Disable datapath output
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outEn : in typeEnDis; --! Enable/Disable datapath output
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aluOp : in aluOps; --! Alu operations
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aluOp : in aluOps; --! Alu operations
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muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
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regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
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outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
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outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
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dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
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dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
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end COMPONENT;
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end COMPONENT;
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COMPONENT ControlUnit is
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COMPONENT ControlUnit is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( reset : in STD_LOGIC;
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC; --! Main system clock
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clk : in STD_LOGIC; --! Main system clock
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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DpAluOp : out aluOps; --! Alu operations
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DpAluOp : out aluOps; --! Alu operations
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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DpRegFileReadAddrB : out generalRegisters; --! General register address to read
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DpRegFileReadAddrB : out generalRegisters; --! General register address to read
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DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)
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DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)
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DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)
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DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)
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MemoryDataReadEn : out std_logic; --! Enable Main memory read
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MemoryDataReadEn : out std_logic; --! Enable Main memory read
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MemoryDataWriteEn: out std_logic; --! Enable Main memory write
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MemoryDataWriteEn: out std_logic; --! Enable Main memory write
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
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MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
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MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
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end COMPONENT;
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end COMPONENT;
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signal InputImediate : STD_LOGIC_VECTOR (n downto 0);
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signal InputImediate : STD_LOGIC_VECTOR (n downto 0);
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signal enableOutputDp : typeEnDis;
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signal enableOutputDp : typeEnDis;
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signal aluOperations : aluOps;
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signal aluOperations : aluOps;
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signal InputDataPathSelector : STD_LOGIC_VECTOR (2 downto 0);
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signal InputDataPathSelector : dpMuxInputs;
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signal InputDataPathAluASelector : STD_LOGIC_VECTOR (1 downto 0);
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signal InputDataPathAluASelector : STD_LOGIC_VECTOR (1 downto 0);
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signal registerFileWriteAddress : generalRegisters;
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signal registerFileWriteAddress : generalRegisters;
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signal registerFileWriteEnable : STD_LOGIC;
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signal registerFileWriteEnable : STD_LOGIC;
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signal registerFileReadAddressA : generalRegisters;
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signal registerFileReadAddressA : generalRegisters;
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signal registerFileReadAddressB : generalRegisters;
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signal registerFileReadAddressB : generalRegisters;
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signal registerFileReadEnableA : STD_LOGIC;
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signal registerFileReadEnableA : STD_LOGIC;
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signal registerFileReadEnableB : STD_LOGIC;
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signal registerFileReadEnableB : STD_LOGIC;
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signal dataPathOutput : STD_LOGIC_VECTOR (n downto 0);
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signal dataPathOutput : STD_LOGIC_VECTOR (n downto 0);
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signal dataPathFlags : STD_LOGIC_VECTOR (2 downto 0);
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signal dataPathFlags : STD_LOGIC_VECTOR (2 downto 0);
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begin
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begin
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--! Instantiate the Datapath
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--! Instantiate the Datapath
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uDataPath: DataPath PORT MAP (
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uDataPath: DataPath PORT MAP (
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inputMm => InputImediate,
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inputMm => InputImediate,
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inputImm => mem_data_in,
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inputImm => mem_data_in,
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clk => clk,
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clk => clk,
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outEn => enableOutputDp,
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outEn => enableOutputDp,
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aluOp => aluOperations,
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aluOp => aluOperations,
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muxSel => InputDataPathSelector,
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muxSel => InputDataPathSelector,
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muxRegFile => InputDataPathAluASelector,
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muxRegFile => InputDataPathAluASelector,
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regFileWriteAddr => registerFileWriteAddress,
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regFileWriteAddr => registerFileWriteAddress,
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regFileWriteEn => registerFileWriteEnable,
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regFileWriteEn => registerFileWriteEnable,
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regFileReadAddrA => registerFileReadAddressA,
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regFileReadAddrA => registerFileReadAddressA,
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regFileReadAddrB => registerFileReadAddressB,
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regFileReadAddrB => registerFileReadAddressB,
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regFileEnA => registerFileReadEnableA,
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regFileEnA => registerFileReadEnableA,
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regFileEnB => registerFileReadEnableB,
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regFileEnB => registerFileReadEnableB,
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outputDp => dataPathOutput,
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outputDp => dataPathOutput,
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dpFlags => dataPathFlags
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dpFlags => dataPathFlags
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);
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);
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--! Instantiate the control unit
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--! Instantiate the control unit
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uControlUnit: ControlUnit PORT MAP (
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uControlUnit: ControlUnit PORT MAP (
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reset => rst,
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reset => rst,
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clk => clk,
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clk => clk,
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FlagsDp => dataPathFlags,
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FlagsDp => dataPathFlags,
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DataDp => dataPathOutput,
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DataDp => dataPathOutput,
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outEnDp => enableOutputDp,
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outEnDp => enableOutputDp,
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MuxDp => InputDataPathSelector,
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MuxDp => InputDataPathSelector,
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MuxRegDp => InputDataPathAluASelector,
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MuxRegDp => InputDataPathAluASelector,
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ImmDp => InputImediate,
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ImmDp => InputImediate,
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DpAluOp => aluOperations,
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DpAluOp => aluOperations,
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DpRegFileWriteAddr => registerFileWriteAddress,
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DpRegFileWriteAddr => registerFileWriteAddress,
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DpRegFileWriteEn => registerFileWriteEnable,
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DpRegFileWriteEn => registerFileWriteEnable,
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DpRegFileReadAddrA => registerFileReadAddressA,
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DpRegFileReadAddrA => registerFileReadAddressA,
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DpRegFileReadAddrB => registerFileReadAddressB,
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DpRegFileReadAddrB => registerFileReadAddressB,
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DpRegFileReadEnA => registerFileReadEnableA,
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DpRegFileReadEnA => registerFileReadEnableA,
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DpRegFileReadEnB => registerFileReadEnableB,
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DpRegFileReadEnB => registerFileReadEnableB,
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MemoryDataReadEn => mem_rd,
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MemoryDataReadEn => mem_rd,
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MemoryDataWriteEn => mem_wr,
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MemoryDataWriteEn => mem_wr,
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MemoryDataInput => mem_data_in,
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MemoryDataInput => mem_data_in,
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MemoryDataRdAddr => mem_rd_addr,
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MemoryDataRdAddr => mem_rd_addr,
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MemoryDataWrAddr => mem_wr_addr,
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MemoryDataWrAddr => mem_wr_addr,
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MemoryDataOut => mem_data_out
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MemoryDataOut => mem_data_out
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);
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);
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end Behavioral;
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end Behavioral;
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