--! @file
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--! @file
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--! @brief 2:1 CPU global Definitions
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--! @brief 2:1 CPU global Definitions
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--! @mainpage
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--! @mainpage
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--! <H1>Main document of the OpenCPU32 project</H1>\n
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--! <H1>Main document of the OpenCPU32 project</H1>\n
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--! <H2>Features</H2>
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--! <H2>Features</H2>
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--! 32 Bits \n
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--! 32 Bits \n
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--! RISC \n\n
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--! RISC \n\n
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--! Interesting links \n
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--! Interesting links \n
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--! http://www.ohwr.org/projects \n
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--! http://www.ohwr.org/projects \n
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--! http://opencores.org/ \n
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--! http://opencores.org/ \n
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--! Use standard library
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--! Use standard library
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library ieee;
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library ieee;
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use ieee.STD_LOGIC_1164.all;
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use ieee.STD_LOGIC_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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package pkgOpenCPU32 is
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package pkgOpenCPU32 is
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--! Declare constants, enums, functions used by the design
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--! Declare constants, enums, functions used by the design
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constant nBits : integer := 32;
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constant nBits : integer := 32;
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constant instructionSize : integer := nBits;
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constant instructionSize : integer := nBits;
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--! Number of general registers (r0..r15)
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--! Number of general registers (r0..r15)
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constant numGenRegs : integer := 16;
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constant numGenRegs : integer := 16;
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type aluOps is (alu_pass, alu_passB, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and,
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type aluOps is (alu_pass, alu_passB, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_udiv, alu_or, alu_and,
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alu_xor, alu_not, alu_shfLt, alu_shfRt, alu_roLt, alu_roRt);
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alu_xor, alu_not, alu_shfLt, alu_shfRt, alu_roLt, alu_roRt);
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type typeEnDis is (enable, disable);
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type typeEnDis is (enable, disable);
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type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
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type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
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type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu);
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type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu);
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type dpMuxAluIn is (fromMemory, fromImediate, fromRegFileA);
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type dpMuxAluIn is (fromMemory, fromImediate, fromRegFileA);
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type controlUnitStates is (initial, fetch, decode, execute, executing);
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type controlUnitStates is (initial, fetch, decode, execute, executing);
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type executionStates is (initInstructionExecution, waitToExecute, writeRegister, releaseWriteRead, readRegisterA, readRegisterB, releaseRead);
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type executionStates is (initInstructionExecution, waitToExecute, writeRegister, releaseWriteRead, readRegisterA, readRegisterB, releaseRead);
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--! Flags positions
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--! Flags positions
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constant flag_sign : integer := 2;
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constant flag_sign : integer := 2;
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constant flag_zero : integer := 1;
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constant flag_zero : integer := 1;
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constant flag_carry : integer := 0;
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constant flag_carry : integer := 0;
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function reg2Num (a: generalRegisters) return integer;
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function reg2Num (a: generalRegisters) return integer;
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function Num2reg (a: integer) return generalRegisters;
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function Num2reg (a: integer) return generalRegisters;
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function muxPos( a: dpMuxInputs) return std_logic_vector;
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function muxPos( a: dpMuxInputs) return std_logic_vector;
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function muxRegPos(a: dpMuxAluIn) return std_logic_vector;
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function muxRegPos(a: dpMuxAluIn) return std_logic_vector;
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function opcode2AluOp (opcode : std_logic_vector(5 downto 0)) return aluOps;
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function opcode2AluOp (opcode : std_logic_vector(5 downto 0)) return aluOps;
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function udivision(dividend: unsigned; divisor: unsigned) return unsigned;
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-- Opcodes
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-- Opcodes
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subtype opcodes is std_logic_vector(5 downto 0); -- 6 Bits (64 instructions max)
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subtype opcodes is std_logic_vector(5 downto 0); -- 6 Bits (64 instructions max)
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-- Each instruction will take 32 bits
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-- Each instruction will take 32 bits
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-- Tutorial on using records.. (http://vhdlguru.blogspot.com.br/2010/02/arrays-and-records-in-vhdl.html)
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-- Tutorial on using records.. (http://vhdlguru.blogspot.com.br/2010/02/arrays-and-records-in-vhdl.html)
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type instructionType is record
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type instructionType is record
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opcode : std_logic_vector(5 downto 0);
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opcode : std_logic_vector(5 downto 0);
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reg1 : std_logic_vector(3 downto 0);
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reg1 : std_logic_vector(3 downto 0);
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reg2 : std_logic_vector(3 downto 0);
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reg2 : std_logic_vector(3 downto 0);
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imm : std_logic_vector(15 downto 0); -- Max imediate value (16 bits)
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imm : std_logic_vector(15 downto 0); -- Max imediate value (16 bits)
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end record;
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end record;
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-- Data movement
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-- Data movement
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constant mov_reg : opcodes := conv_std_logic_vector(0,6); -- Move data between registers
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constant mov_reg : opcodes := conv_std_logic_vector(0,6); -- Move data between registers
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constant mov_val : opcodes := conv_std_logic_vector(1,6); -- Move data from imediate value to a register
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constant mov_val : opcodes := conv_std_logic_vector(1,6); -- Move data from imediate value to a register
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constant stom_reg : opcodes := conv_std_logic_vector(2,6); -- Store a value in memory coming from a register
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constant stom_reg : opcodes := conv_std_logic_vector(2,6); -- Store a value in memory coming from a register
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constant stom_val : opcodes := conv_std_logic_vector(3,6); -- Store a value in memory coming from imediate
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constant stom_val : opcodes := conv_std_logic_vector(3,6); -- Store a value in memory coming from imediate
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constant ld_reg : opcodes := conv_std_logic_vector(4,6); -- Load a value from memory into a register
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constant ld_reg : opcodes := conv_std_logic_vector(4,6); -- Load a value from memory into a register
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constant ld_val : opcodes := conv_std_logic_vector(5,6); -- Load a value from memoru into another address in memory
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constant ld_val : opcodes := conv_std_logic_vector(5,6); -- Load a value from memoru into another address in memory
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-- Jump instructions
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-- Jump instructions
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constant jmp_val : opcodes := conv_std_logic_vector(6,6); -- Jump (PC <= Val)
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constant jmp_val : opcodes := conv_std_logic_vector(6,6); -- Jump (PC <= Val)
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constant jmpr_val : opcodes := conv_std_logic_vector(7,6); -- Jump relative (PC <= PC + Val)
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constant jmpr_val : opcodes := conv_std_logic_vector(7,6); -- Jump relative (PC <= PC + Val)
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constant jz_val : opcodes := conv_std_logic_vector(8,6); -- Jump if zero
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constant jz_val : opcodes := conv_std_logic_vector(8,6); -- Jump if zero
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constant jzr_val : opcodes := conv_std_logic_vector(9,6); -- Jump if zero relative
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constant jzr_val : opcodes := conv_std_logic_vector(9,6); -- Jump if zero relative
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constant jnz_val : opcodes := conv_std_logic_vector(10,6); -- Jump if not zero
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constant jnz_val : opcodes := conv_std_logic_vector(10,6); -- Jump if not zero
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constant jnzr_val : opcodes := conv_std_logic_vector(11,6); -- Jump if not zero relative
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constant jnzr_val : opcodes := conv_std_logic_vector(11,6); -- Jump if not zero relative
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constant call_reg : opcodes := conv_std_logic_vector(12,6); -- Jump to address (Save return value on the stack
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constant call_reg : opcodes := conv_std_logic_vector(12,6); -- Jump to address (Save return value on the stack
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constant ret_reg : opcodes := conv_std_logic_vector(13,6); -- Pop return value from the stack and jump to it
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constant ret_reg : opcodes := conv_std_logic_vector(13,6); -- Pop return value from the stack and jump to it
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-- Logical instructions
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-- Logical instructions
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constant and_reg : opcodes := conv_std_logic_vector(14,6); -- And between to registers
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constant and_reg : opcodes := conv_std_logic_vector(14,6); -- And between to registers
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constant and_val : opcodes := conv_std_logic_vector(15,6); -- And between register and imediate
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constant and_val : opcodes := conv_std_logic_vector(15,6); -- And between register and imediate
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constant or_reg : opcodes := conv_std_logic_vector(16,6); -- Or between to registers
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constant or_reg : opcodes := conv_std_logic_vector(16,6); -- Or between to registers
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constant or_val : opcodes := conv_std_logic_vector(17,6); -- Or between register and imediate
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constant or_val : opcodes := conv_std_logic_vector(17,6); -- Or between register and imediate
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constant xor_reg : opcodes := conv_std_logic_vector(18,6); -- Xor between to registers
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constant xor_reg : opcodes := conv_std_logic_vector(18,6); -- Xor between to registers
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constant xor_val : opcodes := conv_std_logic_vector(19,6); -- Xor between register and imediate
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constant xor_val : opcodes := conv_std_logic_vector(19,6); -- Xor between register and imediate
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constant not_reg : opcodes := conv_std_logic_vector(20,6); -- Not on register
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constant not_reg : opcodes := conv_std_logic_vector(20,6); -- Not on register
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constant shl_reg : opcodes := conv_std_logic_vector(21,6); -- Shift left register (one shift)
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constant shl_reg : opcodes := conv_std_logic_vector(21,6); -- Shift left register (one shift)
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constant shr_reg : opcodes := conv_std_logic_vector(22,6); -- Shift right register (one shift)
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constant shr_reg : opcodes := conv_std_logic_vector(22,6); -- Shift right register (one shift)
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constant rol_reg : opcodes := conv_std_logic_vector(23,6); -- Rotate left register (one rotation)
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constant rol_reg : opcodes := conv_std_logic_vector(23,6); -- Rotate left register (one rotation)
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constant ror_reg : opcodes := conv_std_logic_vector(24,6); -- Rotate right register (one rotation)
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constant ror_reg : opcodes := conv_std_logic_vector(24,6); -- Rotate right register (one rotation)
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constant sbit_reg : opcodes := conv_std_logic_vector(25,6); -- Set bit pointed by register
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constant sbit_reg : opcodes := conv_std_logic_vector(25,6); -- Set bit pointed by register
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constant cbit_reg : opcodes := conv_std_logic_vector(26,6); -- Clear bit pointed by register
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constant cbit_reg : opcodes := conv_std_logic_vector(26,6); -- Clear bit pointed by register
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-- Math operations instructions (unsigned)
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-- Math operations instructions (unsigned)
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constant add_reg : opcodes := conv_std_logic_vector(27,6); -- Add to registers
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constant add_reg : opcodes := conv_std_logic_vector(27,6); -- Add to registers
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constant add_val : opcodes := conv_std_logic_vector(28,6); -- Add register and a imediate value
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constant add_val : opcodes := conv_std_logic_vector(28,6); -- Add register and a imediate value
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constant sub_reg : opcodes := conv_std_logic_vector(29,6); -- Subtract to registers
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constant sub_reg : opcodes := conv_std_logic_vector(29,6); -- Subtract to registers
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constant sub_val : opcodes := conv_std_logic_vector(30,6); -- Subtract register and a imediate value
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constant sub_val : opcodes := conv_std_logic_vector(30,6); -- Subtract register and a imediate value
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constant inc_reg : opcodes := conv_std_logic_vector(31,6); -- Increment register
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constant inc_reg : opcodes := conv_std_logic_vector(31,6); -- Increment register
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constant dec_reg : opcodes := conv_std_logic_vector(32,6); -- Decrement register
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constant dec_reg : opcodes := conv_std_logic_vector(32,6); -- Decrement register
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-- Control opcodes
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-- Control opcodes
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constant nop : opcodes := conv_std_logic_vector(33,6); -- Nop...
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constant nop : opcodes := conv_std_logic_vector(33,6); -- Nop...
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constant halt : opcodes := conv_std_logic_vector(34,6); -- Halt processor
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constant halt : opcodes := conv_std_logic_vector(34,6); -- Halt processor
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end pkgOpenCPU32;
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end pkgOpenCPU32;
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--! Define functions or procedures
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--! Define functions or procedures
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package body pkgOpenCPU32 is
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package body pkgOpenCPU32 is
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function muxPos( a: dpMuxInputs) return std_logic_vector is
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function muxPos( a: dpMuxInputs) return std_logic_vector is
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variable valRet : std_logic_vector(2 downto 0);
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variable valRet : std_logic_vector(2 downto 0);
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begin
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begin
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case a is
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case a is
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when fromMemory => valRet := "000";
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when fromMemory => valRet := "000";
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when fromImediate => valRet := "001";
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when fromImediate => valRet := "001";
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when fromRegFileA => valRet := "010";
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when fromRegFileA => valRet := "010";
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when fromRegFileB => valRet := "011";
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when fromRegFileB => valRet := "011";
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when fromAlu => valRet := "100";
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when fromAlu => valRet := "100";
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end case;
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end case;
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return valRet;
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return valRet;
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end muxPos;
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end muxPos;
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function muxRegPos(a: dpMuxAluIn) return std_logic_vector is
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function muxRegPos(a: dpMuxAluIn) return std_logic_vector is
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variable valRet : std_logic_vector(1 downto 0);
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variable valRet : std_logic_vector(1 downto 0);
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begin
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begin
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case a is
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case a is
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when fromMemory => valRet := "00";
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when fromMemory => valRet := "00";
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when fromImediate => valRet := "01";
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when fromImediate => valRet := "01";
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when fromRegFileA => valRet := "10";
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when fromRegFileA => valRet := "10";
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end case;
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end case;
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return valRet;
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return valRet;
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end muxRegPos;
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end muxRegPos;
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function reg2Num (a: generalRegisters) return integer is
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function reg2Num (a: generalRegisters) return integer is
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variable valRet : integer;
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variable valRet : integer;
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begin
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begin
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case a is
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case a is
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when r0 => valRet := 0;
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when r0 => valRet := 0;
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when r1 => valRet := 1;
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when r1 => valRet := 1;
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when r2 => valRet := 2;
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when r2 => valRet := 2;
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when r3 => valRet := 3;
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when r3 => valRet := 3;
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when r4 => valRet := 4;
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when r4 => valRet := 4;
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when r5 => valRet := 5;
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when r5 => valRet := 5;
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when r6 => valRet := 6;
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when r6 => valRet := 6;
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when r7 => valRet := 7;
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when r7 => valRet := 7;
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when r8 => valRet := 8;
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when r8 => valRet := 8;
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when r9 => valRet := 9;
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when r9 => valRet := 9;
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when r10 => valRet := 10;
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when r10 => valRet := 10;
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when r11 => valRet := 11;
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when r11 => valRet := 11;
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when r12 => valRet := 12;
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when r12 => valRet := 12;
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when r13 => valRet := 13;
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when r13 => valRet := 13;
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when r14 => valRet := 14;
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when r14 => valRet := 14;
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when r15 => valRet := 15;
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when r15 => valRet := 15;
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end case;
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end case;
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return valRet;
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return valRet;
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end reg2Num;
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end reg2Num;
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function Num2reg (a: integer) return generalRegisters is
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function Num2reg (a: integer) return generalRegisters is
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variable valRet : generalRegisters;
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variable valRet : generalRegisters;
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begin
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begin
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case a is
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case a is
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when 0 => valRet := r0;
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when 0 => valRet := r0;
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when 1 => valRet := r1;
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when 1 => valRet := r1;
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when 2 => valRet := r2;
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when 2 => valRet := r2;
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when 3 => valRet := r3;
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when 3 => valRet := r3;
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when 4 => valRet := r4;
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when 4 => valRet := r4;
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when 5 => valRet := r5;
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when 5 => valRet := r5;
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when 6 => valRet := r6;
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when 6 => valRet := r6;
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when 7 => valRet := r7;
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when 7 => valRet := r7;
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when 8 => valRet := r8;
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when 8 => valRet := r8;
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when 9 => valRet := r9;
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when 9 => valRet := r9;
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when 10 => valRet := r10;
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when 10 => valRet := r10;
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when 11 => valRet := r11;
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when 11 => valRet := r11;
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when 12 => valRet := r12;
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when 12 => valRet := r12;
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when 13 => valRet := r13;
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when 13 => valRet := r13;
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when 14 => valRet := r14;
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when 14 => valRet := r14;
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when 15 => valRet := r15;
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when 15 => valRet := r15;
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when others => valRet := r0;
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when others => valRet := r0;
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end case;
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end case;
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return valRet;
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return valRet;
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end Num2reg;
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end Num2reg;
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function opcode2AluOp (opcode : std_logic_vector(5 downto 0)) return aluOps is
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function opcode2AluOp (opcode : std_logic_vector(5 downto 0)) return aluOps is
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variable valRet : aluOps;
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variable valRet : aluOps;
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begin
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begin
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case opcode is
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case opcode is
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when add_reg | add_val => valRet := alu_sum;
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when add_reg | add_val => valRet := alu_sum;
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when sub_reg | sub_val => valRet := alu_sub;
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when sub_reg | sub_val => valRet := alu_sub;
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when inc_reg => valRet := alu_inc;
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when inc_reg => valRet := alu_inc;
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when dec_reg => valRet := alu_dec;
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when dec_reg => valRet := alu_dec;
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when others => valRet := alu_pass;
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when others => valRet := alu_pass;
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end case;
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end case;
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return valRet;
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return valRet;
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end opcode2AluOp;
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end opcode2AluOp;
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-- Code based on Restoring division algorithm
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-- http://vhdlguru.blogspot.com.br/2010/03/vhdl-function-for-division-two-signed.html
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-- http://en.wikipedia.org/wiki/Division_%28digital%29
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function udivision(dividend: unsigned; divisor: unsigned) return unsigned is
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variable a1 : unsigned(dividend'length-1 downto 0);
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variable b1 : unsigned(divisor'length-1 downto 0);
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variable p1 : unsigned(divisor'length downto 0);
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variable i : integer;
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begin
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a1 := dividend;
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b1 := divisor;
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p1 := (others => '0');
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i := 0;
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for i in 0 to divisor'length-1 loop
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p1(divisor'length-1 downto 1) := p1(divisor'length-2 downto 0);
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p1(0) := a1(dividend'length-1);
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a1(dividend'length-1 downto 1) := a1(dividend'length-2 downto 0);
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p1 := p1-b1;
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if(p1(divisor'length-1) ='1') then
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a1(0) :='0';
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p1 := p1+b1;
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else
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a1(0) :='1';
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end if;
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end loop;
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return a1;
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end;
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end pkgOpenCPU32;
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end pkgOpenCPU32;
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