--! @file
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--! @file
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--! @brief Testbench for OpenCpu top design
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--! @brief Testbench for OpenCpu top design
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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LIBRARY ieee;
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LIBRARY ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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--! Adding library for File I/O
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--! Adding library for File I/O
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-- More information on this site:
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-- More information on this site:
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-- http://people.sabanciuniv.edu/erkays/el310/io_10.pdf
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-- http://people.sabanciuniv.edu/erkays/el310/io_10.pdf
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-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm
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-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm
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use std.textio.ALL;
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use std.textio.ALL;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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ENTITY testOpenCpu IS
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ENTITY testOpenCpu IS
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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END testOpenCpu;
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END testOpenCpu;
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--! @brief openCpu Testbench file
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--! @brief openCpu Testbench file
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--! @details This is the top-level test...
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--! @details This is the top-level test...
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ARCHITECTURE behavior OF testOpenCpu IS
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ARCHITECTURE behavior OF testOpenCpu IS
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--! Component declaration to instantiate the Multiplexer circuit
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--! Component declaration to instantiate the Multiplexer circuit
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COMPONENT openCpu
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COMPONENT openCpu
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( rst : in STD_LOGIC; --! Reset signal
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Port ( rst : in STD_LOGIC; --! Reset signal
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clk : in STD_LOGIC; --! Clock signal
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clk : in STD_LOGIC; --! Clock signal
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mem_rd : out STD_LOGIC; --! Main memory Read enable
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mem_rd : out STD_LOGIC; --! Main memory Read enable
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mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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mem_wr : out STD_LOGIC; --! Main memory Write enable
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mem_wr : out STD_LOGIC; --! Main memory Write enable
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mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory
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mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory
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mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory
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mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0'; --! Wire to connect Test signal to component
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signal rst : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal mem_data_in : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal mem_data_in : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal mem_rd : std_logic; --! Wire to connect Test signal to component
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signal mem_rd : std_logic; --! Wire to connect Test signal to component
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signal mem_rd_addr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal mem_rd_addr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal mem_wr : std_logic; --! Wire to connect Test signal to component
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signal mem_wr : std_logic; --! Wire to connect Test signal to component
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signal mem_wr_addr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal mem_wr_addr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal mem_data_out : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal mem_data_out : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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BEGIN
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BEGIN
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--! Instantiate the Unit Under Test (openCpu) (Doxygen bug if it's not commented!)
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--! Instantiate the Unit Under Test (openCpu) (Doxygen bug if it's not commented!)
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uut: openCpu PORT MAP (
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uut: openCpu PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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mem_rd => mem_rd,
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mem_rd => mem_rd,
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mem_rd_addr => mem_rd_addr,
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mem_rd_addr => mem_rd_addr,
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mem_wr => mem_wr,
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mem_wr => mem_wr,
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mem_wr_addr => mem_wr_addr,
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mem_wr_addr => mem_wr_addr,
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mem_data_in => mem_data_in,
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mem_data_in => mem_data_in,
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mem_data_out => mem_data_out
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mem_data_out => mem_data_out
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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file cmdfile: TEXT; -- Define the file 'handle'
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file cmdfile: TEXT; -- Define the file 'handle'
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variable line_in: Line; -- Line buffer
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variable line_in: Line; -- Line buffer
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variable good: boolean; -- Flag to detect a good line read
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variable good: boolean; -- Flag to detect a good line read
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variable instructionCode : std_logic_vector(n downto 0);
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variable instructionCode : std_logic_vector(n downto 0);
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begin
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begin
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-- Reset operation
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-- Reset operation
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REPORT "RESET" SEVERITY NOTE;
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REPORT "RESET" SEVERITY NOTE;
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-- Open source file for reading...
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-- Open source file for reading...
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FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",READ_MODE);
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FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",READ_MODE);
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-- Check end of file
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-- Check end of file
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if endfile(cmdfile) then
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if endfile(cmdfile) then
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assert false report "End of file found..." severity failure;
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assert false report "End of file found..." severity failure;
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end if;
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end if;
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rst <= '1';
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rst <= '1';
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wait for 2 ns;
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wait for 15 ns;
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rst <= '0';
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rst <= '0';
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wait for 2 ns;
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wait for 15 ns;
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while not endfile( cmdfile ) loop
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readline(cmdfile,line_in); -- Read a line from the file
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readline(cmdfile,line_in); -- Read a line from the file
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read(line_in,instructionCode,good); -- Read the CI input
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read(line_in,instructionCode,good); -- Read the CI input
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assert good report "Could not parse the line" severity ERROR;
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assert good report "Could not parse the line" severity ERROR;
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mem_data_in <= instructionCode;
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mem_data_in <= instructionCode;
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wait until mem_rd = '0';
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wait until mem_rd = '0';
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end loop;
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readline(cmdfile,line_in); -- Read a line from the file
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read(line_in,instructionCode,good); -- Read the CI input
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assert good report "Could not parse the line" severity ERROR;
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mem_data_in <= instructionCode;
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wait until mem_rd = '0';
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readline(cmdfile,line_in); -- Read a line from the file
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read(line_in,instructionCode,good); -- Read the CI input
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assert good report "Could not parse the line" severity ERROR;
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mem_data_in <= instructionCode;
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wait until mem_rd = '0';
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readline(cmdfile,line_in); -- Read a line from the file
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read(line_in,instructionCode,good); -- Read the CI input
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assert good report "Could not parse the line" severity ERROR;
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mem_data_in <= instructionCode;
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wait until mem_rd = '0';
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wait until mem_rd = '0';
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readline(cmdfile,line_in); -- Read a line from the file
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read(line_in,instructionCode,good); -- Read the CI input
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assert good report "Could not parse the line" severity ERROR;
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mem_data_in <= instructionCode;
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wait until mem_rd = '0';
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readline(cmdfile,line_in); -- Read a line from the file
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read(line_in,instructionCode,good); -- Read the CI input
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assert good report "Could not parse the line" severity ERROR;
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mem_data_in <= instructionCode;
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wait until mem_rd = '0';
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readline(cmdfile,line_in); -- Read a line from the file
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read(line_in,instructionCode,good); -- Read the CI input
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assert good report "Could not parse the line" severity ERROR;
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mem_data_in <= instructionCode;
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wait for CLK_period;
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-- Finish simulation
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-- Finish simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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