/* MODULE: openfire_regfile
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/* MODULE: openfire_regfile
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DESCRIPTION: This module instantiates two, dual-port aynchronous memories. In
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DESCRIPTION: This module instantiates two, dual-port aynchronous memories. In
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Xilinx parts this synthesizes to Select (LUT-based) RAM. To handle half-word
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Xilinx parts this synthesizes to Select (LUT-based) RAM. To handle half-word
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and byte loads, MUXes and a feedback loop are used such that only the desired
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and byte loads, MUXes and a feedback loop are used such that only the desired
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portions of the previous word are modified.
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portions of the previous word are modified.
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AUTHOR:
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AUTHOR:
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Stephen Douglas Craven
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Stephen Douglas Craven
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Configurable Computing Lab
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Configurable Computing Lab
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Virginia Tech
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Virginia Tech
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scraven@vt.edu
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scraven@vt.edu
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REVISION HISTORY:
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REVISION HISTORY:
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Revision 0.2, 8/10/2005 SDC
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Revision 0.2, 8/10/2005 SDC
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Initial release
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Initial release
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Revision 0.3 27/03/2007 Antonio J Anton
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Revision 0.3 27/03/2007 Antonio J Anton
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Removed memory load unalignment handling (moved to arbitrer)
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Removed memory load unalignment handling (moved to arbitrer)
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COPYRIGHT:
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COPYRIGHT:
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Copyright (c) 2005 Stephen Douglas Craven
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Copyright (c) 2005 Stephen Douglas Craven
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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SOFTWARE.
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*/
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*/
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`include "openfire_define.v"
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`include "openfire_define.v"
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module openfire_regfile (
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module openfire_regfile (
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`ifdef FSL_LINK
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`ifdef FSL_LINK
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fsl_s_data,
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fsl_s_data,
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`endif
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`endif
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reset, clock,
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reset, clock,
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regA_addr, regB_addr, regD_addr, result, pc_regfile,
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regA_addr, regB_addr, regD_addr, result, pc_regfile,
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dmem_data, regfile_input_sel, we_regfile,
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dmem_data, regfile_input_sel, we_regfile,
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we_alu_branch,
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we_alu_branch,
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regA, regB, regD, enable
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regA, regB, regD, enable
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);
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);
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input reset; // From top level
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input reset; // From top level
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input clock;
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input clock;
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input [4:0] regA_addr; // From DECODE
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input [4:0] regA_addr; // From DECODE
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input [4:0] regB_addr;
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input [4:0] regB_addr;
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input [4:0] regD_addr;
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input [4:0] regD_addr;
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input [3:0] regfile_input_sel;
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input [3:0] regfile_input_sel;
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input we_alu_branch;
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input we_alu_branch;
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input [31:0] result; // From EXECUTE
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input [31:0] result; // From EXECUTE
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input [`A_SPACE+1:0] pc_regfile;
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input [`A_SPACE+1:0] pc_regfile;
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input we_regfile;
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input we_regfile;
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input enable;
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input enable;
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input [31:0] dmem_data; // From DMEM
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input [31:0] dmem_data; // From DMEM
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`ifdef FSL_LINK
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`ifdef FSL_LINK
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input [31:0] fsl_s_data; // From FSL
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input [31:0] fsl_s_data; // From FSL
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`endif
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`endif
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output [31:0] regA;
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output [31:0] regA;
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output [31:0] regB;
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output [31:0] regB;
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output [31:0] regD;
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output [31:0] regD;
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reg [31:0] input_data;
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reg [31:0] input_data;
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wire write_en;
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wire write_en;
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wire [31:0] extended_pc;
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wire [31:0] extended_pc;
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// Write to registers on we_alu_branch OR we_load
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// Write to registers on we_alu_branch OR we_load
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// UNLESS r0 is the target. r0 MUST always be zero. (|regD_addr) isolates R0
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// UNLESS r0 is the target. r0 MUST always be zero. (|regD_addr) isolates R0
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// Allow write on reset to load r0 with zero.
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// Allow write on reset to load r0 with zero.
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assign write_en = reset ? 1'b1 : (we_alu_branch | we_regfile) & (|regD_addr) & enable;
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assign write_en = reset ? 1'b1 : (we_alu_branch | we_regfile) & (|regD_addr) & enable;
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// extended PC to datapath width
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// extended PC to datapath width
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assign extended_pc[31:`A_SPACE+2] = 0;
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assign extended_pc[31:`A_SPACE+2] = 0;
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assign extended_pc[`A_SPACE+1:0] = pc_regfile;
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assign extended_pc[`A_SPACE+1:0] = pc_regfile;
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// Input select into REGFILE
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// Input select into REGFILE
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always@(
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always@(
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`ifdef FSL_LINK
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`ifdef FSL_LINK
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fsl_s_data or
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fsl_s_data or
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`endif
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`endif
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dmem_data or extended_pc or result or regfile_input_sel or write_en or clock
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dmem_data or extended_pc or result or regfile_input_sel or write_en or clock
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)
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)
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begin
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begin
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case(regfile_input_sel)
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case(regfile_input_sel)
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`RF_dmem_byte: input_data <= dmem_data[31:24]; // update byte
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`RF_dmem_byte: input_data <= dmem_data[31:24]; // update byte
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`RF_dmem_halfword: input_data <= dmem_data[31:16]; // update halfword
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`RF_dmem_halfword: input_data <= dmem_data[31:16]; // update halfword
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`RF_dmem_wholeword: input_data <= dmem_data; // update word
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`RF_dmem_wholeword: input_data <= dmem_data; // update word
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`RF_alu_result: input_data <= result;
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`RF_alu_result: input_data <= result;
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`RF_pc: input_data <= extended_pc;
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`RF_pc: input_data <= extended_pc;
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`ifdef FSL_LINK
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`ifdef FSL_LINK
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`RF_fsl: input_data <= fsl_s_data;
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`RF_fsl: input_data <= fsl_s_data;
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`endif
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`endif
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default:
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default:
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begin
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begin
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input_data <= 0;
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input_data <= 0;
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//synthesis translate_off
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//synthesis translate_off
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if(write_en & ~clock & (regfile_input_sel != `RF_zero)) $display("ERROR! REGFILE input selector set to illegal value %d at PC %x", regfile_input_sel, pc_regfile);
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if(write_en & ~clock & (regfile_input_sel != `RF_zero)) $display("ERROR! REGFILE input selector set to illegal value %d at PC %x", regfile_input_sel, pc_regfile);
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//synthesis translate_on
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//synthesis translate_on
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end
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end
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endcase
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endcase
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end
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end
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// We need a 3-port register file -- create from 2, 2-port SRAMs
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// We need a 3-port register file -- create from 2, 2-port SRAMs
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// Tie write ports together
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// Tie write ports together
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openfire_rf_sram RF_BANK0 (
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openfire_rf_sram RF_BANK0 (
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.clock(clock),
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.clock(clock),
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.read_addr(regA_addr),
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.read_addr(regA_addr),
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.write_addr(regD_addr),
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.write_addr(regD_addr),
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.data_in(input_data),
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.data_in(input_data),
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.we(write_en),
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.we(write_en),
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.read_data_out(regA),
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.read_data_out(regA),
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.write_data_out(regD)
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.write_data_out(regD)
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);
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);
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openfire_rf_sram RF_BANK1 (
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openfire_rf_sram RF_BANK1 (
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.clock(clock),
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.clock(clock),
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.read_addr(regB_addr),
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.read_addr(regB_addr),
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.write_addr(regD_addr),
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.write_addr(regD_addr),
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.data_in(input_data),
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.data_in(input_data),
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.we(write_en),
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.we(write_en),
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.read_data_out(regB),
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.read_data_out(regB),
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.write_data_out( )
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.write_data_out( )
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);
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);
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endmodule
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endmodule
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