/* MODULE: openfire soc
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/* MODULE: openfire soc
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DESCRIPTION: Contains top-level SOC
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DESCRIPTION: Contains top-level SOC
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AUTHOR:
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AUTHOR:
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Antonio J. Anton
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Antonio J. Anton
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Anro Ingenieros (www.anro-ingenieros.com)
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Anro Ingenieros (www.anro-ingenieros.com)
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aj@anro-ingenieros.com
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aj@anro-ingenieros.com
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REVISION HISTORY:
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REVISION HISTORY:
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Revision 1.0, 26/03/2007
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Revision 1.0, 26/03/2007
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Initial release
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Initial release
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COPYRIGHT:
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COPYRIGHT:
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Copyright (c) 2007 Antonio J. Anton
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Copyright (c) 2007 Antonio J. Anton
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.*/
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SOFTWARE.*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "openfire_define.v"
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`include "openfire_define.v"
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module openfire_soc(
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module openfire_soc(
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`ifndef SP3SK_USERIO
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`ifndef SP3SK_USERIO
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rst, // if no SP3SK IOs, then we need a reset signal
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rst, // if no SP3SK IOs, then we need a reset signal
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`endif
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`endif
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`ifdef SP3SK_USERIO
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`ifdef SP3SK_USERIO
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leds, drivers_n, segments_n, pushbuttons, switches,
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leds, drivers_n, segments_n, pushbuttons, switches,
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`endif
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`endif
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`ifdef UART1_ENABLE
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`ifdef UART1_ENABLE
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tx1, rx1,
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tx1, rx1,
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`endif
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`endif
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`ifdef UART2_ENABLE
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`ifdef UART2_ENABLE
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tx2, rx2,
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tx2, rx2,
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`endif
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`endif
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`ifdef SP3SK_SRAM
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`ifdef SP3SK_SRAM
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ram_addr, ram_oe_n, ram_we_n,
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ram_addr, ram_oe_n, ram_we_n,
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ram1_io, ram1_ce_n, ram1_ub_n, ram1_lb_n,
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ram1_io, ram1_ce_n, ram1_ub_n, ram1_lb_n,
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ram2_io, ram2_ce_n, ram2_ub_n, ram2_lb_n,
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ram2_io, ram2_ce_n, ram2_ub_n, ram2_lb_n,
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`endif
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`endif
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`ifdef SP3SK_VGA
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`ifdef SP3SK_VGA
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r, g, b, hsync_n, vsync_n,
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r, g, b, hsync_n, vsync_n,
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`endif
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`endif
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`ifdef SP3SK_PROM_DATA
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`ifdef SP3SK_PROM_DATA
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prom_din, prom_cclk, prom_reset_n,
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prom_din, prom_cclk, prom_reset_n,
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`endif
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`endif
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// tx_ultrasonidos_p, tx_ultrasonidos_n, rx_ultrasonidos,
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// tx_ultrasonidos_p, tx_ultrasonidos_n, rx_ultrasonidos,
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// spi_clk, spi_datain, spi_dataout,
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// spi_clk, spi_datain, spi_dataout,
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// spi_cs_1, spi_cs_2, spi_cs_3, spi_cs_4,
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// spi_cs_1, spi_cs_2, spi_cs_3, spi_cs_4,
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// i2c_clk, i2c_data,
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// i2c_clk, i2c_data,
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clk_50mhz
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clk_50mhz
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);
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);
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`ifndef SP3SK_USERIO
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`ifndef SP3SK_USERIO
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input rst; // external RST (active HIGH)
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input rst; // external RST (active HIGH)
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`endif
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`endif
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input clk_50mhz; // board clock 50 MHZ
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input clk_50mhz; // board clock 50 MHZ
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`ifdef SP3SK_USERIO
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`ifdef SP3SK_USERIO
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output [7:0] leds; // onboard LEDS
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output [7:0] leds; // onboard LEDS
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output [3:0] drivers_n; // 7segments element's driver (negated)
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output [3:0] drivers_n; // 7segments element's driver (negated)
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output [7:0] segments_n; // display segment
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output [7:0] segments_n; // display segment
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input [3:0] pushbuttons; // 4 push-buttons
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input [3:0] pushbuttons; // 4 push-buttons
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input [7:0] switches; // 8 switches
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input [7:0] switches; // 8 switches
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`endif
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`endif
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`ifdef UART1_ENABLE
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`ifdef UART1_ENABLE
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input rx1; // RS232 rx
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input rx1; // RS232 rx
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output tx1; // RS232 tx
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output tx1; // RS232 tx
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`endif
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`endif
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`ifdef UART2_ENABLE
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`ifdef UART2_ENABLE
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input rx2; // RS232 rx #2
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input rx2; // RS232 rx #2
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output tx2; // RS232 tx #2
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output tx2; // RS232 tx #2
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`endif
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`endif
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`ifdef SP3SK_SRAM
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`ifdef SP3SK_SRAM
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output [17:0] ram_addr; // SRAM ADDR (256K @)
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output [17:0] ram_addr; // SRAM ADDR (256K @)
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output ram_oe_n; // OE_N shared by 2 IC
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output ram_oe_n; // OE_N shared by 2 IC
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output ram_we_n; // WE_N shared by 2 IC
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output ram_we_n; // WE_N shared by 2 IC
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inout [15:0] ram1_io; // I/O data port SRAM1
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inout [15:0] ram1_io; // I/O data port SRAM1
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output ram1_ce_n; // SRAM1 CE_N chip enable
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output ram1_ce_n; // SRAM1 CE_N chip enable
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output ram1_ub_n; // UB_N upper byte select
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output ram1_ub_n; // UB_N upper byte select
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output ram1_lb_n; // LB_N lower byte select
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output ram1_lb_n; // LB_N lower byte select
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inout [15:0] ram2_io; // I/O data port SRAM2
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inout [15:0] ram2_io; // I/O data port SRAM2
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output ram2_ce_n; // SRAM2 CE_N chip enable
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output ram2_ce_n; // SRAM2 CE_N chip enable
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output ram2_ub_n; // UB_N upper byte select
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output ram2_ub_n; // UB_N upper byte select
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output ram2_lb_n; // LB_N lower byte select
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output ram2_lb_n; // LB_N lower byte select
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`endif
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`endif
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`ifdef SP3SK_VGA
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`ifdef SP3SK_VGA
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output r, g, b; // VGA components (1 bit per component)
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output r, g, b; // VGA components (1 bit per component)
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output hsync_n; // VGA hsync_n
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output hsync_n; // VGA hsync_n
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output vsync_n; // VGA vsync_n
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output vsync_n; // VGA vsync_n
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`endif
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`endif
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`ifdef SP3SK_PROM_DATA
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`ifdef SP3SK_PROM_DATA
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input prom_din;
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input prom_din;
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output prom_cclk;
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output prom_cclk;
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output prom_reset_n;
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output prom_reset_n;
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`endif
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`endif
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//output tx_ultrasonidos_p; // application specific ports
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//output tx_ultrasonidos_p; // application specific ports
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//output tx_ultrasonidos_n;
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//output tx_ultrasonidos_n;
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//input rx_ultrasonidos;
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//input rx_ultrasonidos;
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//output spi_clk;
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//output spi_clk;
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//input spi_datain;
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//input spi_datain;
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//output spi_dataout;
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//output spi_dataout;
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//output spi_cs_1;
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//output spi_cs_1;
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//output spi_cs_2;
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//output spi_cs_2;
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//output spi_cs_3;
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//output spi_cs_3;
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//output spi_cs_4;
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//output spi_cs_4;
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//inout i2c_clk;
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//inout i2c_clk;
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//inout i2c_data;
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//inout i2c_data;
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// -------- connections ------------
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// -------- connections ------------
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`ifdef SP3SK_USERIO
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`ifdef SP3SK_USERIO
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wire rst = pushbuttons[3]; // reset generated from a push button
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wire rst = pushbuttons[3]; // reset generated from a push button
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`endif
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`endif
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wire [31:0] imem_data; // ports to/from CPU
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wire [31:0] imem_data; // ports to/from CPU
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wire [31:0] imem_addr;
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wire [31:0] imem_addr;
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wire [31:0] dmem_data2mem;
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wire [31:0] dmem_data2mem;
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wire [31:0] dmem_data2cpu;
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wire [31:0] dmem_data2cpu;
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wire [31:0] dmem_addr;
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wire [31:0] dmem_addr;
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wire [1:0] dmem_input_sel; // 0=byte, 1=hw, 2=word
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wire [1:0] dmem_input_sel; // 0=byte, 1=hw, 2=word
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wire [3:0] data_selector; // maps each byte in a word (msb..lsb)
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wire [3:0] data_selector; // maps each byte in a word (msb..lsb)
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wire dmem_we; // request data write
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wire dmem_we; // request data write
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wire dmem_re; // request data read
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wire dmem_re; // request data read
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wire imem_re; // request instruction read
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wire imem_re; // request instruction read
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wire [31:0] dmem_data_frombram; // arbitrer to/from BRAM
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wire [31:0] dmem_data_frombram; // arbitrer to/from BRAM
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wire [31:0] dmem_data_tobram;
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wire [31:0] dmem_data_tobram;
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wire dmem_we_bram;
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wire dmem_we_bram;
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wire [31:0] imem_data_frombram;
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wire [31:0] imem_data_frombram;
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`ifdef SP3SK_IODEVICES
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`ifdef SP3SK_IODEVICES
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wire [31:0] dmem_data_fromio; // arbitrer to/from IO-SPACE
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wire [31:0] dmem_data_fromio; // arbitrer to/from IO-SPACE
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wire [31:0] dmem_data_toio;
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wire [31:0] dmem_data_toio;
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wire dmem_we_io;
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wire dmem_we_io;
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wire dmem_re_io;
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wire dmem_re_io;
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`endif
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`endif
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`ifdef IO_MULTICYCLE
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`ifdef IO_MULTICYCLE
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wire io_done; // handle multicycle i/o operations
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wire io_done; // handle multicycle i/o operations
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`endif
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`endif
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wire imem_done; // operation on imem completed
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wire imem_done; // operation on imem completed
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wire dmem_done; // operation on dmem completed
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wire dmem_done; // operation on dmem completed
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`ifdef SP3SK_SRAM
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`ifdef SP3SK_SRAM
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wire [31:0] sram_data2mem1;
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wire [31:0] sram_data2mem1;
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wire [31:0] sram_data2cpu1;
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wire [31:0] sram_data2cpu1;
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wire sram_re1, sram_we1, sram_done1;
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wire sram_re1, sram_we1, sram_done1;
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wire [31:0] sram_data2cpu2;
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wire [31:0] sram_data2cpu2;
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wire sram_re2, sram_done2;
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wire sram_re2, sram_done2;
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wire [17:0] sram_addr3; // port #3 other uses
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wire [17:0] sram_addr3; // port #3 other uses
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wire [31:0] sram_data2cpu3;
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wire [31:0] sram_data2cpu3;
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wire sram_re3, sram_done3;
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wire sram_re3, sram_done3;
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`endif
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`endif
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`ifdef CLK_25MHZ // cpu clock generation
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`ifdef CLK_25MHZ // cpu clock generation
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reg clk;
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reg clk;
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//synthesis translate_off
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//synthesis translate_off
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initial clk = 0;
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initial clk = 0;
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//synthesis translate_on
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//synthesis translate_on
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always @(posedge clk_50mhz) clk <= ~clk; // 25mhz clock
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always @(posedge clk_50mhz) clk <= ~clk; // 25mhz clock
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`else
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`else
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wire clk = clk_50mhz; // 50mhz clock
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wire clk = clk_50mhz; // 50mhz clock
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`endif
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`endif
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`ifdef ENABLE_INTERRUPTS
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`ifdef ENABLE_INTERRUPTS
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wire interrupt; // interrupt line
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wire interrupt; // interrupt line
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`endif
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`endif
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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wire dmem_alignment_exception;
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wire dmem_alignment_exception;
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`endif
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`endif
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// --------- instantiation of the SoC ----------------
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// --------- instantiation of the SoC ----------------
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openfire_cpu CPU( // openfire CPU
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openfire_cpu CPU( // openfire CPU
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.clock(clk),
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.clock(clk),
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.reset(rst),
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.reset(rst),
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`ifdef ENABLE_INTERRUPTS
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`ifdef ENABLE_INTERRUPTS
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.interrupt(interrupt),
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.interrupt(interrupt),
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`endif
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`endif
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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.dmem_alignment_exception(dmem_alignment_exception),
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.dmem_alignment_exception(dmem_alignment_exception),
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`endif
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`endif
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.dmem_addr(dmem_addr),
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.dmem_addr(dmem_addr),
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.dmem_data_in(dmem_data2cpu),
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.dmem_data_in(dmem_data2cpu),
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.dmem_data_out(dmem_data2mem),
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.dmem_data_out(dmem_data2mem),
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.dmem_we(dmem_we),
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.dmem_we(dmem_we),
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.dmem_re(dmem_re),
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.dmem_re(dmem_re),
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.dmem_input_sel(dmem_input_sel),
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.dmem_input_sel(dmem_input_sel),
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.dmem_done(dmem_done),
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.dmem_done(dmem_done),
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.imem_addr(imem_addr),
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.imem_addr(imem_addr),
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.imem_data_in(imem_data),
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.imem_data_in(imem_data),
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.imem_re(imem_re),
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.imem_re(imem_re),
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.imem_done(imem_done)
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.imem_done(imem_done)
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);
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);
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openfire_arbitrer ARBITRER( // bus arbitrer
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openfire_arbitrer ARBITRER( // bus arbitrer
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`ifdef SP3SK_SRAM
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`ifdef SP3SK_SRAM
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.sram_data2mem(sram_data2mem1),
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.sram_data2mem(sram_data2mem1),
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.sram_data2cpu(sram_data2cpu1),
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.sram_data2cpu(sram_data2cpu1),
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.sram_dmem_re(sram_re1),
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.sram_dmem_re(sram_re1),
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.sram_dmem_we(sram_we1),
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.sram_dmem_we(sram_we1),
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.sram_dmem_done(sram_done1),
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.sram_dmem_done(sram_done1),
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.sram_ins2cpu(sram_data2cpu2),
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.sram_ins2cpu(sram_data2cpu2),
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.sram_imem_re(sram_re2),
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.sram_imem_re(sram_re2),
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.sram_imem_done(sram_done2),
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.sram_imem_done(sram_done2),
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`endif
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`endif
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`ifdef IO_MULTICYCLE
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`ifdef IO_MULTICYCLE
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.dmem_done_io(io_done),
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.dmem_done_io(io_done),
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`endif
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`endif
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`ifdef SP3SK_IODEVICES
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`ifdef SP3SK_IODEVICES
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.dmem_we_io(dmem_we_io),
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.dmem_we_io(dmem_we_io),
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.dmem_re_io(dmem_re_io),
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.dmem_re_io(dmem_re_io),
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.dmem_data_fromio(dmem_data_fromio),
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.dmem_data_fromio(dmem_data_fromio),
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.dmem_data_toio(dmem_data_toio),
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.dmem_data_toio(dmem_data_toio),
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`endif
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`endif
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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.dmem_alignment_exception(dmem_alignment_exception),
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.dmem_alignment_exception(dmem_alignment_exception),
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`endif
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`endif
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.clock(clk),
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.clock(clk),
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.reset(rst),
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.reset(rst),
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.imem_done(imem_done),
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.imem_done(imem_done),
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.dmem_done(dmem_done),
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.dmem_done(dmem_done),
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.dmem_address(dmem_addr),
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.dmem_address(dmem_addr),
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.dmem_data_out(dmem_data2cpu),
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.dmem_data_out(dmem_data2cpu),
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.dmem_data_in(dmem_data2mem),
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.dmem_data_in(dmem_data2mem),
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.dmem_re(dmem_re),
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.dmem_re(dmem_re),
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.dmem_we(dmem_we),
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.dmem_we(dmem_we),
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.dmem_input_sel(dmem_input_sel),
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.dmem_input_sel(dmem_input_sel),
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.data_selector(data_selector),
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.data_selector(data_selector),
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.imem_address(imem_addr),
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.imem_address(imem_addr),
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.imem_data(imem_data),
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.imem_data(imem_data),
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.imem_re(imem_re),
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.imem_re(imem_re),
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.dmem_data_frombram(dmem_data_frombram),
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.dmem_data_frombram(dmem_data_frombram),
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.dmem_data_tobram(dmem_data_tobram),
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.dmem_data_tobram(dmem_data_tobram),
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.dmem_we_bram(dmem_we_bram),
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.dmem_we_bram(dmem_we_bram),
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.imem_data_frombram(imem_data_frombram)
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.imem_data_frombram(imem_data_frombram)
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);
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);
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`ifdef SP3SK_IODEVICES
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`ifdef SP3SK_IODEVICES
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openfire_iospace IOSPACE( // i/o space manager
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openfire_iospace IOSPACE( // i/o space manager
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`ifdef SP3SK_USERIO
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`ifdef SP3SK_USERIO
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.leds(leds),
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.leds(leds),
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.drivers_n(drivers_n),
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.drivers_n(drivers_n),
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.segments_n(segments_n),
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.segments_n(segments_n),
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.pushbuttons(pushbuttons),
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.pushbuttons(pushbuttons),
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.switches(switches),
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.switches(switches),
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`endif
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`endif
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`ifdef UART1_ENABLE
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`ifdef UART1_ENABLE
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.tx1(tx1),
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.tx1(tx1),
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.rx1(rx1),
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.rx1(rx1),
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`endif
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`endif
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`ifdef UART2_ENABLE
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`ifdef UART2_ENABLE
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.tx2(tx2),
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.tx2(tx2),
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.rx2(rx2),
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.rx2(rx2),
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`endif
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`endif
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`ifdef SP3SK_PROM_DATA
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`ifdef SP3SK_PROM_DATA
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.prom_din(prom_din),
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.prom_din(prom_din),
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.prom_cclk(prom_cclk),
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.prom_cclk(prom_cclk),
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.prom_reset_n(prom_reset_n),
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.prom_reset_n(prom_reset_n),
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`endif
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`endif
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`ifdef ENABLE_INTERRUPTS
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`ifdef ENABLE_INTERRUPTS
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.interrupt(interrupt),
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.interrupt(interrupt),
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`endif
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`endif
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`ifdef IO_MULTICYCLE
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`ifdef IO_MULTICYCLE
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.done(io_done),
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.done(io_done),
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`endif
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`endif
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.clk(~clk),
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.clk(~clk),
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.rst(rst),
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.rst(rst),
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.addr(dmem_addr[`IO_SIZE+1:2]),
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.addr(dmem_addr[`IO_SIZE+1:2]),
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.data_in(dmem_data_toio),
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.data_in(dmem_data_toio),
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.data_out(dmem_data_fromio),
|
.data_out(dmem_data_fromio),
|
.read(dmem_re_io),
|
.read(dmem_re_io),
|
.write(dmem_we_io)
|
.write(dmem_we_io)
|
);
|
);
|
`endif
|
`endif
|
|
|
openfire_bootram BOOTRAM( // boot ram (block ram)
|
openfire_bootram BOOTRAM( // boot ram (block ram)
|
.rst(rst),
|
.rst(rst),
|
.clk(~clk),
|
.clk(~clk),
|
.ins_addr( imem_addr[12:2] ),
|
.ins_addr( imem_addr[12:2] ),
|
.ins_output(imem_data_frombram),
|
.ins_output(imem_data_frombram),
|
.data_sel(data_selector),
|
.data_sel(data_selector),
|
.data_we(dmem_we_bram),
|
.data_we(dmem_we_bram),
|
.data_addr( dmem_addr[12:2] ),
|
.data_addr( dmem_addr[12:2] ),
|
.data_input(dmem_data_tobram),
|
.data_input(dmem_data_tobram),
|
.data_output(dmem_data_frombram)
|
.data_output(dmem_data_frombram)
|
);
|
);
|
|
|
`ifdef SP3SK_SRAM // sram controller
|
`ifdef SP3SK_SRAM // sram controller
|
sram_controller sram_256kx32(
|
sram_controller sram_256kx32(
|
.rst(rst), .clk(~clk), // controller at full speed
|
.rst(rst), .clk(~clk), // controller at full speed
|
|
|
.ram_addr(ram_addr), .ram_oe_n(ram_oe_n), .ram_we_n(ram_we_n), // sp3sk sram interface
|
.ram_addr(ram_addr), .ram_oe_n(ram_oe_n), .ram_we_n(ram_we_n), // sp3sk sram interface
|
.ram1_io(ram1_io), .ram1_ce_n(ram1_ce_n), .ram1_ub_n(ram1_ub_n), .ram1_lb_n(ram1_lb_n),
|
.ram1_io(ram1_io), .ram1_ce_n(ram1_ce_n), .ram1_ub_n(ram1_ub_n), .ram1_lb_n(ram1_lb_n),
|
.ram2_io(ram2_io), .ram2_ce_n(ram2_ce_n), .ram2_ub_n(ram2_ub_n), .ram2_lb_n(ram2_lb_n),
|
.ram2_io(ram2_io), .ram2_ce_n(ram2_ce_n), .ram2_ub_n(ram2_ub_n), .ram2_lb_n(ram2_lb_n),
|
|
|
.addr1( dmem_addr[19:2] ), // dmem port (read/write) byte capable
|
.addr1( dmem_addr[19:2] ), // dmem port (read/write) byte capable
|
.data2mem1(sram_data2mem1),
|
.data2mem1(sram_data2mem1),
|
.data2cpu1(sram_data2cpu1),
|
.data2cpu1(sram_data2cpu1),
|
.re1(sram_re1),
|
.re1(sram_re1),
|
.we1(sram_we1),
|
.we1(sram_we1),
|
.select1(data_selector),
|
.select1(data_selector),
|
.done1(sram_done1),
|
.done1(sram_done1),
|
|
|
.addr2( imem_addr[19:2] ), // imem port (read only) word only
|
.addr2( imem_addr[19:2] ), // imem port (read only) word only
|
.data2cpu2(sram_data2cpu2),
|
.data2cpu2(sram_data2cpu2),
|
.re2(sram_re2),
|
.re2(sram_re2),
|
.done2(sram_done2),
|
.done2(sram_done2),
|
|
|
.addr3(sram_addr3), // aux port (read only) word only
|
.addr3(sram_addr3), // aux port (read only) word only
|
.data2cpu3(sram_data2cpu3),
|
.data2cpu3(sram_data2cpu3),
|
.re3(sram_re3),
|
.re3(sram_re3),
|
.done3(sram_done3)
|
.done3(sram_done3)
|
);
|
);
|
`endif
|
`endif
|
|
|
`ifdef SP3SK_VGA // vga module
|
`ifdef SP3SK_VGA // vga module
|
vga_controller VGA(
|
vga_controller VGA(
|
.reset(rst),
|
.reset(rst),
|
.cpu_clk(clk), // for the sram fetch module
|
.cpu_clk(clk), // for the sram fetch module
|
.pixel_clk(clk), // should be 25MHz for 640x480 video mode
|
.pixel_clk(clk), // should be 25MHz for 640x480 video mode
|
.hsync_n(hsync_n),
|
.hsync_n(hsync_n),
|
.vsync_n(vsync_n),
|
.vsync_n(vsync_n),
|
.red(r),
|
.red(r),
|
.green(g),
|
.green(g),
|
.blue(b),
|
.blue(b),
|
.ram_pointer(sram_addr3),
|
.ram_pointer(sram_addr3),
|
.ram_data(sram_data2cpu3),
|
.ram_data(sram_data2cpu3),
|
.req(sram_re3),
|
.req(sram_re3),
|
.rdy(sram_done3)
|
.rdy(sram_done3)
|
);
|
);
|
`endif
|
`endif
|
|
|
`include "openfire_debug.v"
|
`include "openfire_debug.v"
|
endmodule
|
endmodule
|
|
|
|
|
