//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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// Copyright (C) 2015 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: ogfx_gpu_reg.v
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// *File Name: ogfx_gpu_reg.v
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//
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//
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// *Module Description:
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// *Module Description:
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// Configuration registers of the Graphic-Processing unit
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// Configuration registers of the Graphic-Processing unit
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev$
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// $Rev$
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// $LastChangedBy$
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// $LastChangedBy$
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// $LastChangedDate$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`ifdef OGFX_NO_INCLUDE
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`else
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`else
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`include "openGFX430_defines.v"
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`include "openGFX430_defines.v"
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`endif
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`endif
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module ogfx_gpu_reg (
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module ogfx_gpu_reg (
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// OUTPUTs
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// OUTPUTs
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cfg_dst_px_addr_o, // Destination pixel address configuration
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cfg_dst_px_addr_o, // Destination pixel address configuration
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cfg_dst_cl_swp_o, // Destination Column/Line-Swap configuration
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cfg_dst_cl_swp_o, // Destination Column/Line-Swap configuration
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cfg_dst_x_swp_o, // Destination X-Swap configuration
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cfg_dst_x_swp_o, // Destination X-Swap configuration
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cfg_dst_y_swp_o, // Destination Y-Swap configuration
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cfg_dst_y_swp_o, // Destination Y-Swap configuration
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cfg_fill_color_o, // Fill color (for rectangle fill operation)
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cfg_fill_color_o, // Fill color (for rectangle fill operation)
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cfg_pix_op_sel_o, // Pixel operation to be performed during the copy
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cfg_pix_op_sel_o, // Pixel operation to be performed during the copy
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cfg_rec_width_o, // Rectangle width configuration
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cfg_rec_width_o, // Rectangle width configuration
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cfg_rec_height_o, // Rectangle height configuration
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cfg_rec_height_o, // Rectangle height configuration
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cfg_src_px_addr_o, // Source pixel address configuration
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cfg_src_px_addr_o, // Source pixel address configuration
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cfg_src_cl_swp_o, // Source Column/Line-Swap configuration
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cfg_src_cl_swp_o, // Source Column/Line-Swap configuration
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cfg_src_x_swp_o, // Source X-Swap configuration
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cfg_src_x_swp_o, // Source X-Swap configuration
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cfg_src_y_swp_o, // Source Y-Swap configuration
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cfg_src_y_swp_o, // Source Y-Swap configuration
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cfg_transparent_color_o, // Transparent color (for rectangle transparent copy operation)
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cfg_transparent_color_o, // Transparent color (for rectangle transparent copy operation)
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gpu_cmd_done_evt_o, // GPU command done event
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gpu_cmd_done_evt_o, // GPU command done event
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gpu_cmd_error_evt_o, // GPU command error event
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gpu_cmd_error_evt_o, // GPU command error event
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gpu_get_data_o, // GPU get next data
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gpu_get_data_o, // GPU get next data
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exec_fill_o, // Rectangle fill on going
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exec_fill_o, // Rectangle fill on going
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exec_copy_o, // Rectangle copy on going
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exec_copy_o, // Rectangle copy on going
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exec_copy_trans_o, // Rectangle transparent copy on going
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exec_copy_trans_o, // Rectangle transparent copy on going
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trig_exec_o, // Trigger rectangle execution
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trig_exec_o, // Trigger rectangle execution
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// INPUTs
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// INPUTs
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mclk, // Main system clock
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mclk, // Main system clock
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puc_rst, // Main system reset
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puc_rst, // Main system reset
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gpu_data_i, // GPU data
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gpu_data_i, // GPU data
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gpu_data_avail_i, // GPU data available
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gpu_data_avail_i, // GPU data available
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gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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gpu_enable_i, // GPU enable
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gpu_enable_i, // GPU enable
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gpu_exec_done_i // GPU execution done
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gpu_exec_done_i // GPU execution done
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [`APIX_MSB:0] cfg_dst_px_addr_o; // Destination pixel address configuration
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output [`APIX_MSB:0] cfg_dst_px_addr_o; // Destination pixel address configuration
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output cfg_dst_cl_swp_o; // Destination Column/Line-Swap configuration
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output cfg_dst_cl_swp_o; // Destination Column/Line-Swap configuration
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output cfg_dst_x_swp_o; // Destination X-Swap configuration
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output cfg_dst_x_swp_o; // Destination X-Swap configuration
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output cfg_dst_y_swp_o; // Destination Y-Swap configuration
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output cfg_dst_y_swp_o; // Destination Y-Swap configuration
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output [15:0] cfg_fill_color_o; // Fill color (for rectangle fill operation)
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output [15:0] cfg_fill_color_o; // Fill color (for rectangle fill operation)
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output [3:0] cfg_pix_op_sel_o; // Pixel operation to be performed during the copy
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output [3:0] cfg_pix_op_sel_o; // Pixel operation to be performed during the copy
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output [`LPIX_MSB:0] cfg_rec_width_o; // Rectangle width configuration
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output [`LPIX_MSB:0] cfg_rec_width_o; // Rectangle width configuration
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output [`LPIX_MSB:0] cfg_rec_height_o; // Rectangle height configuration
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output [`LPIX_MSB:0] cfg_rec_height_o; // Rectangle height configuration
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output [`APIX_MSB:0] cfg_src_px_addr_o; // Source pixel address configuration
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output [`APIX_MSB:0] cfg_src_px_addr_o; // Source pixel address configuration
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output cfg_src_cl_swp_o; // Source Column/Line-Swap configuration
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output cfg_src_cl_swp_o; // Source Column/Line-Swap configuration
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output cfg_src_x_swp_o; // Source X-Swap configuration
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output cfg_src_x_swp_o; // Source X-Swap configuration
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output cfg_src_y_swp_o; // Source Y-Swap configuration
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output cfg_src_y_swp_o; // Source Y-Swap configuration
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output [15:0] cfg_transparent_color_o; // Transparent color (for rectangle transparent copy operation)
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output [15:0] cfg_transparent_color_o; // Transparent color (for rectangle transparent copy operation)
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output gpu_cmd_done_evt_o; // GPU command done event
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output gpu_cmd_done_evt_o; // GPU command done event
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output gpu_cmd_error_evt_o; // GPU command error event
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output gpu_cmd_error_evt_o; // GPU command error event
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output gpu_get_data_o; // GPU get next data
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output gpu_get_data_o; // GPU get next data
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output exec_fill_o; // Rectangle fill on going
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output exec_fill_o; // Rectangle fill on going
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output exec_copy_o; // Rectangle copy on going
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output exec_copy_o; // Rectangle copy on going
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output exec_copy_trans_o; // Rectangle transparent copy on going
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output exec_copy_trans_o; // Rectangle transparent copy on going
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output trig_exec_o; // Trigger rectangle execution
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output trig_exec_o; // Trigger rectangle execution
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// INPUTs
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// INPUTs
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//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input [15:0] gpu_data_i; // GPU data
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input [15:0] gpu_data_i; // GPU data
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input gpu_data_avail_i; // GPU data available
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input gpu_data_avail_i; // GPU data available
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input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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input gpu_enable_i; // GPU enable
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input gpu_enable_i; // GPU enable
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input gpu_exec_done_i; // GPU execution done
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input gpu_exec_done_i; // GPU execution done
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//=============================================================================
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//=============================================================================
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// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
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// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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// Video modes decoding
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// Video modes decoding
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wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);
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wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);
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wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);
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wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);
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wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);
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wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);
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wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);
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wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);
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wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp | gfx_mode_2_bpp | gfx_mode_1_bpp);
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wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp | gfx_mode_2_bpp | gfx_mode_1_bpp);
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// Remaining wires/registers
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// Remaining wires/registers
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reg exec_fill_o;
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reg exec_fill_o;
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reg exec_copy_o;
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reg exec_copy_o;
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reg exec_copy_trans_o;
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reg exec_copy_trans_o;
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reg [1:0] src_offset_sel;
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reg [1:0] src_offset_sel;
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reg src_x_swp;
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reg src_x_swp;
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reg src_y_swp;
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reg src_y_swp;
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reg src_cl_swp;
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reg src_cl_swp;
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reg [3:0] pix_op_sel;
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reg [3:0] pix_op_sel;
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reg [1:0] dst_offset_sel;
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reg [1:0] dst_offset_sel;
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reg dst_x_swp;
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reg dst_x_swp;
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reg dst_y_swp;
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reg dst_y_swp;
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reg dst_cl_swp;
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reg dst_cl_swp;
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reg [3:0] reg_access;
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reg [3:0] reg_access;
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wire [3:0] reg_access_nxt;
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wire [3:0] reg_access_nxt;
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reg [15:0] fill_color;
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reg [15:0] fill_color;
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reg [`LPIX_MSB:0] rec_width;
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reg [`LPIX_MSB:0] rec_width;
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reg [`LPIX_MSB:0] rec_height;
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reg [`LPIX_MSB:0] rec_height;
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wire [`APIX_MSB:0] src_px_addr;
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wire [`APIX_MSB:0] src_px_addr;
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wire [`APIX_MSB:0] src_px_addr_align;
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wire [`APIX_MSB:0] src_px_addr_align;
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wire [`APIX_MSB:0] dst_px_addr;
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wire [`APIX_MSB:0] dst_px_addr;
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wire [`APIX_MSB:0] dst_px_addr_align;
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wire [`APIX_MSB:0] dst_px_addr_align;
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wire [`APIX_MSB:0] of0_addr;
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wire [`APIX_MSB:0] of0_addr;
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wire [`APIX_MSB:0] of1_addr;
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wire [`APIX_MSB:0] of1_addr;
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wire [`APIX_MSB:0] of2_addr;
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wire [`APIX_MSB:0] of2_addr;
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wire [`APIX_MSB:0] of3_addr;
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wire [`APIX_MSB:0] of3_addr;
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reg [15:0] transparent_color;
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reg [15:0] transparent_color;
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wire [`APIX_MSB:0] src_offset_addr;
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wire [`APIX_MSB:0] src_offset_addr;
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wire [`APIX_MSB:0] dst_offset_addr;
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wire [`APIX_MSB:0] dst_offset_addr;
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//=============================================================================
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//=============================================================================
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// 2) GPU COMMAND STATE MACHINE
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// 2) GPU COMMAND STATE MACHINE
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//=============================================================================
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//=============================================================================
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//
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//
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// EXEC_FILL - Execute rectangle fill command
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// EXEC_FILL - Execute rectangle fill command
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// {2'b00, reserved<4:0>, pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
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// {2'b00, reserved<4:0>, pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
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// {fill_color[15:0]}
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// {fill_color[15:0]}
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//
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//
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// EXEC_COPY - Execute rectangle copy command
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// EXEC_COPY - Execute rectangle copy command
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// {2'b01, src_offset[1:0], src_X-Swp, src_Y-Swp, src_CL-Swp, pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
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// {2'b01, src_offset[1:0], src_X-Swp, src_Y-Swp, src_CL-Swp, pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
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//
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//
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// EXEC_COPY_TRANS - Execute rectangle copy with transparency command
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// EXEC_COPY_TRANS - Execute rectangle copy with transparency command
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// {2'b10, src_offset[1:0], src_X-Swp, src_Y-Swp, src_CL-Swp, pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
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// {2'b10, src_offset[1:0], src_X-Swp, src_Y-Swp, src_CL-Swp, pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
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//
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//
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// REC_WIDTH - Set rectangle width
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// REC_WIDTH - Set rectangle width
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// {4'b1100, width[11:0]}
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// {4'b1100, width[11:0]}
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//
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//
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// REC_HEIGHT - Set rectangle height
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// REC_HEIGHT - Set rectangle height
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// {4'b1101, height[11:0]}
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// {4'b1101, height[11:0]}
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//
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//
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// SRC_PX_ADDR - Set source address
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// SRC_PX_ADDR - Set source address
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// {4'b1111, 2'b10, 10'b0000000000}
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// {4'b1111, 2'b10, 10'b0000000000}
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// {addr[31:16] }
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// {addr[15:0] }
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// {addr[15:0] }
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// {addr[31:16] }
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//
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//
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// DST_PX_ADDR - Set destination address
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// DST_PX_ADDR - Set destination address
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// {4'b1111, 2'b10, 10'b0000000001}
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// {4'b1111, 2'b10, 10'b0000000001}
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// {addr[31:16] }
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// {addr[15:0] }
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// {addr[15:0] }
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// {addr[31:16] }
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//
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//
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// OF0_ADDR - Set address offset 0
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// OF0_ADDR - Set address offset 0
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// {4'b1111, 2'b10, 10'b0000010000}
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// {4'b1111, 2'b10, 10'b0000010000}
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// {addr[31:16] }
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// {addr[15:0] }
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// {addr[15:0] }
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// {addr[31:16] }
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//
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//
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// OF1_ADDR - Set address offset 1
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// OF1_ADDR - Set address offset 1
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// {4'b1111, 2'b10, 10'b0000010001}
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// {4'b1111, 2'b10, 10'b0000010001}
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// {addr[31:16] }
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// {addr[15:0] }
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// {addr[15:0] }
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// {addr[31:16] }
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//
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//
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// OF2_ADDR - Set address offset 2
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// OF2_ADDR - Set address offset 2
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// {4'b1111, 2'b10, 10'b0000010010}
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// {4'b1111, 2'b10, 10'b0000010010}
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// {addr[31:16] }
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// {addr[15:0] }
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// {addr[15:0] }
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// {addr[31:16] }
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//
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//
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// OF3_ADDR - Set address offset 3
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// OF3_ADDR - Set address offset 3
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// {4'b1111, 2'b10, 10'b0000010011}
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// {4'b1111, 2'b10, 10'b0000010011}
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// {addr[31:16] }
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// {addr[15:0] }
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// {addr[15:0] }
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// {addr[31:16] }
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//
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//
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// SET_FILL - Set fill color
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// SET_FILL - Set fill color
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// {4'b1111, 2'b01, 10'b0000100000}
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// {4'b1111, 2'b01, 10'b0000100000}
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// {fill_color[15:0] }
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// {fill_color[15:0] }
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//
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//
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// SET_TRANSPARENT - Set transparent color
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// SET_TRANSPARENT - Set transparent color
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// {4'b1111, 2'b01, 10'b0000100001}
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// {4'b1111, 2'b01, 10'b0000100001}
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// {transparent_color[15:0] }
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// {transparent_color[15:0] }
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// State definition
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// State definition
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parameter CMD_WAIT = 4'h0;
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parameter CMD_WAIT = 4'h0;
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parameter CMD_READ = 4'h1;
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parameter CMD_READ = 4'h1;
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parameter DATA1B_WAIT = 4'h2;
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parameter DATA1B_WAIT = 4'h2;
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parameter DATA1B_READ = 4'h3;
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parameter DATA1B_READ = 4'h3;
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parameter DATA2B1_WAIT = 4'h4;
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parameter DATA2B1_WAIT = 4'h4;
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parameter DATA2B1_READ = 4'h5;
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parameter DATA2B1_READ = 4'h5;
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parameter DATA2B2_WAIT = 4'h6;
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parameter DATA2B2_WAIT = 4'h6;
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parameter DATA2B2_READ = 4'h7;
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parameter DATA2B2_READ = 4'h7;
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parameter EXEC_START = 4'h8;
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parameter EXEC_START = 4'h8;
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parameter EXEC = 4'h9;
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parameter EXEC = 4'h9;
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parameter ERROR = 4'hA;
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parameter ERROR = 4'hA;
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// State machine
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// State machine
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reg [3:0] gpu_state;
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reg [3:0] gpu_state;
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reg [3:0] gpu_state_nxt;
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reg [3:0] gpu_state_nxt;
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// Arcs control
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// Arcs control
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wire cmd_available = gpu_data_avail_i;
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wire cmd_available = gpu_data_avail_i;
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wire cmd_not_valid = ((gpu_data_i[15:14]!= `OP_EXEC_FILL ) &
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wire cmd_not_valid = ((gpu_data_i[15:14]!= `OP_EXEC_FILL ) &
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(gpu_data_i[15:14]!= `OP_EXEC_COPY ) &
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(gpu_data_i[15:14]!= `OP_EXEC_COPY ) &
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(gpu_data_i[15:14]!= `OP_EXEC_COPY_TRANS) &
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(gpu_data_i[15:14]!= `OP_EXEC_COPY_TRANS) &
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(gpu_data_i[15:12]!= `OP_REC_WIDTH ) &
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(gpu_data_i[15:12]!= `OP_REC_WIDTH ) &
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(gpu_data_i[15:12]!= `OP_REC_HEIGHT ) &
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(gpu_data_i[15:12]!= `OP_REC_HEIGHT ) &
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(gpu_data_i[15:0] != `OP_SRC_PX_ADDR ) &
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(gpu_data_i[15:0] != `OP_SRC_PX_ADDR ) &
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(gpu_data_i[15:0] != `OP_DST_PX_ADDR ) &
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(gpu_data_i[15:0] != `OP_DST_PX_ADDR ) &
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(gpu_data_i[15:0] != `OP_OF0_ADDR ) &
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(gpu_data_i[15:0] != `OP_OF0_ADDR ) &
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(gpu_data_i[15:0] != `OP_OF1_ADDR ) &
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(gpu_data_i[15:0] != `OP_OF1_ADDR ) &
|
(gpu_data_i[15:0] != `OP_OF2_ADDR ) &
|
(gpu_data_i[15:0] != `OP_OF2_ADDR ) &
|
(gpu_data_i[15:0] != `OP_OF3_ADDR ) &
|
(gpu_data_i[15:0] != `OP_OF3_ADDR ) &
|
(gpu_data_i[15:0] != `OP_SET_FILL ) &
|
(gpu_data_i[15:0] != `OP_SET_FILL ) &
|
(gpu_data_i[15:0] != `OP_SET_TRANSPARENT));
|
(gpu_data_i[15:0] != `OP_SET_TRANSPARENT));
|
|
|
wire cmd_has_1b_data = (gpu_data_i[15:14]== `OP_EXEC_FILL ) |
|
wire cmd_has_1b_data = (gpu_data_i[15:14]== `OP_EXEC_FILL ) |
|
(gpu_data_i[15:0] == `OP_SET_FILL ) |
|
(gpu_data_i[15:0] == `OP_SET_FILL ) |
|
(gpu_data_i[15:0] == `OP_SET_TRANSPARENT);
|
(gpu_data_i[15:0] == `OP_SET_TRANSPARENT);
|
|
|
wire cmd_has_2b_data = (gpu_data_i[15:0] == `OP_SRC_PX_ADDR ) |
|
wire cmd_has_2b_data = (gpu_data_i[15:0] == `OP_SRC_PX_ADDR ) |
|
(gpu_data_i[15:0] == `OP_DST_PX_ADDR ) |
|
(gpu_data_i[15:0] == `OP_DST_PX_ADDR ) |
|
(gpu_data_i[15:0] == `OP_OF0_ADDR ) |
|
(gpu_data_i[15:0] == `OP_OF0_ADDR ) |
|
(gpu_data_i[15:0] == `OP_OF1_ADDR ) |
|
(gpu_data_i[15:0] == `OP_OF1_ADDR ) |
|
(gpu_data_i[15:0] == `OP_OF2_ADDR ) |
|
(gpu_data_i[15:0] == `OP_OF2_ADDR ) |
|
(gpu_data_i[15:0] == `OP_OF3_ADDR );
|
(gpu_data_i[15:0] == `OP_OF3_ADDR );
|
|
|
wire cmd_has_exec = exec_fill_o | exec_copy_o | exec_copy_trans_o;
|
wire cmd_has_exec = exec_fill_o | exec_copy_o | exec_copy_trans_o;
|
|
|
wire data_available = gpu_data_avail_i;
|
wire data_available = gpu_data_avail_i;
|
|
|
|
|
// State transition
|
// State transition
|
always @(gpu_state or cmd_available or cmd_not_valid or cmd_has_1b_data or cmd_has_2b_data or cmd_has_exec or data_available or gpu_exec_done_i)
|
always @(gpu_state or cmd_available or cmd_not_valid or cmd_has_1b_data or cmd_has_2b_data or cmd_has_exec or data_available or gpu_exec_done_i)
|
case (gpu_state)
|
case (gpu_state)
|
CMD_WAIT : gpu_state_nxt = cmd_available ? CMD_READ : CMD_WAIT ;
|
CMD_WAIT : gpu_state_nxt = cmd_available ? CMD_READ : CMD_WAIT ;
|
CMD_READ : gpu_state_nxt = cmd_not_valid ? ERROR :
|
CMD_READ : gpu_state_nxt = cmd_not_valid ? ERROR :
|
cmd_has_1b_data ? DATA1B_WAIT :
|
cmd_has_1b_data ? DATA1B_WAIT :
|
cmd_has_2b_data ? DATA2B1_WAIT :
|
cmd_has_2b_data ? DATA2B1_WAIT :
|
cmd_has_exec ? EXEC_START : CMD_WAIT ;
|
cmd_has_exec ? EXEC_START : CMD_WAIT ;
|
|
|
DATA1B_WAIT : gpu_state_nxt = data_available ? DATA1B_READ : DATA1B_WAIT ;
|
DATA1B_WAIT : gpu_state_nxt = data_available ? DATA1B_READ : DATA1B_WAIT ;
|
DATA1B_READ : gpu_state_nxt = cmd_has_exec ? EXEC_START : CMD_WAIT ;
|
DATA1B_READ : gpu_state_nxt = cmd_has_exec ? EXEC_START : CMD_WAIT ;
|
|
|
DATA2B1_WAIT : gpu_state_nxt = data_available ? DATA2B1_READ : DATA2B1_WAIT ;
|
DATA2B1_WAIT : gpu_state_nxt = data_available ? DATA2B1_READ : DATA2B1_WAIT ;
|
DATA2B1_READ : gpu_state_nxt = DATA2B2_WAIT ;
|
DATA2B1_READ : gpu_state_nxt = DATA2B2_WAIT ;
|
|
|
DATA2B2_WAIT : gpu_state_nxt = data_available ? DATA2B2_READ : DATA2B2_WAIT ;
|
DATA2B2_WAIT : gpu_state_nxt = data_available ? DATA2B2_READ : DATA2B2_WAIT ;
|
DATA2B2_READ : gpu_state_nxt = cmd_has_exec ? EXEC_START : CMD_WAIT ;
|
DATA2B2_READ : gpu_state_nxt = cmd_has_exec ? EXEC_START : CMD_WAIT ;
|
|
|
EXEC_START : gpu_state_nxt = gpu_exec_done_i ? CMD_WAIT : EXEC ;
|
EXEC_START : gpu_state_nxt = gpu_exec_done_i ? CMD_WAIT : EXEC ;
|
EXEC : gpu_state_nxt = gpu_exec_done_i ? CMD_WAIT : EXEC ;
|
EXEC : gpu_state_nxt = gpu_exec_done_i ? CMD_WAIT : EXEC ;
|
ERROR : gpu_state_nxt = ERROR ;
|
ERROR : gpu_state_nxt = ERROR ;
|
// pragma coverage off
|
// pragma coverage off
|
default : gpu_state_nxt = CMD_WAIT ;
|
default : gpu_state_nxt = CMD_WAIT ;
|
// pragma coverage on
|
// pragma coverage on
|
endcase
|
endcase
|
|
|
|
|
// State machine
|
// State machine
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) gpu_state <= CMD_WAIT;
|
if (puc_rst) gpu_state <= CMD_WAIT;
|
else if (~gpu_enable_i) gpu_state <= CMD_WAIT;
|
else if (~gpu_enable_i) gpu_state <= CMD_WAIT;
|
else gpu_state <= gpu_state_nxt;
|
else gpu_state <= gpu_state_nxt;
|
|
|
|
|
// Event generation, fifo data request
|
// Event generation, fifo data request
|
assign gpu_cmd_done_evt_o = (gpu_state!=ERROR) & (gpu_state!=CMD_WAIT) & (gpu_state_nxt==CMD_WAIT);
|
assign gpu_cmd_done_evt_o = (gpu_state!=ERROR) & (gpu_state!=CMD_WAIT) & (gpu_state_nxt==CMD_WAIT);
|
assign gpu_cmd_error_evt_o = (gpu_state==ERROR);
|
assign gpu_cmd_error_evt_o = (gpu_state==ERROR);
|
assign gpu_get_data_o = (gpu_state==CMD_READ) | (gpu_state==DATA1B_READ) | (gpu_state==DATA2B1_READ) | (gpu_state==DATA2B2_READ);
|
assign gpu_get_data_o = (gpu_state==CMD_READ) | (gpu_state==DATA1B_READ) | (gpu_state==DATA2B1_READ) | (gpu_state==DATA2B2_READ);
|
|
|
// Execution triggers
|
// Execution triggers
|
assign trig_exec_o = (exec_fill_o |
|
assign trig_exec_o = (exec_fill_o |
|
exec_copy_o |
|
exec_copy_o |
|
exec_copy_trans_o) & (gpu_state==EXEC_START);
|
exec_copy_trans_o) & (gpu_state==EXEC_START);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 3) CONFIGURATION REGISTERS
|
// 3) CONFIGURATION REGISTERS
|
//=============================================================================
|
//=============================================================================
|
|
|
// Detect execution commands
|
// Detect execution commands
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) exec_fill_o <= 1'b0;
|
if (puc_rst) exec_fill_o <= 1'b0;
|
else if ((gpu_state==CMD_WAIT) & cmd_available) exec_fill_o <= (gpu_data_i[15:14]==`OP_EXEC_FILL);
|
else if ((gpu_state==CMD_WAIT) & cmd_available) exec_fill_o <= (gpu_data_i[15:14]==`OP_EXEC_FILL);
|
else if ((gpu_state_nxt==CMD_WAIT) ) exec_fill_o <= 1'b0;
|
else if ((gpu_state_nxt==CMD_WAIT) ) exec_fill_o <= 1'b0;
|
|
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) exec_copy_o <= 1'b0;
|
if (puc_rst) exec_copy_o <= 1'b0;
|
else if ((gpu_state==CMD_WAIT) & cmd_available) exec_copy_o <= (gpu_data_i[15:14]==`OP_EXEC_COPY);
|
else if ((gpu_state==CMD_WAIT) & cmd_available) exec_copy_o <= (gpu_data_i[15:14]==`OP_EXEC_COPY);
|
else if ((gpu_state_nxt==CMD_WAIT) ) exec_copy_o <= 1'b0;
|
else if ((gpu_state_nxt==CMD_WAIT) ) exec_copy_o <= 1'b0;
|
|
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) exec_copy_trans_o <= 1'b0;
|
if (puc_rst) exec_copy_trans_o <= 1'b0;
|
else if ((gpu_state==CMD_WAIT) & cmd_available) exec_copy_trans_o <= (gpu_data_i[15:14]==`OP_EXEC_COPY_TRANS);
|
else if ((gpu_state==CMD_WAIT) & cmd_available) exec_copy_trans_o <= (gpu_data_i[15:14]==`OP_EXEC_COPY_TRANS);
|
else if ((gpu_state_nxt==CMD_WAIT) ) exec_copy_trans_o <= 1'b0;
|
else if ((gpu_state_nxt==CMD_WAIT) ) exec_copy_trans_o <= 1'b0;
|
|
|
// Detect register accesses
|
// Detect register accesses
|
parameter REG_EXEC_FILL = 4'h1;
|
parameter REG_EXEC_FILL = 4'h1;
|
parameter REG_REC_WIDTH = 4'h2;
|
parameter REG_REC_WIDTH = 4'h2;
|
parameter REG_REC_HEIGHT = 4'h3;
|
parameter REG_REC_HEIGHT = 4'h3;
|
parameter REG_SRC_PX_ADDR = 4'h4;
|
parameter REG_SRC_PX_ADDR = 4'h4;
|
parameter REG_DST_PX_ADDR = 4'h5;
|
parameter REG_DST_PX_ADDR = 4'h5;
|
parameter REG_OF0_ADDR = 4'h6;
|
parameter REG_OF0_ADDR = 4'h6;
|
parameter REG_OF1_ADDR = 4'h7;
|
parameter REG_OF1_ADDR = 4'h7;
|
parameter REG_OF2_ADDR = 4'h8;
|
parameter REG_OF2_ADDR = 4'h8;
|
parameter REG_OF3_ADDR = 4'h9;
|
parameter REG_OF3_ADDR = 4'h9;
|
parameter REG_SET_FILL = 4'hA;
|
parameter REG_SET_FILL = 4'hA;
|
parameter REG_SET_TRANSPARENT = 4'hB;
|
parameter REG_SET_TRANSPARENT = 4'hB;
|
|
|
assign reg_access_nxt = ({4{gpu_data_i[15:14]== `OP_EXEC_FILL }} & REG_EXEC_FILL ) |
|
assign reg_access_nxt = ({4{gpu_data_i[15:14]== `OP_EXEC_FILL }} & REG_EXEC_FILL ) |
|
({4{gpu_data_i[15:12]== `OP_REC_WIDTH }} & REG_REC_WIDTH ) |
|
({4{gpu_data_i[15:12]== `OP_REC_WIDTH }} & REG_REC_WIDTH ) |
|
({4{gpu_data_i[15:12]== `OP_REC_HEIGHT }} & REG_REC_HEIGHT ) |
|
({4{gpu_data_i[15:12]== `OP_REC_HEIGHT }} & REG_REC_HEIGHT ) |
|
({4{gpu_data_i[15:0] == `OP_SRC_PX_ADDR }} & REG_SRC_PX_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_SRC_PX_ADDR }} & REG_SRC_PX_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_DST_PX_ADDR }} & REG_DST_PX_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_DST_PX_ADDR }} & REG_DST_PX_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_OF0_ADDR }} & REG_OF0_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_OF0_ADDR }} & REG_OF0_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_OF1_ADDR }} & REG_OF1_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_OF1_ADDR }} & REG_OF1_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_OF2_ADDR }} & REG_OF2_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_OF2_ADDR }} & REG_OF2_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_OF3_ADDR }} & REG_OF3_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_OF3_ADDR }} & REG_OF3_ADDR ) |
|
({4{gpu_data_i[15:0] == `OP_SET_FILL }} & REG_SET_FILL ) |
|
({4{gpu_data_i[15:0] == `OP_SET_FILL }} & REG_SET_FILL ) |
|
({4{gpu_data_i[15:0] == `OP_SET_TRANSPARENT}} & REG_SET_TRANSPARENT) ;
|
({4{gpu_data_i[15:0] == `OP_SET_TRANSPARENT}} & REG_SET_TRANSPARENT) ;
|
|
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) reg_access <= 4'h0;
|
if (puc_rst) reg_access <= 4'h0;
|
else if (gpu_state==CMD_READ) reg_access <= reg_access_nxt;
|
else if (gpu_state==CMD_READ) reg_access <= reg_access_nxt;
|
else if (gpu_state_nxt==CMD_WAIT) reg_access <= 4'h0;
|
else if (gpu_state_nxt==CMD_WAIT) reg_access <= 4'h0;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 4) CONFIGURATION REGISTERS
|
// 4) CONFIGURATION REGISTERS
|
//=============================================================================
|
//=============================================================================
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// EXECUTION CONFIG Register
|
// EXECUTION CONFIG Register
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
wire exec_all_cfg_wr = (exec_fill_o | exec_copy_o | exec_copy_trans_o) & (gpu_state==CMD_READ);
|
wire exec_all_cfg_wr = (exec_fill_o | exec_copy_o | exec_copy_trans_o) & (gpu_state==CMD_READ);
|
wire exec_src_cfg_wr = ( exec_copy_o | exec_copy_trans_o) & (gpu_state==CMD_READ);
|
wire exec_src_cfg_wr = ( exec_copy_o | exec_copy_trans_o) & (gpu_state==CMD_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst)
|
if (puc_rst)
|
begin
|
begin
|
src_offset_sel <= 2'b00;
|
src_offset_sel <= 2'b00;
|
src_x_swp <= 1'b0;
|
src_x_swp <= 1'b0;
|
src_y_swp <= 1'b0;
|
src_y_swp <= 1'b0;
|
src_cl_swp <= 1'b0;
|
src_cl_swp <= 1'b0;
|
end
|
end
|
else if (exec_src_cfg_wr)
|
else if (exec_src_cfg_wr)
|
begin
|
begin
|
src_offset_sel <= gpu_data_i[13:12];
|
src_offset_sel <= gpu_data_i[13:12];
|
src_x_swp <= gpu_data_i[11];
|
src_x_swp <= gpu_data_i[11];
|
src_y_swp <= gpu_data_i[10];
|
src_y_swp <= gpu_data_i[10];
|
src_cl_swp <= gpu_data_i[9];
|
src_cl_swp <= gpu_data_i[9];
|
end
|
end
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst)
|
if (puc_rst)
|
begin
|
begin
|
pix_op_sel <= 4'b0000;
|
pix_op_sel <= 4'b0000;
|
dst_offset_sel <= 2'b00;
|
dst_offset_sel <= 2'b00;
|
dst_x_swp <= 1'b0;
|
dst_x_swp <= 1'b0;
|
dst_y_swp <= 1'b0;
|
dst_y_swp <= 1'b0;
|
dst_cl_swp <= 1'b0;
|
dst_cl_swp <= 1'b0;
|
end
|
end
|
else if (exec_all_cfg_wr)
|
else if (exec_all_cfg_wr)
|
begin
|
begin
|
pix_op_sel <= gpu_data_i[8:5];
|
pix_op_sel <= gpu_data_i[8:5];
|
dst_offset_sel <= gpu_data_i[4:3];
|
dst_offset_sel <= gpu_data_i[4:3];
|
dst_x_swp <= gpu_data_i[2];
|
dst_x_swp <= gpu_data_i[2];
|
dst_y_swp <= gpu_data_i[1];
|
dst_y_swp <= gpu_data_i[1];
|
dst_cl_swp <= gpu_data_i[0];
|
dst_cl_swp <= gpu_data_i[0];
|
end
|
end
|
|
|
assign cfg_src_x_swp_o = src_x_swp;
|
assign cfg_src_x_swp_o = src_x_swp;
|
assign cfg_src_y_swp_o = src_y_swp;
|
assign cfg_src_y_swp_o = src_y_swp;
|
assign cfg_src_cl_swp_o = src_cl_swp;
|
assign cfg_src_cl_swp_o = src_cl_swp;
|
assign cfg_pix_op_sel_o = pix_op_sel;
|
assign cfg_pix_op_sel_o = pix_op_sel;
|
assign cfg_dst_x_swp_o = dst_x_swp;
|
assign cfg_dst_x_swp_o = dst_x_swp;
|
assign cfg_dst_y_swp_o = dst_y_swp;
|
assign cfg_dst_y_swp_o = dst_y_swp;
|
assign cfg_dst_cl_swp_o = dst_cl_swp;
|
assign cfg_dst_cl_swp_o = dst_cl_swp;
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// FILL_COLOR Register
|
// FILL_COLOR Register
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
wire fill_color_wr = ((reg_access==REG_EXEC_FILL) |
|
wire fill_color_wr = ((reg_access==REG_EXEC_FILL) |
|
(reg_access==REG_SET_FILL ) ) & (gpu_state==DATA1B_READ);
|
(reg_access==REG_SET_FILL ) ) & (gpu_state==DATA1B_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) fill_color <= 16'h0000;
|
if (puc_rst) fill_color <= 16'h0000;
|
else if (fill_color_wr) fill_color <= gpu_data_i;
|
else if (fill_color_wr) fill_color <= gpu_data_i;
|
|
|
assign cfg_fill_color_o = fill_color;
|
assign cfg_fill_color_o = fill_color;
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// REC_WIDTH Register
|
// REC_WIDTH Register
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
wire rec_width_wr = (reg_access_nxt==REG_REC_WIDTH) & (gpu_state==CMD_READ);
|
wire rec_width_wr = (reg_access_nxt==REG_REC_WIDTH) & (gpu_state==CMD_READ);
|
|
|
wire [`LPIX_MSB:0] rec_w_h_nxt = (|gpu_data_i[`LPIX_MSB:0]) ? gpu_data_i[`LPIX_MSB:0] :
|
wire [`LPIX_MSB:0] rec_w_h_nxt = (|gpu_data_i[`LPIX_MSB:0]) ? gpu_data_i[`LPIX_MSB:0] :
|
{{`LPIX_MSB{1'b0}}, 1'b1};
|
{{`LPIX_MSB{1'b0}}, 1'b1};
|
|
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) rec_width <= {{`LPIX_MSB{1'b0}}, 1'b1};
|
if (puc_rst) rec_width <= {{`LPIX_MSB{1'b0}}, 1'b1};
|
else if (rec_width_wr) rec_width <= rec_w_h_nxt;
|
else if (rec_width_wr) rec_width <= rec_w_h_nxt;
|
|
|
assign cfg_rec_width_o = rec_width;
|
assign cfg_rec_width_o = rec_width;
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// REC_HEIGHT Register
|
// REC_HEIGHT Register
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
wire rec_height_wr = (reg_access_nxt==REG_REC_HEIGHT) & (gpu_state==CMD_READ);
|
wire rec_height_wr = (reg_access_nxt==REG_REC_HEIGHT) & (gpu_state==CMD_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) rec_height <= {{`LPIX_MSB{1'b0}}, 1'b1};
|
if (puc_rst) rec_height <= {{`LPIX_MSB{1'b0}}, 1'b1};
|
else if (rec_height_wr) rec_height <= rec_w_h_nxt;
|
else if (rec_height_wr) rec_height <= rec_w_h_nxt;
|
|
|
assign cfg_rec_height_o = rec_height;
|
assign cfg_rec_height_o = rec_height;
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// SRC_PX_ADDR_HI Register
|
// SRC_PX_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] src_px_addr_hi;
|
reg [`APIX_HI_MSB:0] src_px_addr_hi;
|
|
|
wire src_px_addr_hi_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B1_READ);
|
wire src_px_addr_hi_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) src_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) src_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (src_px_addr_hi_wr) src_px_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (src_px_addr_hi_wr) src_px_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// SRC_PX_ADDR_LO Register
|
// SRC_PX_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] src_px_addr_lo;
|
reg [`APIX_LO_MSB:0] src_px_addr_lo;
|
|
|
wire src_px_addr_lo_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B2_READ);
|
wire src_px_addr_lo_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) src_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) src_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (src_px_addr_lo_wr) src_px_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (src_px_addr_lo_wr) src_px_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign src_px_addr = {src_px_addr_hi[`APIX_HI_MSB:0], src_px_addr_lo};
|
assign src_px_addr = {src_px_addr_hi[`APIX_HI_MSB:0], src_px_addr_lo};
|
`else
|
`else
|
assign src_px_addr = {src_px_addr_lo[`APIX_LO_MS:0]};
|
assign src_px_addr = {src_px_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
assign src_px_addr_align = src_px_addr + src_offset_addr;
|
assign src_px_addr_align = src_px_addr + src_offset_addr;
|
assign cfg_src_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {src_px_addr_align[`APIX_MSB:0] } |
|
assign cfg_src_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {src_px_addr_align[`APIX_MSB:0] } |
|
{`APIX_MSB+1{gfx_mode_2_bpp }} & {src_px_addr_align[`APIX_MSB-1:0], 1'b0 } |
|
{`APIX_MSB+1{gfx_mode_2_bpp }} & {src_px_addr_align[`APIX_MSB-1:0], 1'b0 } |
|
{`APIX_MSB+1{gfx_mode_4_bpp }} & {src_px_addr_align[`APIX_MSB-2:0], 2'b00 } |
|
{`APIX_MSB+1{gfx_mode_4_bpp }} & {src_px_addr_align[`APIX_MSB-2:0], 2'b00 } |
|
{`APIX_MSB+1{gfx_mode_8_bpp }} & {src_px_addr_align[`APIX_MSB-3:0], 3'b000 } |
|
{`APIX_MSB+1{gfx_mode_8_bpp }} & {src_px_addr_align[`APIX_MSB-3:0], 3'b000 } |
|
{`APIX_MSB+1{gfx_mode_16_bpp}} & {src_px_addr_align[`APIX_MSB-4:0], 4'b0000} ;
|
{`APIX_MSB+1{gfx_mode_16_bpp}} & {src_px_addr_align[`APIX_MSB-4:0], 4'b0000} ;
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// DST_PX_ADDR_HI Register
|
// DST_PX_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] dst_px_addr_hi;
|
reg [`APIX_HI_MSB:0] dst_px_addr_hi;
|
|
|
wire dst_px_addr_hi_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B1_READ);
|
wire dst_px_addr_hi_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) dst_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) dst_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (dst_px_addr_hi_wr) dst_px_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (dst_px_addr_hi_wr) dst_px_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// DST_PX_ADDR_LO Register
|
// DST_PX_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] dst_px_addr_lo;
|
reg [`APIX_LO_MSB:0] dst_px_addr_lo;
|
|
|
wire dst_px_addr_lo_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B2_READ);
|
wire dst_px_addr_lo_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) dst_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) dst_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (dst_px_addr_lo_wr) dst_px_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (dst_px_addr_lo_wr) dst_px_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign dst_px_addr = {dst_px_addr_hi[`APIX_HI_MSB:0], dst_px_addr_lo};
|
assign dst_px_addr = {dst_px_addr_hi[`APIX_HI_MSB:0], dst_px_addr_lo};
|
`else
|
`else
|
assign dst_px_addr = {dst_px_addr_lo[`APIX_LO_MS:0]};
|
assign dst_px_addr = {dst_px_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
assign dst_px_addr_align = dst_px_addr + dst_offset_addr;
|
assign dst_px_addr_align = dst_px_addr + dst_offset_addr;
|
assign cfg_dst_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {dst_px_addr_align[`APIX_MSB:0] } |
|
assign cfg_dst_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {dst_px_addr_align[`APIX_MSB:0] } |
|
{`APIX_MSB+1{gfx_mode_2_bpp }} & {dst_px_addr_align[`APIX_MSB-1:0], 1'b0 } |
|
{`APIX_MSB+1{gfx_mode_2_bpp }} & {dst_px_addr_align[`APIX_MSB-1:0], 1'b0 } |
|
{`APIX_MSB+1{gfx_mode_4_bpp }} & {dst_px_addr_align[`APIX_MSB-2:0], 2'b00 } |
|
{`APIX_MSB+1{gfx_mode_4_bpp }} & {dst_px_addr_align[`APIX_MSB-2:0], 2'b00 } |
|
{`APIX_MSB+1{gfx_mode_8_bpp }} & {dst_px_addr_align[`APIX_MSB-3:0], 3'b000 } |
|
{`APIX_MSB+1{gfx_mode_8_bpp }} & {dst_px_addr_align[`APIX_MSB-3:0], 3'b000 } |
|
{`APIX_MSB+1{gfx_mode_16_bpp}} & {dst_px_addr_align[`APIX_MSB-4:0], 4'b0000} ;
|
{`APIX_MSB+1{gfx_mode_16_bpp}} & {dst_px_addr_align[`APIX_MSB-4:0], 4'b0000} ;
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF0_ADDR_HI Register
|
// OF0_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] of0_addr_hi;
|
reg [`APIX_HI_MSB:0] of0_addr_hi;
|
|
|
wire of0_addr_hi_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B1_READ);
|
wire of0_addr_hi_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of0_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) of0_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (of0_addr_hi_wr) of0_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (of0_addr_hi_wr) of0_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF0_ADDR_LO Register
|
// OF0_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] of0_addr_lo;
|
reg [`APIX_LO_MSB:0] of0_addr_lo;
|
|
|
wire of0_addr_lo_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B2_READ);
|
wire of0_addr_lo_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of0_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) of0_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (of0_addr_lo_wr) of0_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (of0_addr_lo_wr) of0_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign of0_addr = {of0_addr_hi[`APIX_HI_MSB:0], of0_addr_lo};
|
assign of0_addr = {of0_addr_hi[`APIX_HI_MSB:0], of0_addr_lo};
|
`else
|
`else
|
assign of0_addr = {of0_addr_lo[`APIX_LO_MS:0]};
|
assign of0_addr = {of0_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF1_ADDR_HI Register
|
// OF1_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] of1_addr_hi;
|
reg [`APIX_HI_MSB:0] of1_addr_hi;
|
|
|
wire of1_addr_hi_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B1_READ);
|
wire of1_addr_hi_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of1_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) of1_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (of1_addr_hi_wr) of1_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (of1_addr_hi_wr) of1_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF1_ADDR_LO Register
|
// OF1_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] of1_addr_lo;
|
reg [`APIX_LO_MSB:0] of1_addr_lo;
|
|
|
wire of1_addr_lo_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B2_READ);
|
wire of1_addr_lo_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of1_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) of1_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (of1_addr_lo_wr) of1_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (of1_addr_lo_wr) of1_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign of1_addr = {of1_addr_hi[`APIX_HI_MSB:0], of1_addr_lo};
|
assign of1_addr = {of1_addr_hi[`APIX_HI_MSB:0], of1_addr_lo};
|
`else
|
`else
|
assign of1_addr = {of1_addr_lo[`APIX_LO_MS:0]};
|
assign of1_addr = {of1_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF2_ADDR_HI Register
|
// OF2_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] of2_addr_hi;
|
reg [`APIX_HI_MSB:0] of2_addr_hi;
|
|
|
wire of2_addr_hi_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B1_READ);
|
wire of2_addr_hi_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of2_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) of2_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (of2_addr_hi_wr) of2_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (of2_addr_hi_wr) of2_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF2_ADDR_LO Register
|
// OF2_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] of2_addr_lo;
|
reg [`APIX_LO_MSB:0] of2_addr_lo;
|
|
|
wire of2_addr_lo_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B2_READ);
|
wire of2_addr_lo_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of2_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) of2_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (of2_addr_lo_wr) of2_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (of2_addr_lo_wr) of2_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign of2_addr = {of2_addr_hi[`APIX_HI_MSB:0], of2_addr_lo};
|
assign of2_addr = {of2_addr_hi[`APIX_HI_MSB:0], of2_addr_lo};
|
`else
|
`else
|
assign of2_addr = {of2_addr_lo[`APIX_LO_MS:0]};
|
assign of2_addr = {of2_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF3_ADDR_HI Register
|
// OF3_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] of3_addr_hi;
|
reg [`APIX_HI_MSB:0] of3_addr_hi;
|
|
|
wire of3_addr_hi_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B1_READ);
|
wire of3_addr_hi_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of3_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) of3_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (of3_addr_hi_wr) of3_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (of3_addr_hi_wr) of3_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF3_ADDR_LO Register
|
// OF3_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] of3_addr_lo;
|
reg [`APIX_LO_MSB:0] of3_addr_lo;
|
|
|
wire of3_addr_lo_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B2_READ);
|
wire of3_addr_lo_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of3_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) of3_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (of3_addr_lo_wr) of3_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (of3_addr_lo_wr) of3_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign of3_addr = {of3_addr_hi[`APIX_HI_MSB:0], of3_addr_lo};
|
assign of3_addr = {of3_addr_hi[`APIX_HI_MSB:0], of3_addr_lo};
|
`else
|
`else
|
assign of3_addr = {of3_addr_lo[`APIX_LO_MS:0]};
|
assign of3_addr = {of3_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
// Offset address selection
|
// Offset address selection
|
assign src_offset_addr = (src_offset_sel==2'h0) ? of0_addr :
|
assign src_offset_addr = (src_offset_sel==2'h0) ? of0_addr :
|
(src_offset_sel==2'h1) ? of1_addr :
|
(src_offset_sel==2'h1) ? of1_addr :
|
(src_offset_sel==2'h2) ? of2_addr : of3_addr;
|
(src_offset_sel==2'h2) ? of2_addr : of3_addr;
|
|
|
assign dst_offset_addr = (dst_offset_sel==2'h0) ? of0_addr :
|
assign dst_offset_addr = (dst_offset_sel==2'h0) ? of0_addr :
|
(dst_offset_sel==2'h1) ? of1_addr :
|
(dst_offset_sel==2'h1) ? of1_addr :
|
(dst_offset_sel==2'h2) ? of2_addr : of3_addr;
|
(dst_offset_sel==2'h2) ? of2_addr : of3_addr;
|
|
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// TRANSPARENT_COLOR Register
|
// TRANSPARENT_COLOR Register
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
wire transparent_color_wr = (reg_access==REG_SET_TRANSPARENT) & (gpu_state==DATA1B_READ);
|
wire transparent_color_wr = (reg_access==REG_SET_TRANSPARENT) & (gpu_state==DATA1B_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) transparent_color <= 16'h0000;
|
if (puc_rst) transparent_color <= 16'h0000;
|
else if (transparent_color_wr) transparent_color <= gpu_data_i;
|
else if (transparent_color_wr) transparent_color <= gpu_data_i;
|
|
|
assign cfg_transparent_color_o = transparent_color;
|
assign cfg_transparent_color_o = transparent_color;
|
|
|
endmodule // ogfx_gpu_reg
|
endmodule // ogfx_gpu_reg
|
|
|
`ifdef OGFX_NO_INCLUDE
|
`ifdef OGFX_NO_INCLUDE
|
`else
|
`else
|
`include "openGFX430_undefines.v"
|
`include "openGFX430_undefines.v"
|
`endif
|
`endif
|
|
|