//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2001 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: tb_openMSP430.v
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// *File Name: tb_openMSP430.v
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//
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//
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// *Module Description:
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// *Module Description:
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// openMSP430 testbench
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// openMSP430 testbench
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 134 $
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// $Rev: 151 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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// $LastChangedDate: 2012-07-23 00:24:11 +0200 (Mon, 23 Jul 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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module tb_openMSP430;
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module tb_openMSP430;
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|
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//
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//
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// Wire & Register definition
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// Wire & Register definition
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//------------------------------
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//------------------------------
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|
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// Data Memory interface
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// Data Memory interface
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wire [`DMEM_MSB:0] dmem_addr;
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wire [`DMEM_MSB:0] dmem_addr;
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wire dmem_cen;
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wire dmem_cen;
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wire [15:0] dmem_din;
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wire [15:0] dmem_din;
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wire [1:0] dmem_wen;
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wire [1:0] dmem_wen;
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wire [15:0] dmem_dout;
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wire [15:0] dmem_dout;
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|
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// Program Memory interface
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// Program Memory interface
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wire [`PMEM_MSB:0] pmem_addr;
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wire [`PMEM_MSB:0] pmem_addr;
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wire pmem_cen;
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wire pmem_cen;
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wire [15:0] pmem_din;
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wire [15:0] pmem_din;
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wire [1:0] pmem_wen;
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wire [1:0] pmem_wen;
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wire [15:0] pmem_dout;
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wire [15:0] pmem_dout;
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|
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// Peripherals interface
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// Peripherals interface
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wire [13:0] per_addr;
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wire [13:0] per_addr;
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wire [15:0] per_din;
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wire [15:0] per_din;
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wire [15:0] per_dout;
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wire [15:0] per_dout;
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wire [1:0] per_we;
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wire [1:0] per_we;
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wire per_en;
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wire per_en;
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// Digital I/O
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// Digital I/O
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wire irq_port1;
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wire irq_port1;
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wire irq_port2;
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wire irq_port2;
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wire [15:0] per_dout_dio;
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wire [15:0] per_dout_dio;
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wire [7:0] p1_dout;
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wire [7:0] p1_dout;
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wire [7:0] p1_dout_en;
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wire [7:0] p1_dout_en;
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wire [7:0] p1_sel;
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wire [7:0] p1_sel;
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wire [7:0] p2_dout;
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wire [7:0] p2_dout;
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wire [7:0] p2_dout_en;
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wire [7:0] p2_dout_en;
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wire [7:0] p2_sel;
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wire [7:0] p2_sel;
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wire [7:0] p3_dout;
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wire [7:0] p3_dout;
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wire [7:0] p3_dout_en;
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wire [7:0] p3_dout_en;
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wire [7:0] p3_sel;
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wire [7:0] p3_sel;
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wire [7:0] p4_dout;
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wire [7:0] p4_dout;
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wire [7:0] p4_dout_en;
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wire [7:0] p4_dout_en;
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wire [7:0] p4_sel;
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wire [7:0] p4_sel;
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wire [7:0] p5_dout;
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wire [7:0] p5_dout;
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wire [7:0] p5_dout_en;
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wire [7:0] p5_dout_en;
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wire [7:0] p5_sel;
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wire [7:0] p5_sel;
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wire [7:0] p6_dout;
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wire [7:0] p6_dout;
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wire [7:0] p6_dout_en;
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wire [7:0] p6_dout_en;
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wire [7:0] p6_sel;
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wire [7:0] p6_sel;
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reg [7:0] p1_din;
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reg [7:0] p1_din;
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reg [7:0] p2_din;
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reg [7:0] p2_din;
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reg [7:0] p3_din;
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reg [7:0] p3_din;
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reg [7:0] p4_din;
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reg [7:0] p4_din;
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reg [7:0] p5_din;
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reg [7:0] p5_din;
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reg [7:0] p6_din;
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reg [7:0] p6_din;
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// Peripheral templates
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// Peripheral templates
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wire [15:0] per_dout_temp_8b;
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wire [15:0] per_dout_temp_8b;
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wire [15:0] per_dout_temp_16b;
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wire [15:0] per_dout_temp_16b;
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// Simple full duplex UART
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// Simple full duplex UART
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wire [15:0] per_dout_uart;
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wire [15:0] per_dout_uart;
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wire irq_uart_rx;
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wire irq_uart_rx;
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wire irq_uart_tx;
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wire irq_uart_tx;
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wire uart_txd;
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wire uart_txd;
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reg uart_rxd;
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reg uart_rxd;
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// Timer A
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// Timer A
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wire irq_ta0;
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wire irq_ta0;
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wire irq_ta1;
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wire irq_ta1;
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wire [15:0] per_dout_timerA;
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wire [15:0] per_dout_timerA;
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reg inclk;
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reg inclk;
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reg taclk;
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reg taclk;
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reg ta_cci0a;
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reg ta_cci0a;
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reg ta_cci0b;
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reg ta_cci0b;
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reg ta_cci1a;
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reg ta_cci1a;
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reg ta_cci1b;
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reg ta_cci1b;
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reg ta_cci2a;
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reg ta_cci2a;
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reg ta_cci2b;
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reg ta_cci2b;
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wire ta_out0;
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wire ta_out0;
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wire ta_out0_en;
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wire ta_out0_en;
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wire ta_out1;
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wire ta_out1;
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wire ta_out1_en;
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wire ta_out1_en;
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wire ta_out2;
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wire ta_out2;
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wire ta_out2_en;
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wire ta_out2_en;
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// Clock / Reset & Interrupts
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// Clock / Reset & Interrupts
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reg dco_clk;
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reg dco_clk;
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wire dco_enable;
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wire dco_enable;
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wire dco_wkup;
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wire dco_wkup;
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reg dco_local_enable;
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reg dco_local_enable;
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reg lfxt_clk;
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reg lfxt_clk;
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wire lfxt_enable;
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wire lfxt_enable;
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wire lfxt_wkup;
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wire lfxt_wkup;
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reg lfxt_local_enable;
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reg lfxt_local_enable;
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wire mclk;
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wire mclk;
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wire aclk;
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wire aclk;
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wire aclk_en;
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wire aclk_en;
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wire smclk;
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wire smclk;
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wire smclk_en;
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wire smclk_en;
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reg reset_n;
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reg reset_n;
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wire puc_rst;
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wire puc_rst;
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reg nmi;
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reg nmi;
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reg [13:0] irq;
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reg [13:0] irq;
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wire [13:0] irq_acc;
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wire [13:0] irq_acc;
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wire [13:0] irq_in;
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wire [13:0] irq_in;
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reg cpu_en;
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reg cpu_en;
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reg [13:0] wkup;
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reg [13:0] wkup;
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wire [13:0] wkup_in;
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wire [13:0] wkup_in;
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// Scan (ASIC version only)
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// Scan (ASIC version only)
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reg scan_enable;
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reg scan_enable;
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reg scan_mode;
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reg scan_mode;
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// Debug interface
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// Debug interface
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reg dbg_en;
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reg dbg_en;
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wire dbg_freeze;
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wire dbg_freeze;
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wire dbg_uart_txd;
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wire dbg_uart_txd;
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wire dbg_uart_rxd;
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wire dbg_uart_rxd;
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reg dbg_uart_rxd_sel;
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reg dbg_uart_rxd_sel;
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reg dbg_uart_rxd_dly;
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reg dbg_uart_rxd_dly;
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reg dbg_uart_rxd_pre;
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reg dbg_uart_rxd_pre;
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reg dbg_uart_rxd_meta;
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reg dbg_uart_rxd_meta;
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reg [15:0] dbg_uart_buf;
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reg [15:0] dbg_uart_buf;
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reg dbg_uart_rx_busy;
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reg dbg_uart_rx_busy;
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reg dbg_uart_tx_busy;
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reg dbg_uart_tx_busy;
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// Core testbench debuging signals
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// Core testbench debuging signals
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wire [8*32-1:0] i_state;
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wire [8*32-1:0] i_state;
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wire [8*32-1:0] e_state;
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wire [8*32-1:0] e_state;
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wire [31:0] inst_cycle;
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wire [31:0] inst_cycle;
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wire [8*32-1:0] inst_full;
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wire [8*32-1:0] inst_full;
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wire [31:0] inst_number;
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wire [31:0] inst_number;
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wire [15:0] inst_pc;
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wire [15:0] inst_pc;
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wire [8*32-1:0] inst_short;
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wire [8*32-1:0] inst_short;
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// Testbench variables
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// Testbench variables
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integer error;
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integer error;
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reg stimulus_done;
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reg stimulus_done;
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//
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//
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// Include files
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// Include files
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//------------------------------
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//------------------------------
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// CPU & Memory registers
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// CPU & Memory registers
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`include "registers.v"
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`include "registers.v"
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// Debug interface tasks
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// Debug interface tasks
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`include "dbg_uart_tasks.v"
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`include "dbg_uart_tasks.v"
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// Simple uart tasks
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// Simple uart tasks
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//`include "uart_tasks.v"
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//`include "uart_tasks.v"
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// Verilog stimulus
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// Verilog stimulus
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`include "stimulus.v"
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`include "stimulus.v"
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//
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//
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// Initialize ROM
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// Initialize ROM
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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#10 $readmemh("./pmem.mem", pmem_0.mem);
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#10 $readmemh("./pmem.mem", pmem_0.mem);
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end
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end
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//
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//
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// Generate Clock & Reset
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// Generate Clock & Reset
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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dco_clk = 1'b0;
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dco_clk = 1'b0;
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dco_local_enable = 1'b0;
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dco_local_enable = 1'b0;
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forever
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forever
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begin
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begin
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#25; // 20 MHz
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#25; // 20 MHz
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dco_local_enable = (dco_enable===1) ? dco_enable : (dco_wkup===1);
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dco_local_enable = (dco_enable===1) ? dco_enable : (dco_wkup===1);
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if (dco_local_enable)
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if (dco_local_enable)
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dco_clk = ~dco_clk;
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dco_clk = ~dco_clk;
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end
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end
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end
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end
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|
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initial
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initial
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begin
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begin
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lfxt_clk = 1'b0;
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lfxt_clk = 1'b0;
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lfxt_local_enable = 1'b0;
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lfxt_local_enable = 1'b0;
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forever
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forever
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begin
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begin
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#763; // 655 kHz
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#763; // 655 kHz
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lfxt_local_enable = (lfxt_enable===1) ? lfxt_enable : (lfxt_wkup===1);
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lfxt_local_enable = (lfxt_enable===1) ? lfxt_enable : (lfxt_wkup===1);
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if (lfxt_local_enable)
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if (lfxt_local_enable)
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lfxt_clk = ~lfxt_clk;
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lfxt_clk = ~lfxt_clk;
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end
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end
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end
|
end
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|
|
initial
|
initial
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begin
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begin
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reset_n = 1'b1;
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reset_n = 1'b1;
|
#93;
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#93;
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reset_n = 1'b0;
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reset_n = 1'b0;
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#593;
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#593;
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reset_n = 1'b1;
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reset_n = 1'b1;
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end
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end
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|
|
initial
|
initial
|
begin
|
begin
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error = 0;
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error = 0;
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stimulus_done = 1;
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stimulus_done = 1;
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irq = 14'h0000;
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irq = 14'h0000;
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nmi = 1'b0;
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nmi = 1'b0;
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wkup = 14'h0000;
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wkup = 14'h0000;
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cpu_en = 1'b1;
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cpu_en = 1'b1;
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dbg_en = 1'b0;
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dbg_en = 1'b0;
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dbg_uart_rxd_sel = 1'b0;
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dbg_uart_rxd_sel = 1'b0;
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dbg_uart_rxd_dly = 1'b1;
|
dbg_uart_rxd_dly = 1'b1;
|
dbg_uart_rxd_pre = 1'b1;
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dbg_uart_rxd_pre = 1'b1;
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dbg_uart_rxd_meta= 1'b0;
|
dbg_uart_rxd_meta= 1'b0;
|
dbg_uart_buf = 16'h0000;
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dbg_uart_buf = 16'h0000;
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dbg_uart_rx_busy = 1'b0;
|
dbg_uart_rx_busy = 1'b0;
|
dbg_uart_tx_busy = 1'b0;
|
dbg_uart_tx_busy = 1'b0;
|
p1_din = 8'h00;
|
p1_din = 8'h00;
|
p2_din = 8'h00;
|
p2_din = 8'h00;
|
p3_din = 8'h00;
|
p3_din = 8'h00;
|
p4_din = 8'h00;
|
p4_din = 8'h00;
|
p5_din = 8'h00;
|
p5_din = 8'h00;
|
p6_din = 8'h00;
|
p6_din = 8'h00;
|
inclk = 1'b0;
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inclk = 1'b0;
|
taclk = 1'b0;
|
taclk = 1'b0;
|
ta_cci0a = 1'b0;
|
ta_cci0a = 1'b0;
|
ta_cci0b = 1'b0;
|
ta_cci0b = 1'b0;
|
ta_cci1a = 1'b0;
|
ta_cci1a = 1'b0;
|
ta_cci1b = 1'b0;
|
ta_cci1b = 1'b0;
|
ta_cci2a = 1'b0;
|
ta_cci2a = 1'b0;
|
ta_cci2b = 1'b0;
|
ta_cci2b = 1'b0;
|
uart_rxd = 1'b1;
|
uart_rxd = 1'b1;
|
scan_enable = 1'b0;
|
scan_enable = 1'b0;
|
scan_mode = 1'b0;
|
scan_mode = 1'b0;
|
end
|
end
|
|
|
|
|
//
|
//
|
// Program Memory
|
// Program Memory
|
//----------------------------------
|
//----------------------------------
|
|
|
ram #(`PMEM_MSB, `PMEM_SIZE) pmem_0 (
|
ram #(`PMEM_MSB, `PMEM_SIZE) pmem_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.ram_dout (pmem_dout), // Program Memory data output
|
.ram_dout (pmem_dout), // Program Memory data output
|
|
|
// INPUTs
|
// INPUTs
|
.ram_addr (pmem_addr), // Program Memory address
|
.ram_addr (pmem_addr), // Program Memory address
|
.ram_cen (pmem_cen), // Program Memory chip enable (low active)
|
.ram_cen (pmem_cen), // Program Memory chip enable (low active)
|
.ram_clk (mclk), // Program Memory clock
|
.ram_clk (mclk), // Program Memory clock
|
.ram_din (pmem_din), // Program Memory data input
|
.ram_din (pmem_din), // Program Memory data input
|
.ram_wen (pmem_wen) // Program Memory write enable (low active)
|
.ram_wen (pmem_wen) // Program Memory write enable (low active)
|
);
|
);
|
|
|
|
|
//
|
//
|
// Data Memory
|
// Data Memory
|
//----------------------------------
|
//----------------------------------
|
|
|
ram #(`DMEM_MSB, `DMEM_SIZE) dmem_0 (
|
ram #(`DMEM_MSB, `DMEM_SIZE) dmem_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.ram_dout (dmem_dout), // Data Memory data output
|
.ram_dout (dmem_dout), // Data Memory data output
|
|
|
// INPUTs
|
// INPUTs
|
.ram_addr (dmem_addr), // Data Memory address
|
.ram_addr (dmem_addr), // Data Memory address
|
.ram_cen (dmem_cen), // Data Memory chip enable (low active)
|
.ram_cen (dmem_cen), // Data Memory chip enable (low active)
|
.ram_clk (mclk), // Data Memory clock
|
.ram_clk (mclk), // Data Memory clock
|
.ram_din (dmem_din), // Data Memory data input
|
.ram_din (dmem_din), // Data Memory data input
|
.ram_wen (dmem_wen) // Data Memory write enable (low active)
|
.ram_wen (dmem_wen) // Data Memory write enable (low active)
|
);
|
);
|
|
|
|
|
//
|
//
|
// openMSP430 Instance
|
// openMSP430 Instance
|
//----------------------------------
|
//----------------------------------
|
|
|
openMSP430 dut (
|
openMSP430 dut (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.aclk (aclk), // ASIC ONLY: ACLK
|
.aclk (aclk), // ASIC ONLY: ACLK
|
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
|
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
|
.dbg_freeze (dbg_freeze), // Freeze peripherals
|
.dbg_freeze (dbg_freeze), // Freeze peripherals
|
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
|
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
|
.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
|
.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
|
.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
.dmem_addr (dmem_addr), // Data Memory address
|
.dmem_addr (dmem_addr), // Data Memory address
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
.dmem_din (dmem_din), // Data Memory data input
|
.dmem_din (dmem_din), // Data Memory data input
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
|
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
|
.lfxt_enable (lfxt_enable), // ASIC ONLY: Low frequency oscillator enable
|
.lfxt_enable (lfxt_enable), // ASIC ONLY: Low frequency oscillator enable
|
.lfxt_wkup (lfxt_wkup), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
.lfxt_wkup (lfxt_wkup), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.pmem_addr (pmem_addr), // Program Memory address
|
.pmem_addr (pmem_addr), // Program Memory address
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.smclk (smclk), // ASIC ONLY: SMCLK
|
.smclk (smclk), // ASIC ONLY: SMCLK
|
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
|
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
|
|
|
// INPUTs
|
// INPUTs
|
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
|
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
|
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
|
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
|
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
|
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
|
.dco_clk (dco_clk), // Fast oscillator (fast clock)
|
.dco_clk (dco_clk), // Fast oscillator (fast clock)
|
.dmem_dout (dmem_dout), // Data Memory data output
|
.dmem_dout (dmem_dout), // Data Memory data output
|
.irq (irq_in), // Maskable interrupts
|
.irq (irq_in), // Maskable interrupts
|
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
|
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
.per_dout (per_dout), // Peripheral data output
|
.per_dout (per_dout), // Peripheral data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
|
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
|
.scan_enable (scan_enable), // ASIC ONLY: Scan enable (active during scan shifting)
|
.scan_enable (scan_enable), // ASIC ONLY: Scan enable (active during scan shifting)
|
.scan_mode (scan_mode), // ASIC ONLY: Scan mode
|
.scan_mode (scan_mode), // ASIC ONLY: Scan mode
|
.wkup (|wkup_in) // ASIC ONLY: System Wake-up (asynchronous)
|
.wkup (|wkup_in) // ASIC ONLY: System Wake-up (asynchronous)
|
);
|
);
|
|
|
//
|
//
|
// Digital I/O
|
// Digital I/O
|
//----------------------------------
|
//----------------------------------
|
|
|
`ifdef CVER
|
`ifdef CVER
|
omsp_gpio #(1,
|
omsp_gpio #(1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1,
|
1) gpio_0 (
|
1) gpio_0 (
|
`else
|
`else
|
omsp_gpio #(.P1_EN(1),
|
omsp_gpio #(.P1_EN(1),
|
.P2_EN(1),
|
.P2_EN(1),
|
.P3_EN(1),
|
.P3_EN(1),
|
.P4_EN(1),
|
.P4_EN(1),
|
.P5_EN(1),
|
.P5_EN(1),
|
.P6_EN(1)) gpio_0 (
|
.P6_EN(1)) gpio_0 (
|
`endif
|
`endif
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.irq_port1 (irq_port1), // Port 1 interrupt
|
.irq_port1 (irq_port1), // Port 1 interrupt
|
.irq_port2 (irq_port2), // Port 2 interrupt
|
.irq_port2 (irq_port2), // Port 2 interrupt
|
.p1_dout (p1_dout), // Port 1 data output
|
.p1_dout (p1_dout), // Port 1 data output
|
.p1_dout_en (p1_dout_en), // Port 1 data output enable
|
.p1_dout_en (p1_dout_en), // Port 1 data output enable
|
.p1_sel (p1_sel), // Port 1 function select
|
.p1_sel (p1_sel), // Port 1 function select
|
.p2_dout (p2_dout), // Port 2 data output
|
.p2_dout (p2_dout), // Port 2 data output
|
.p2_dout_en (p2_dout_en), // Port 2 data output enable
|
.p2_dout_en (p2_dout_en), // Port 2 data output enable
|
.p2_sel (p2_sel), // Port 2 function select
|
.p2_sel (p2_sel), // Port 2 function select
|
.p3_dout (p3_dout), // Port 3 data output
|
.p3_dout (p3_dout), // Port 3 data output
|
.p3_dout_en (p3_dout_en), // Port 3 data output enable
|
.p3_dout_en (p3_dout_en), // Port 3 data output enable
|
.p3_sel (p3_sel), // Port 3 function select
|
.p3_sel (p3_sel), // Port 3 function select
|
.p4_dout (p4_dout), // Port 4 data output
|
.p4_dout (p4_dout), // Port 4 data output
|
.p4_dout_en (p4_dout_en), // Port 4 data output enable
|
.p4_dout_en (p4_dout_en), // Port 4 data output enable
|
.p4_sel (p4_sel), // Port 4 function select
|
.p4_sel (p4_sel), // Port 4 function select
|
.p5_dout (p5_dout), // Port 5 data output
|
.p5_dout (p5_dout), // Port 5 data output
|
.p5_dout_en (p5_dout_en), // Port 5 data output enable
|
.p5_dout_en (p5_dout_en), // Port 5 data output enable
|
.p5_sel (p5_sel), // Port 5 function select
|
.p5_sel (p5_sel), // Port 5 function select
|
.p6_dout (p6_dout), // Port 6 data output
|
.p6_dout (p6_dout), // Port 6 data output
|
.p6_dout_en (p6_dout_en), // Port 6 data output enable
|
.p6_dout_en (p6_dout_en), // Port 6 data output enable
|
.p6_sel (p6_sel), // Port 6 function select
|
.p6_sel (p6_sel), // Port 6 function select
|
.per_dout (per_dout_dio), // Peripheral data output
|
.per_dout (per_dout_dio), // Peripheral data output
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.p1_din (p1_din), // Port 1 data input
|
.p1_din (p1_din), // Port 1 data input
|
.p2_din (p2_din), // Port 2 data input
|
.p2_din (p2_din), // Port 2 data input
|
.p3_din (p3_din), // Port 3 data input
|
.p3_din (p3_din), // Port 3 data input
|
.p4_din (p4_din), // Port 4 data input
|
.p4_din (p4_din), // Port 4 data input
|
.p5_din (p5_din), // Port 5 data input
|
.p5_din (p5_din), // Port 5 data input
|
.p6_din (p6_din), // Port 6 data input
|
.p6_din (p6_din), // Port 6 data input
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc_rst (puc_rst) // Main system reset
|
.puc_rst (puc_rst) // Main system reset
|
);
|
);
|
|
|
//
|
//
|
// Timers
|
// Timers
|
//----------------------------------
|
//----------------------------------
|
|
|
omsp_timerA timerA_0 (
|
omsp_timerA timerA_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
|
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
|
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
|
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
|
.per_dout (per_dout_timerA), // Peripheral data output
|
.per_dout (per_dout_timerA), // Peripheral data output
|
.ta_out0 (ta_out0), // Timer A output 0
|
.ta_out0 (ta_out0), // Timer A output 0
|
.ta_out0_en (ta_out0_en), // Timer A output 0 enable
|
.ta_out0_en (ta_out0_en), // Timer A output 0 enable
|
.ta_out1 (ta_out1), // Timer A output 1
|
.ta_out1 (ta_out1), // Timer A output 1
|
.ta_out1_en (ta_out1_en), // Timer A output 1 enable
|
.ta_out1_en (ta_out1_en), // Timer A output 1 enable
|
.ta_out2 (ta_out2), // Timer A output 2
|
.ta_out2 (ta_out2), // Timer A output 2
|
.ta_out2_en (ta_out2_en), // Timer A output 2 enable
|
.ta_out2_en (ta_out2_en), // Timer A output 2 enable
|
|
|
// INPUTs
|
// INPUTs
|
.aclk_en (aclk_en), // ACLK enable (from CPU)
|
.aclk_en (aclk_en), // ACLK enable (from CPU)
|
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
|
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
|
.inclk (inclk), // INCLK external timer clock (SLOW)
|
.inclk (inclk), // INCLK external timer clock (SLOW)
|
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
|
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
.ta_cci0a (ta_cci0a), // Timer A compare 0 input A
|
.ta_cci0a (ta_cci0a), // Timer A compare 0 input A
|
.ta_cci0b (ta_cci0b), // Timer A compare 0 input B
|
.ta_cci0b (ta_cci0b), // Timer A compare 0 input B
|
.ta_cci1a (ta_cci1a), // Timer A compare 1 input A
|
.ta_cci1a (ta_cci1a), // Timer A compare 1 input A
|
.ta_cci1b (ta_cci1b), // Timer A compare 1 input B
|
.ta_cci1b (ta_cci1b), // Timer A compare 1 input B
|
.ta_cci2a (ta_cci2a), // Timer A compare 2 input A
|
.ta_cci2a (ta_cci2a), // Timer A compare 2 input A
|
.ta_cci2b (ta_cci2b), // Timer A compare 2 input B
|
.ta_cci2b (ta_cci2b), // Timer A compare 2 input B
|
.taclk (taclk) // TACLK external timer clock (SLOW)
|
.taclk (taclk) // TACLK external timer clock (SLOW)
|
);
|
);
|
|
|
//
|
//
|
// Simple full duplex UART (8N1 protocol)
|
// Simple full duplex UART (8N1 protocol)
|
//----------------------------------------
|
//----------------------------------------
|
`ifdef READY_FOR_PRIMETIME
|
`ifdef READY_FOR_PRIMETIME
|
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (
|
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.irq_uart_rx (irq_uart_rx), // UART receive interrupt
|
.irq_uart_rx (irq_uart_rx), // UART receive interrupt
|
.irq_uart_tx (irq_uart_tx), // UART transmit interrupt
|
.irq_uart_tx (irq_uart_tx), // UART transmit interrupt
|
.per_dout (per_dout_uart), // Peripheral data output
|
.per_dout (per_dout_uart), // Peripheral data output
|
.uart_txd (uart_txd), // UART Data Transmit (TXD)
|
.uart_txd (uart_txd), // UART Data Transmit (TXD)
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
.uart_rxd (uart_rxd) // UART Data Receive (RXD)
|
.uart_rxd (uart_rxd) // UART Data Receive (RXD)
|
);
|
);
|
`else
|
`else
|
assign irq_uart_rx = 1'b0;
|
assign irq_uart_rx = 1'b0;
|
assign irq_uart_tx = 1'b0;
|
assign irq_uart_tx = 1'b0;
|
assign per_dout_uart = 16'h0000;
|
assign per_dout_uart = 16'h0000;
|
assign uart_txd = 1'b0;
|
assign uart_txd = 1'b0;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Peripheral templates
|
// Peripheral templates
|
//----------------------------------
|
//----------------------------------
|
|
|
template_periph_8b template_periph_8b_0 (
|
template_periph_8b template_periph_8b_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.per_dout (per_dout_temp_8b), // Peripheral data output
|
.per_dout (per_dout_temp_8b), // Peripheral data output
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc_rst (puc_rst) // Main system reset
|
.puc_rst (puc_rst) // Main system reset
|
);
|
);
|
|
|
`ifdef CVER
|
`ifdef CVER
|
template_periph_16b #(15'h0190) template_periph_16b_0 (
|
template_periph_16b #(15'h0190) template_periph_16b_0 (
|
`else
|
`else
|
template_periph_16b #(.BASE_ADDR(15'd`PER_SIZE-15'h0070)) template_periph_16b_0 (
|
template_periph_16b #(.BASE_ADDR((15'd`PER_SIZE-15'h0070) & 15'h7ff8)) template_periph_16b_0 (
|
`endif
|
`endif
|
// OUTPUTs
|
// OUTPUTs
|
.per_dout (per_dout_temp_16b), // Peripheral data output
|
.per_dout (per_dout_temp_16b), // Peripheral data output
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc_rst (puc_rst) // Main system reset
|
.puc_rst (puc_rst) // Main system reset
|
);
|
);
|
|
|
|
|
//
|
//
|
// Combine peripheral data bus
|
// Combine peripheral data bus
|
//----------------------------------
|
//----------------------------------
|
|
|
assign per_dout = per_dout_dio |
|
assign per_dout = per_dout_dio |
|
per_dout_timerA |
|
per_dout_timerA |
|
per_dout_uart |
|
per_dout_uart |
|
per_dout_temp_8b |
|
per_dout_temp_8b |
|
per_dout_temp_16b;
|
per_dout_temp_16b;
|
|
|
|
|
//
|
//
|
// Map peripheral interrupts & wakeups
|
// Map peripheral interrupts & wakeups
|
//----------------------------------------
|
//----------------------------------------
|
|
|
assign irq_in = irq | {1'b0, // Vector 13 (0xFFFA)
|
assign irq_in = irq | {1'b0, // Vector 13 (0xFFFA)
|
1'b0, // Vector 12 (0xFFF8)
|
1'b0, // Vector 12 (0xFFF8)
|
1'b0, // Vector 11 (0xFFF6)
|
1'b0, // Vector 11 (0xFFF6)
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
irq_ta0, // Vector 9 (0xFFF2)
|
irq_ta0, // Vector 9 (0xFFF2)
|
irq_ta1, // Vector 8 (0xFFF0)
|
irq_ta1, // Vector 8 (0xFFF0)
|
irq_uart_rx, // Vector 7 (0xFFEE)
|
irq_uart_rx, // Vector 7 (0xFFEE)
|
irq_uart_tx, // Vector 6 (0xFFEC)
|
irq_uart_tx, // Vector 6 (0xFFEC)
|
1'b0, // Vector 5 (0xFFEA)
|
1'b0, // Vector 5 (0xFFEA)
|
1'b0, // Vector 4 (0xFFE8)
|
1'b0, // Vector 4 (0xFFE8)
|
irq_port2, // Vector 3 (0xFFE6)
|
irq_port2, // Vector 3 (0xFFE6)
|
irq_port1, // Vector 2 (0xFFE4)
|
irq_port1, // Vector 2 (0xFFE4)
|
1'b0, // Vector 1 (0xFFE2)
|
1'b0, // Vector 1 (0xFFE2)
|
1'b0}; // Vector 0 (0xFFE0)
|
1'b0}; // Vector 0 (0xFFE0)
|
|
|
assign wkup_in = wkup | {1'b0, // Vector 13 (0xFFFA)
|
assign wkup_in = wkup | {1'b0, // Vector 13 (0xFFFA)
|
1'b0, // Vector 12 (0xFFF8)
|
1'b0, // Vector 12 (0xFFF8)
|
1'b0, // Vector 11 (0xFFF6)
|
1'b0, // Vector 11 (0xFFF6)
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
1'b0, // Vector 9 (0xFFF2)
|
1'b0, // Vector 9 (0xFFF2)
|
1'b0, // Vector 8 (0xFFF0)
|
1'b0, // Vector 8 (0xFFF0)
|
1'b0, // Vector 7 (0xFFEE)
|
1'b0, // Vector 7 (0xFFEE)
|
1'b0, // Vector 6 (0xFFEC)
|
1'b0, // Vector 6 (0xFFEC)
|
1'b0, // Vector 5 (0xFFEA)
|
1'b0, // Vector 5 (0xFFEA)
|
1'b0, // Vector 4 (0xFFE8)
|
1'b0, // Vector 4 (0xFFE8)
|
1'b0, // Vector 3 (0xFFE6)
|
1'b0, // Vector 3 (0xFFE6)
|
1'b0, // Vector 2 (0xFFE4)
|
1'b0, // Vector 2 (0xFFE4)
|
1'b0, // Vector 1 (0xFFE2)
|
1'b0, // Vector 1 (0xFFE2)
|
1'b0}; // Vector 0 (0xFFE0)
|
1'b0}; // Vector 0 (0xFFE0)
|
|
|
|
|
//
|
//
|
// Debug utility signals
|
// Debug utility signals
|
//----------------------------------------
|
//----------------------------------------
|
msp_debug msp_debug_0 (
|
msp_debug msp_debug_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.e_state (e_state), // Execution state
|
.e_state (e_state), // Execution state
|
.i_state (i_state), // Instruction fetch state
|
.i_state (i_state), // Instruction fetch state
|
.inst_cycle (inst_cycle), // Cycle number within current instruction
|
.inst_cycle (inst_cycle), // Cycle number within current instruction
|
.inst_full (inst_full), // Currently executed instruction (full version)
|
.inst_full (inst_full), // Currently executed instruction (full version)
|
.inst_number (inst_number), // Instruction number since last system reset
|
.inst_number (inst_number), // Instruction number since last system reset
|
.inst_pc (inst_pc), // Instruction Program counter
|
.inst_pc (inst_pc), // Instruction Program counter
|
.inst_short (inst_short), // Currently executed instruction (short version)
|
.inst_short (inst_short), // Currently executed instruction (short version)
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.puc_rst (puc_rst) // Main system reset
|
.puc_rst (puc_rst) // Main system reset
|
);
|
);
|
|
|
|
|
//
|
//
|
// Generate Waveform
|
// Generate Waveform
|
//----------------------------------------
|
//----------------------------------------
|
initial
|
initial
|
begin
|
begin
|
`ifdef NODUMP
|
`ifdef NODUMP
|
`else
|
`else
|
`ifdef VPD_FILE
|
`ifdef VPD_FILE
|
$vcdplusfile("tb_openMSP430.vpd");
|
$vcdplusfile("tb_openMSP430.vpd");
|
$vcdpluson();
|
$vcdpluson();
|
`else
|
`else
|
`ifdef TRN_FILE
|
`ifdef TRN_FILE
|
$recordfile ("tb_openMSP430.trn");
|
$recordfile ("tb_openMSP430.trn");
|
$recordvars;
|
$recordvars;
|
`else
|
`else
|
$dumpfile("tb_openMSP430.vcd");
|
$dumpfile("tb_openMSP430.vcd");
|
$dumpvars(0, tb_openMSP430);
|
$dumpvars(0, tb_openMSP430);
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
end
|
end
|
|
|
//
|
//
|
// End of simulation
|
// End of simulation
|
//----------------------------------------
|
//----------------------------------------
|
|
|
initial // Timeout
|
initial // Timeout
|
begin
|
begin
|
`ifdef NO_TIMEOUT
|
`ifdef NO_TIMEOUT
|
`else
|
`else
|
`ifdef VERY_LONG_TIMEOUT
|
`ifdef VERY_LONG_TIMEOUT
|
#500000000;
|
#500000000;
|
`else
|
`else
|
`ifdef LONG_TIMEOUT
|
`ifdef LONG_TIMEOUT
|
#5000000;
|
#5000000;
|
`else
|
`else
|
#500000;
|
#500000;
|
`endif
|
`endif
|
`endif
|
`endif
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$display("| SIMULATION FAILED |");
|
$display("| SIMULATION FAILED |");
|
$display("| (simulation Timeout) |");
|
$display("| (simulation Timeout) |");
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$finish;
|
$finish;
|
`endif
|
`endif
|
end
|
end
|
|
|
initial // Normal end of test
|
initial // Normal end of test
|
begin
|
begin
|
@(negedge stimulus_done);
|
@(negedge stimulus_done);
|
wait(inst_pc=='hffff);
|
wait(inst_pc=='hffff);
|
|
|
$display(" ===============================================");
|
$display(" ===============================================");
|
if (error!=0)
|
if (error!=0)
|
begin
|
begin
|
$display("| SIMULATION FAILED |");
|
$display("| SIMULATION FAILED |");
|
$display("| (some verilog stimulus checks failed) |");
|
$display("| (some verilog stimulus checks failed) |");
|
end
|
end
|
else if (~stimulus_done)
|
else if (~stimulus_done)
|
begin
|
begin
|
$display("| SIMULATION FAILED |");
|
$display("| SIMULATION FAILED |");
|
$display("| (the verilog stimulus didn't complete) |");
|
$display("| (the verilog stimulus didn't complete) |");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("| SIMULATION PASSED |");
|
$display("| SIMULATION PASSED |");
|
end
|
end
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$finish;
|
$finish;
|
end
|
end
|
|
|
|
|
//
|
//
|
// Tasks Definition
|
// Tasks Definition
|
//------------------------------
|
//------------------------------
|
|
|
task tb_error;
|
task tb_error;
|
input [65*8:0] error_string;
|
input [65*8:0] error_string;
|
begin
|
begin
|
$display("ERROR: %s %t", error_string, $time);
|
$display("ERROR: %s %t", error_string, $time);
|
error = error+1;
|
error = error+1;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
endmodule
|
endmodule
|
|
|
