/*===========================================================================*/
|
/*===========================================================================*/
|
/* Copyright (C) 2001 Authors */
|
/* Copyright (C) 2001 Authors */
|
/* */
|
/* */
|
/* This source file may be used and distributed without restriction provided */
|
/* This source file may be used and distributed without restriction provided */
|
/* that this copyright statement is not removed from the file and that any */
|
/* that this copyright statement is not removed from the file and that any */
|
/* derivative work contains the original copyright notice and the associated */
|
/* derivative work contains the original copyright notice and the associated */
|
/* disclaimer. */
|
/* disclaimer. */
|
/* */
|
/* */
|
/* This source file is free software; you can redistribute it and/or modify */
|
/* This source file is free software; you can redistribute it and/or modify */
|
/* it under the terms of the GNU Lesser General Public License as published */
|
/* it under the terms of the GNU Lesser General Public License as published */
|
/* by the Free Software Foundation; either version 2.1 of the License, or */
|
/* by the Free Software Foundation; either version 2.1 of the License, or */
|
/* (at your option) any later version. */
|
/* (at your option) any later version. */
|
/* */
|
/* */
|
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
|
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
|
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
|
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
|
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
|
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
|
/* License for more details. */
|
/* License for more details. */
|
/* */
|
/* */
|
/* You should have received a copy of the GNU Lesser General Public License */
|
/* You should have received a copy of the GNU Lesser General Public License */
|
/* along with this source; if not, write to the Free Software Foundation, */
|
/* along with this source; if not, write to the Free Software Foundation, */
|
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
|
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
|
/* */
|
/* */
|
/*===========================================================================*/
|
/*===========================================================================*/
|
/* CLOCK MODULE */
|
/* CLOCK MODULE */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/* Test the clock module: */
|
/* Test the clock module: */
|
/* - Check the ACLK and SMCLK clock generation. */
|
/* - Check the ACLK and SMCLK clock generation. */
|
/* */
|
/* */
|
/* Author(s): */
|
/* Author(s): */
|
/* - Olivier Girard, olgirard@gmail.com */
|
/* - Olivier Girard, olgirard@gmail.com */
|
/* */
|
/* */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/* $Rev: 19 $ */
|
/* $Rev: 19 $ */
|
/* $LastChangedBy: olivier.girard $ */
|
/* $LastChangedBy: olivier.girard $ */
|
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
|
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
|
/*===========================================================================*/
|
/*===========================================================================*/
|
|
|
`define LONG_TIMEOUT
|
`define LONG_TIMEOUT
|
|
|
|
|
integer dco_clk_counter;
|
integer dco_clk_counter;
|
always @ (negedge dco_clk)
|
always @ (negedge dco_clk)
|
dco_clk_counter <= dco_clk_counter+1;
|
dco_clk_counter <= dco_clk_counter+1;
|
|
|
integer lfxt_clk_counter;
|
integer lfxt_clk_counter;
|
always @ (negedge lfxt_clk)
|
always @ (negedge lfxt_clk)
|
lfxt_clk_counter <= lfxt_clk_counter+1;
|
lfxt_clk_counter <= lfxt_clk_counter+1;
|
|
|
integer mclk_counter;
|
integer mclk_counter;
|
always @ (posedge mclk)
|
always @ (posedge mclk)
|
mclk_counter <= mclk_counter+1;
|
mclk_counter <= mclk_counter+1;
|
|
|
integer aclk_counter;
|
integer aclk_counter;
|
always @ (negedge aclk)
|
always @ (negedge aclk)
|
aclk_counter <= aclk_counter+1;
|
aclk_counter <= aclk_counter+1;
|
|
|
integer smclk_counter;
|
integer smclk_counter;
|
always @ (negedge smclk)
|
always @ (negedge smclk)
|
smclk_counter <= smclk_counter+1;
|
smclk_counter <= smclk_counter+1;
|
|
|
integer dbg_clk_counter;
|
integer dbg_clk_counter;
|
always @ (negedge dbg_clk)
|
always @ (negedge dbg_clk)
|
dbg_clk_counter <= dbg_clk_counter+1;
|
dbg_clk_counter <= dbg_clk_counter+1;
|
|
|
reg [15:0] reg_val;
|
reg [15:0] reg_val;
|
reg [15:0] bcsctl1_mask;
|
reg [15:0] bcsctl1_mask;
|
reg [15:0] bcsctl2_mask;
|
reg [15:0] bcsctl2_mask;
|
|
|
initial
|
initial
|
begin
|
begin
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$display("| START SIMULATION |");
|
$display("| START SIMULATION |");
|
$display(" ===============================================");
|
$display(" ===============================================");
|
repeat(5) @(posedge mclk);
|
repeat(5) @(posedge mclk);
|
stimulus_done = 0;
|
stimulus_done = 0;
|
|
|
force tb_openMSP430.dut.wdt_reset = 1'b0;
|
force tb_openMSP430.dut.wdt_reset = 1'b0;
|
|
|
`ifdef ASIC
|
`ifdef ASIC_CLOCKING
|
|
|
// MCLK GENERATION: SELECTING DCO_CLK
|
// MCLK GENERATION: SELECTING DCO_CLK
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
// ------- Divider /1 ----------
|
// ------- Divider /1 ----------
|
@(r15 === 16'h0001);
|
@(r15 === 16'h0001);
|
@(posedge mclk);
|
@(posedge mclk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
mclk_counter = 0;
|
mclk_counter = 0;
|
repeat(735) @(posedge dco_clk);
|
repeat(735) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
|
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
|
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
|
|
|
|
|
`ifdef MCLK_DIVIDER
|
`ifdef MCLK_DIVIDER
|
// ------- Divider /2 ----------
|
// ------- Divider /2 ----------
|
@(r15 === 16'h0002);
|
@(r15 === 16'h0002);
|
@(posedge mclk);
|
@(posedge mclk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
mclk_counter = 0;
|
mclk_counter = 0;
|
repeat(735) @(posedge dco_clk);
|
repeat(735) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
if (mclk_counter !== 367) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
if (mclk_counter !== 367) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
|
|
|
|
// ------- Divider /4 ----------
|
// ------- Divider /4 ----------
|
@(r15 === 16'h0003);
|
@(r15 === 16'h0003);
|
@(posedge mclk);
|
@(posedge mclk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
mclk_counter = 0;
|
mclk_counter = 0;
|
repeat(735) @(posedge dco_clk);
|
repeat(735) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
if (mclk_counter !== 183) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
if (mclk_counter !== 183) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
|
|
|
|
// ------- Divider /8 ----------
|
// ------- Divider /8 ----------
|
@(r15 === 16'h0004);
|
@(r15 === 16'h0004);
|
@(posedge mclk);
|
@(posedge mclk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
mclk_counter = 0;
|
mclk_counter = 0;
|
repeat(735) @(posedge dco_clk);
|
repeat(735) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
if (mclk_counter !== 91) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
if (mclk_counter !== 91) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
|
|
`else
|
`else
|
// ------- Divider /2 ----------
|
// ------- Divider /2 ----------
|
@(r15 === 16'h0002);
|
@(r15 === 16'h0002);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
mclk_counter = 0;
|
mclk_counter = 0;
|
repeat(735) @(posedge dco_clk);
|
repeat(735) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
|
|
|
|
// ------- Divider /4 ----------
|
// ------- Divider /4 ----------
|
@(r15 === 16'h0003);
|
@(r15 === 16'h0003);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
mclk_counter = 0;
|
mclk_counter = 0;
|
repeat(735) @(posedge dco_clk);
|
repeat(735) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
|
|
|
|
// ------- Divider /8 ----------
|
// ------- Divider /8 ----------
|
@(r15 === 16'h0004);
|
@(r15 === 16'h0004);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
mclk_counter = 0;
|
mclk_counter = 0;
|
repeat(735) @(posedge dco_clk);
|
repeat(735) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
|
|
|
|
`endif
|
`endif
|
|
|
@(r15 === 16'h1000);
|
@(r15 === 16'h1000);
|
|
|
|
|
// MCLK GENERATION: SELECTING LFXT_CLK
|
// MCLK GENERATION: SELECTING LFXT_CLK
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
// VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_MCLK" PATTERN
|
// VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_MCLK" PATTERN
|
@(r15 === 16'h2000);
|
@(r15 === 16'h2000);
|
|
|
|
|
// ACLK GENERATION
|
// ACLK GENERATION
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
// ------- Divider /1 ----------
|
// ------- Divider /1 ----------
|
@(r15 === 16'h2001);
|
@(r15 === 16'h2001);
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
@(posedge lfxt_clk);
|
@(posedge lfxt_clk);
|
`else
|
`else
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
`endif
|
`endif
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
repeat(54) @(posedge lfxt_clk);
|
repeat(54) @(posedge lfxt_clk);
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
|
`else
|
`else
|
repeat(54) @(posedge dco_clk);
|
repeat(54) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
|
`endif
|
`endif
|
|
|
|
|
`ifdef ACLK_DIVIDER
|
`ifdef ACLK_DIVIDER
|
// ------- Divider /2 ----------
|
// ------- Divider /2 ----------
|
@(r15 === 16'h2002);
|
@(r15 === 16'h2002);
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
@(posedge lfxt_clk);
|
@(posedge lfxt_clk);
|
`else
|
`else
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
`endif
|
`endif
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
repeat(54) @(posedge lfxt_clk);
|
repeat(54) @(posedge lfxt_clk);
|
#1;
|
#1;
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
|
if (aclk_counter !== 28) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
|
if (aclk_counter !== 28) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
|
`else
|
`else
|
repeat(54) @(posedge dco_clk);
|
repeat(54) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
|
if (aclk_counter !== 27) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
|
if (aclk_counter !== 27) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
|
`endif
|
`endif
|
|
|
|
|
// ------- Divider /4 ----------
|
// ------- Divider /4 ----------
|
@(r15 === 16'h2003);
|
@(r15 === 16'h2003);
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
@(posedge lfxt_clk);
|
@(posedge lfxt_clk);
|
`else
|
`else
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
`endif
|
`endif
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
repeat(54) @(posedge lfxt_clk);
|
repeat(54) @(posedge lfxt_clk);
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
|
if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
|
if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
|
`else
|
`else
|
repeat(54) @(posedge dco_clk);
|
repeat(54) @(posedge dco_clk);
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
|
if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
|
if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
|
`endif
|
`endif
|
|
|
|
|
// ------- Divider /8 ----------
|
// ------- Divider /8 ----------
|
@(r15 === 16'h2004);
|
@(r15 === 16'h2004);
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
@(posedge lfxt_clk);
|
@(posedge lfxt_clk);
|
`else
|
`else
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
`endif
|
`endif
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
repeat(54) @(posedge lfxt_clk);
|
repeat(54) @(posedge lfxt_clk);
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
`else
|
`else
|
repeat(54) @(posedge dco_clk);
|
repeat(54) @(posedge dco_clk);
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
`endif
|
`endif
|
|
|
`else
|
`else
|
// ------- Divider /2 ----------
|
// ------- Divider /2 ----------
|
@(r15 === 16'h2002);
|
@(r15 === 16'h2002);
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
@(posedge lfxt_clk);
|
@(posedge lfxt_clk);
|
`else
|
`else
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
`endif
|
`endif
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
repeat(54) @(posedge lfxt_clk);
|
repeat(54) @(posedge lfxt_clk);
|
#1;
|
#1;
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
|
`else
|
`else
|
repeat(54) @(posedge dco_clk);
|
repeat(54) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
|
`endif
|
`endif
|
|
|
|
|
// ------- Divider /4 ----------
|
// ------- Divider /4 ----------
|
@(r15 === 16'h2003);
|
@(r15 === 16'h2003);
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
@(posedge lfxt_clk);
|
@(posedge lfxt_clk);
|
`else
|
`else
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
`endif
|
`endif
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
repeat(54) @(posedge lfxt_clk);
|
repeat(54) @(posedge lfxt_clk);
|
#1;
|
#1;
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
|
`else
|
`else
|
repeat(54) @(posedge dco_clk);
|
repeat(54) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
|
`endif
|
`endif
|
|
|
|
|
// ------- Divider /8 ----------
|
// ------- Divider /8 ----------
|
@(r15 === 16'h2004);
|
@(r15 === 16'h2004);
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
@(posedge lfxt_clk);
|
@(posedge lfxt_clk);
|
`else
|
`else
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
`endif
|
`endif
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
lfxt_clk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
repeat(54) @(posedge lfxt_clk);
|
repeat(54) @(posedge lfxt_clk);
|
#1;
|
#1;
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
`else
|
`else
|
repeat(54) @(posedge dco_clk);
|
repeat(54) @(posedge dco_clk);
|
#1;
|
#1;
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
`endif
|
`endif
|
|
|
`endif
|
`endif
|
|
|
@(r15 === 16'h3000);
|
@(r15 === 16'h3000);
|
|
|
|
|
// SMCLK GENERATION - DCO_CLK INPUT
|
// SMCLK GENERATION - DCO_CLK INPUT
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
// ------- Divider /1 ----------
|
// ------- Divider /1 ----------
|
@(r15 === 16'h3001);
|
@(r15 === 16'h3001);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
repeat(600) @(posedge dco_clk);
|
repeat(600) @(posedge dco_clk);
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
|
|
|
`ifdef SMCLK_DIVIDER
|
`ifdef SMCLK_DIVIDER
|
// ------- Divider /2 ----------
|
// ------- Divider /2 ----------
|
@(r15 === 16'h3002);
|
@(r15 === 16'h3002);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
repeat(600) @(posedge dco_clk);
|
repeat(600) @(posedge dco_clk);
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
|
|
|
|
// ------- Divider /4 ----------
|
// ------- Divider /4 ----------
|
@(r15 === 16'h3003);
|
@(r15 === 16'h3003);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
repeat(600) @(posedge dco_clk);
|
repeat(600) @(posedge dco_clk);
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
|
|
|
|
// ------- Divider /8 ----------
|
// ------- Divider /8 ----------
|
@(r15 === 16'h3004);
|
@(r15 === 16'h3004);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
repeat(600) @(posedge dco_clk);
|
repeat(600) @(posedge dco_clk);
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
|
|
`else
|
`else
|
// ------- Divider /2 ----------
|
// ------- Divider /2 ----------
|
@(r15 === 16'h3002);
|
@(r15 === 16'h3002);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
repeat(600) @(posedge dco_clk);
|
repeat(600) @(posedge dco_clk);
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
|
|
|
|
// ------- Divider /4 ----------
|
// ------- Divider /4 ----------
|
@(r15 === 16'h3003);
|
@(r15 === 16'h3003);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
repeat(600) @(posedge dco_clk);
|
repeat(600) @(posedge dco_clk);
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
|
|
|
|
// ------- Divider /8 ----------
|
// ------- Divider /8 ----------
|
@(r15 === 16'h3004);
|
@(r15 === 16'h3004);
|
@(posedge dco_clk);
|
@(posedge dco_clk);
|
#1;
|
#1;
|
dco_clk_counter = 0;
|
dco_clk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
repeat(600) @(posedge dco_clk);
|
repeat(600) @(posedge dco_clk);
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
|
|
`endif
|
`endif
|
|
|
@(r15 === 16'h4000);
|
@(r15 === 16'h4000);
|
|
|
|
|
// SMCLK GENERATION - LFXT_CLK INPUT
|
// SMCLK GENERATION - LFXT_CLK INPUT
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
// VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_SMCLK" PATTERN
|
// VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_SMCLK" PATTERN
|
@(r15 === 16'h5000);
|
@(r15 === 16'h5000);
|
|
|
|
|
// CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT
|
// CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
@(r15 === 16'h5001);
|
@(r15 === 16'h5001);
|
repeat(50) @(negedge dco_clk);
|
repeat(50) @(negedge dco_clk);
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
|
cpu_en = 1'b0;
|
cpu_en = 1'b0;
|
#(3*763*2);
|
#(3*763*2);
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk counters
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk counters
|
mclk_counter = 0;
|
mclk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
|
|
#(50*500); // Make sure that the CPU is stopped
|
#(50*500); // Make sure that the CPU is stopped
|
if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");
|
if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");
|
if (mclk_counter !== 0) tb_error("====== MCLK is not stopped (test 4) =====");
|
if (mclk_counter !== 0) tb_error("====== MCLK is not stopped (test 4) =====");
|
`ifdef OSCOFF_EN
|
`ifdef OSCOFF_EN
|
if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 5) =====");
|
if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 5) =====");
|
`else
|
`else
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
`ifdef ACLK_DIVIDER
|
`ifdef ACLK_DIVIDER
|
if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");
|
if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");
|
`else
|
`else
|
if (aclk_counter !== 17) tb_error("====== ACLK is not running (test 5) =====");
|
if (aclk_counter !== 17) tb_error("====== ACLK is not running (test 5) =====");
|
`endif
|
`endif
|
`else
|
`else
|
if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");
|
if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");
|
`endif
|
`endif
|
`endif
|
`endif
|
if (smclk_counter !== 0) tb_error("====== SMCLK is not stopped (test 6) =====");
|
if (smclk_counter !== 0) tb_error("====== SMCLK is not stopped (test 6) =====");
|
cpu_en = 1'b1;
|
cpu_en = 1'b1;
|
|
|
#(50*500); // Make sure that the CPU runs again
|
#(50*500); // Make sure that the CPU runs again
|
if (reg_val == r14) tb_error("====== CPU is not running (test 7) =====");
|
if (reg_val == r14) tb_error("====== CPU is not running (test 7) =====");
|
if (mclk_counter == 0) tb_error("====== MCLK is not running (test 8) =====");
|
if (mclk_counter == 0) tb_error("====== MCLK is not running (test 8) =====");
|
if (aclk_counter == 0) tb_error("====== ACLK is not running (test 9) =====");
|
if (aclk_counter == 0) tb_error("====== ACLK is not running (test 9) =====");
|
if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 10) =====");
|
if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 10) =====");
|
|
|
|
|
@(r15 === 16'h5002);
|
@(r15 === 16'h5002);
|
`ifdef DBG_EN
|
`ifdef DBG_EN
|
repeat(50) @(posedge dco_clk);
|
repeat(50) @(posedge dco_clk);
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 2) =====");
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 2) =====");
|
|
|
dbg_en = 1'b1;
|
dbg_en = 1'b1;
|
repeat(6) @(posedge mclk);
|
repeat(6) @(posedge mclk);
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
|
mclk_counter = 0;
|
mclk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
dbg_clk_counter = 0;
|
dbg_clk_counter = 0;
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 3) =====");
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 3) =====");
|
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 4) =====");
|
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 4) =====");
|
|
|
repeat(500) @(posedge dco_clk); // Make sure that the DBG interface runs
|
repeat(500) @(posedge dco_clk); // Make sure that the DBG interface runs
|
if (reg_val == r14) tb_error("====== CPU is stopped (test 5) =====");
|
if (reg_val == r14) tb_error("====== CPU is stopped (test 5) =====");
|
if (mclk_counter == 0) tb_error("====== MCLK is stopped (test 6) =====");
|
if (mclk_counter == 0) tb_error("====== MCLK is stopped (test 6) =====");
|
if (aclk_counter == 0) tb_error("====== ACLK is stopped (test 7) =====");
|
if (aclk_counter == 0) tb_error("====== ACLK is stopped (test 7) =====");
|
if (smclk_counter == 0) tb_error("====== SMCLK is stopped (test 8) =====");
|
if (smclk_counter == 0) tb_error("====== SMCLK is stopped (test 8) =====");
|
if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is stopped (test 9) =====");
|
if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is stopped (test 9) =====");
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
|
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 11) =====");
|
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 11) =====");
|
|
|
dbg_en = 1'b0;
|
dbg_en = 1'b0;
|
repeat(6) @(posedge mclk);
|
repeat(6) @(posedge mclk);
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
|
mclk_counter = 0;
|
mclk_counter = 0;
|
aclk_counter = 0;
|
aclk_counter = 0;
|
smclk_counter = 0;
|
smclk_counter = 0;
|
dbg_clk_counter = 0;
|
dbg_clk_counter = 0;
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 12) =====");
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 12) =====");
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 13) =====");
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 13) =====");
|
|
|
repeat(500) @(posedge dco_clk); // Make sure that the DBG interface is stopped
|
repeat(500) @(posedge dco_clk); // Make sure that the DBG interface is stopped
|
if (reg_val == r14) tb_error("====== CPU is not running (test 14) =====");
|
if (reg_val == r14) tb_error("====== CPU is not running (test 14) =====");
|
if (mclk_counter == 0) tb_error("====== MCLK is not running (test 15) =====");
|
if (mclk_counter == 0) tb_error("====== MCLK is not running (test 15) =====");
|
if (aclk_counter == 0) tb_error("====== ACLK is not running (test 16) =====");
|
if (aclk_counter == 0) tb_error("====== ACLK is not running (test 16) =====");
|
if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 17) =====");
|
if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 17) =====");
|
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 18) =====");
|
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 18) =====");
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 19) =====");
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 19) =====");
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 20) =====");
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 20) =====");
|
|
|
if (r15 !== 16'h5002) tb_error("====== DBG_EN did generate a PUC reset (test 21) =====");
|
if (r15 !== 16'h5002) tb_error("====== DBG_EN did generate a PUC reset (test 21) =====");
|
`endif
|
`endif
|
|
|
@(r15 === 16'h6000);
|
@(r15 === 16'h6000);
|
|
|
|
|
// RD/WR ACCESS TO REGISTERS
|
// RD/WR ACCESS TO REGISTERS
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
bcsctl1_mask = 16'h0000;
|
bcsctl1_mask = 16'h0000;
|
bcsctl2_mask = 16'h0000;
|
bcsctl2_mask = 16'h0000;
|
|
|
`ifdef ASIC
|
`ifdef ASIC_CLOCKING
|
`ifdef ACLK_DIVIDER
|
`ifdef ACLK_DIVIDER
|
bcsctl1_mask = bcsctl1_mask | 16'h0030;
|
bcsctl1_mask = bcsctl1_mask | 16'h0030;
|
`endif
|
`endif
|
`else
|
`else
|
bcsctl1_mask = bcsctl1_mask | 16'h0030;
|
bcsctl1_mask = bcsctl1_mask | 16'h0030;
|
`endif
|
`endif
|
|
|
`ifdef MCLK_MUX
|
`ifdef MCLK_MUX
|
bcsctl2_mask = bcsctl2_mask | 16'h0080;
|
bcsctl2_mask = bcsctl2_mask | 16'h0080;
|
`endif
|
`endif
|
`ifdef MCLK_DIVIDER
|
`ifdef MCLK_DIVIDER
|
bcsctl2_mask = bcsctl2_mask | 16'h0030;
|
bcsctl2_mask = bcsctl2_mask | 16'h0030;
|
`endif
|
`endif
|
`ifdef ASIC
|
`ifdef ASIC_CLOCKING
|
`ifdef SMCLK_MUX
|
`ifdef SMCLK_MUX
|
bcsctl2_mask = bcsctl2_mask | 16'h0008;
|
bcsctl2_mask = bcsctl2_mask | 16'h0008;
|
`endif
|
`endif
|
`ifdef SMCLK_DIVIDER
|
`ifdef SMCLK_DIVIDER
|
bcsctl2_mask = bcsctl2_mask | 16'h0006;
|
bcsctl2_mask = bcsctl2_mask | 16'h0006;
|
`endif
|
`endif
|
`else
|
`else
|
bcsctl2_mask = bcsctl2_mask | 16'h0008;
|
bcsctl2_mask = bcsctl2_mask | 16'h0008;
|
bcsctl2_mask = bcsctl2_mask | 16'h0006;
|
bcsctl2_mask = bcsctl2_mask | 16'h0006;
|
`endif
|
`endif
|
|
|
@(r15 === 16'h7000);
|
@(r15 === 16'h7000);
|
if (r4 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
|
if (r4 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
|
if (r5 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
|
if (r5 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
|
|
|
if (r6 !== bcsctl1_mask) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
|
if (r6 !== bcsctl1_mask) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
|
if (r7 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
|
if (r7 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
|
|
|
if (r8 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
|
if (r8 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
|
if (r9 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
|
if (r9 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
|
|
|
if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
|
if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
|
if (r11 !== bcsctl2_mask) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
|
if (r11 !== bcsctl2_mask) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
|
|
|
if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
|
if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
|
if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
|
if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
|
|
|
|
|
`else
|
`else
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$display("| SIMULATION SKIPPED |");
|
$display("| SIMULATION SKIPPED |");
|
$display("| (this test is not supported in FPGA mode) |");
|
$display("| (this test is not supported in FPGA mode) |");
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$finish;
|
$finish;
|
`endif
|
`endif
|
|
|
stimulus_done = 1;
|
stimulus_done = 1;
|
end
|
end
|
|
|
|
|