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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_sync.s43] - Diff between revs 134 and 141

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/*===========================================================================*/
/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/* disclaimer.                                                               */
/*                                                                           */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/* (at your option) any later version.                                       */
/*                                                                           */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/* License for more details.                                                 */
/*                                                                           */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*                                                                           */
/*===========================================================================*/
/*===========================================================================*/
/*                            DEBUG INTERFACE:  UART                         */
/*                            DEBUG INTERFACE:  UART                         */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* Test the UART debug interface:                                            */
/* Test the UART debug interface:                                            */
/*                        - Check synchronization of the serial              */
/*                        - Check synchronization of the serial              */
/*                          debug interface input.                           */
/*                          debug interface input.                           */
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
.set   DMEM_BASE, (__data_start     )
.include "pmem_defs.asm"
.set   DMEM_200,  (__data_start+0x00)
 
.set   DMEM_250,  (__data_start+0x50)
 
 
 
.global main
.global main
.macro LPM0
.macro LPM0
 bis    #0x0010, r2
 bis    #0x0010, r2
.endm
.endm
main:
main:
        mov #DMEM_250, r1       ; # Initialize stack pointer
        mov #DMEM_250, r1       ; # Initialize stack pointer
        mov   #0x0000, &DMEM_200
        mov   #0x0000, &DMEM_200
        mov   #0x0000, r15
        mov   #0x0000, r15
        eint
        eint
        LPM0
        LPM0
        mov   #0x1000, r15
        mov   #0x1000, r15
        /* ----------------------         END OF TEST        --------------- */
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
end_of_test:
        mov #0x0010, r14
        mov #0x0010, r14
  wait_loop:
  wait_loop:
        dec r14
        dec r14
        jnz wait_loop
        jnz wait_loop
        nop
        nop
        br #0xffff
        br #0xffff
        /* ----------------------         INTERRUPT VECTORS  --------------- */
        /* ----------------------         INTERRUPT VECTORS  --------------- */
.section .vectors, "a"
.section .vectors, "a"
.word end_of_test        ; Interrupt  0 (lowest priority)    
.word end_of_test        ; Interrupt  0 (lowest priority)    
.word end_of_test        ; Interrupt  1                      
.word end_of_test        ; Interrupt  1                      
.word end_of_test        ; Interrupt  2                      
.word end_of_test        ; Interrupt  2                      
.word end_of_test        ; Interrupt  3                      
.word end_of_test        ; Interrupt  3                      
.word end_of_test        ; Interrupt  4                      
.word end_of_test        ; Interrupt  4                      
.word end_of_test        ; Interrupt  5                      
.word end_of_test        ; Interrupt  5                      
.word end_of_test        ; Interrupt  6                      
.word end_of_test        ; Interrupt  6                      
.word end_of_test        ; Interrupt  7                      
.word end_of_test        ; Interrupt  7                      
.word end_of_test        ; Interrupt  8                      
.word end_of_test        ; Interrupt  8                      
.word end_of_test        ; Interrupt  9                      
.word end_of_test        ; Interrupt  9                      
.word end_of_test        ; Interrupt 10                      Watchdog timer
.word end_of_test        ; Interrupt 10                      Watchdog timer
.word end_of_test        ; Interrupt 11                      
.word end_of_test        ; Interrupt 11                      
.word end_of_test        ; Interrupt 12                      
.word end_of_test        ; Interrupt 12                      
.word end_of_test        ; Interrupt 13                      
.word end_of_test        ; Interrupt 13                      
.word end_of_test        ; Interrupt 14                      NMI
.word end_of_test        ; Interrupt 14                      NMI
.word main               ; Interrupt 15 (highest priority)   RESET
.word main               ; Interrupt 15 (highest priority)   RESET
 
 

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