/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* DEBUG INTERFACE: UART */
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/* DEBUG INTERFACE: UART */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the UART debug interface: */
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/* Test the UART debug interface: */
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/* - Check synchronization of the serial */
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/* - Check synchronization of the serial */
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/* debug interface input. */
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/* debug interface input. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $ */
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/* $Rev: 95 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define VERY_LONG_TIMEOUT
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`define VERY_LONG_TIMEOUT
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integer ii;
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integer ii;
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reg [15:0] jj;
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reg [15:0] jj;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_EN
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`ifdef DBG_UART
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`ifdef DBG_UART
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#1 dbg_en = 1;
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#1 dbg_en = 1;
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repeat(30) @(posedge mclk);
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repeat(30) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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// Enable metastablity emulation for the RXD path
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// Enable metastablity emulation for the RXD path
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dbg_uart_rxd_meta = 1'b1;
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dbg_uart_rxd_meta = 1'b1;
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//--------------------------------------------------------
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//--------------------------------------------------------
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// TRY VARIOUS SERIAL DEBUG INTERFACE TRANSFER
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// TRY VARIOUS SERIAL DEBUG INTERFACE TRANSFER
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// WITH DIFFERENT BAUD-RATES
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// WITH DIFFERENT BAUD-RATES
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//--------------------------------------------------------
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//--------------------------------------------------------
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for ( ii=0; ii < 500; ii=ii+1)
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for ( ii=0; ii < 500; ii=ii+1)
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begin
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begin
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#1 reset_n = 0;
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#1 reset_n = 0;
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repeat(1) @(posedge mclk);
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repeat(1) @(posedge mclk);
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#1 reset_n = 1;
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#1 reset_n = 1;
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repeat(10) @(posedge mclk);
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repeat(10) @(posedge mclk);
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UART_PERIOD = 650 + 1*ii;
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UART_PERIOD = 650 + 1*ii;
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$display("Synchronisation test for DBG_UART_PERIOD = %5d ns / ii = %-d", UART_PERIOD, ii);
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$display("Synchronisation test for DBG_UART_PERIOD = %5d ns / ii = %-d", UART_PERIOD, ii);
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// SEND UART SYNCHRONIZATION FRAME
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// SEND UART SYNCHRONIZATION FRAME
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dbg_uart_sync;
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dbg_uart_sync;
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// READ CPU_ID
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// READ CPU_ID
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dbg_uart_rd(CPU_ID_LO);
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dbg_uart_rd(CPU_ID_LO);
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if (dbg_uart_buf !== dbg_cpu_id[15:0])
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if (dbg_uart_buf !== dbg_cpu_id[15:0])
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begin
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begin
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$display("CPU_ID_LO: read = 0x%-4h / expected = 0x%-4h", dbg_uart_buf, dbg_cpu_id[15:0]);
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$display("CPU_ID_LO: read = 0x%-4h / expected = 0x%-4h", dbg_uart_buf, dbg_cpu_id[15:0]);
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tb_error("====== CPU_ID_LO incorrect (test 1) =====");
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tb_error("====== CPU_ID_LO incorrect (test 1) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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dbg_uart_rd(CPU_ID_HI);
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dbg_uart_rd(CPU_ID_HI);
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if (dbg_uart_buf !== dbg_cpu_id[31:16])
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if (dbg_uart_buf !== dbg_cpu_id[31:16])
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begin
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begin
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$display("CPU_ID_HI: read = 0x%-4h / expected = 0x%-4h", dbg_uart_buf, dbg_cpu_id[31:16]);
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$display("CPU_ID_HI: read = 0x%-4h / expected = 0x%-4h", dbg_uart_buf, dbg_cpu_id[31:16]);
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tb_error("====== CPU_ID_HI incorrect (test 1) =====");
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tb_error("====== CPU_ID_HI incorrect (test 1) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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//-----------------------------------
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//-----------------------------------
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// MAKE SOME READ/WRITE ACCESS
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// MAKE SOME READ/WRITE ACCESS
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//-----------------------------------
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//-----------------------------------
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jj = 'h4328;
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jj = 'h4328;
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dbg_uart_wr(MEM_DATA, 16'h4328);
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dbg_uart_wr(MEM_DATA, 16'h4328);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h4328)
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if (dbg_uart_buf !== 16'h4328)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x4328", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x4328", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 1) =====");
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tb_error("====== MEM_DATA incorrect (test 1) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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jj = 'h3280;
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jj = 'h3280;
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dbg_uart_wr(MEM_DATA, 16'h3280);
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dbg_uart_wr(MEM_DATA, 16'h3280);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h3280)
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if (dbg_uart_buf !== 16'h3280)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x3280", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x3280", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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jj = 'h2800;
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jj = 'h2800;
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dbg_uart_wr(MEM_DATA, 16'h2800);
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dbg_uart_wr(MEM_DATA, 16'h2800);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h2800)
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if (dbg_uart_buf !== 16'h2800)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x2800", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x2800", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 1) =====");
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tb_error("====== MEM_DATA incorrect (test 1) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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jj = 'h8000;
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jj = 'h8000;
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dbg_uart_wr(MEM_DATA, 16'h8000);
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dbg_uart_wr(MEM_DATA, 16'h8000);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h8000)
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if (dbg_uart_buf !== 16'h8000)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x8000", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x8000", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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jj = 'h0000;
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jj = 'h0000;
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dbg_uart_wr(MEM_DATA, 16'h0000);
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dbg_uart_wr(MEM_DATA, 16'h0000);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h0000)
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if (dbg_uart_buf !== 16'h0000)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x0000", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x0000", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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jj = 'hffff;
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jj = 'hffff;
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dbg_uart_wr(MEM_DATA, 16'hffff);
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dbg_uart_wr(MEM_DATA, 16'hffff);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'hffff)
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if (dbg_uart_buf !== 16'hffff)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0xffff", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0xffff", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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jj = 'h7f7f;
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jj = 'h7f7f;
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dbg_uart_wr(MEM_DATA, 16'h7f7f);
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dbg_uart_wr(MEM_DATA, 16'h7f7f);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h7f7f)
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if (dbg_uart_buf !== 16'h7f7f)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x7f7f", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x7f7f", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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jj = 'h55aa;
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jj = 'h55aa;
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dbg_uart_wr(MEM_DATA, 16'h55aa);
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dbg_uart_wr(MEM_DATA, 16'h55aa);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h55aa)
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if (dbg_uart_buf !== 16'h55aa)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x55aa", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x55aa", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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jj = 'h5aa5;
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jj = 'h5aa5;
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dbg_uart_wr(MEM_DATA, 16'h5aa5);
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dbg_uart_wr(MEM_DATA, 16'h5aa5);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h5aa5)
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if (dbg_uart_buf !== 16'h5aa5)
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begin
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begin
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x5aa5", dbg_uart_buf);
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$display("DMEM_DATA: read = 0x%-4h / expected = 0x5aa5", dbg_uart_buf);
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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tb_error("====== MEM_DATA incorrect (test 2) =====");
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force_end_of_sim;
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force_end_of_sim;
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end
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end
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end
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end
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//--------------------------------------------------------
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//--------------------------------------------------------
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// TRY LONGEST POSSIBLE SYNCHRONIZATION FRAME
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// TRY LONGEST POSSIBLE SYNCHRONIZATION FRAME
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//--------------------------------------------------------
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//--------------------------------------------------------
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#1 reset_n = 0;
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#1 reset_n = 0;
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repeat(1) @(posedge mclk);
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repeat(1) @(posedge mclk);
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#1 reset_n = 1;
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#1 reset_n = 1;
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repeat(10) @(posedge mclk);
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repeat(10) @(posedge mclk);
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dbg_uart_rxd_pre = 1'b0;
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dbg_uart_rxd_pre = 1'b0;
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@(posedge dut.dbg_0.dbg_uart_0.sync_cnt[`DBG_UART_XFER_CNT_W+2]);
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@(posedge dut.dbg_0.dbg_uart_0.sync_cnt[`DBG_UART_XFER_CNT_W+2]);
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dbg_uart_rxd_pre = 1'b1;
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dbg_uart_rxd_pre = 1'b1;
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repeat(100) @(posedge mclk);
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repeat(100) @(posedge mclk);
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dbg_uart_rxd_pre = 1'b0;
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dbg_uart_rxd_pre = 1'b0;
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@(posedge dut.dbg_0.dbg_uart_0.xfer_cnt[`DBG_UART_XFER_CNT_W-1]);
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@(posedge dut.dbg_0.dbg_uart_0.xfer_cnt[`DBG_UART_XFER_CNT_W-1]);
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dbg_uart_rxd_pre = 1'b1;
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dbg_uart_rxd_pre = 1'b1;
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repeat(100) @(posedge mclk);
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repeat(100) @(posedge mclk);
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//--------------------------------------------------------
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//--------------------------------------------------------
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// END OF TEST
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// END OF TEST
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//--------------------------------------------------------
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//--------------------------------------------------------
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#1 reset_n = 0;
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#1 reset_n = 0;
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repeat(1) @(posedge mclk);
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repeat(1) @(posedge mclk);
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#1 reset_n = 1;
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#1 reset_n = 1;
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repeat(10) @(posedge mclk);
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repeat(10) @(posedge mclk);
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UART_PERIOD = 550;
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UART_PERIOD = 550;
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$display("Synchronisation test for DBG_UART_PERIOD = %5d ns / ii = %-d", UART_PERIOD, ii);
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$display("Synchronisation test for DBG_UART_PERIOD = %5d ns / ii = %-d", UART_PERIOD, ii);
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// SEND UART SYNCHRONIZATION FRAME
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// SEND UART SYNCHRONIZATION FRAME
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dbg_uart_sync;
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dbg_uart_sync;
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// Let the CPU run
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// Let the CPU run
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dbg_uart_wr(CPU_CTL, 16'h0002);
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dbg_uart_wr(CPU_CTL, 16'h0002);
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// Generate an IRQ
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// Generate an IRQ
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wkup[0] = 1'b1;
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wkup[0] = 1'b1;
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@(negedge mclk);
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@(negedge mclk);
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irq[0] = 1'b1;
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irq[`IRQ_NR-16] = 1'b1;
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@(negedge irq_acc[0])
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@(negedge irq_acc[`IRQ_NR-16])
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@(negedge mclk);
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@(negedge mclk);
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wkup[0] = 1'b0;
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wkup[0] = 1'b0;
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irq[0] = 1'b0;
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irq[`IRQ_NR-16] = 1'b0;
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repeat(10) @(posedge mclk);
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repeat(10) @(posedge mclk);
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stimulus_done = 1;
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stimulus_done = 1;
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`else
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`else
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| SIMULATION SKIPPED |");
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$display("| (serial debug interface UART not included) |");
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$display("| (serial debug interface UART not included) |");
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$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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`endif
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`endif
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`else
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`else
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| SIMULATION SKIPPED |");
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$display("| (serial debug interface not included) |");
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$display("| (serial debug interface not included) |");
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$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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`endif
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`endif
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end
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end
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task force_end_of_sim;
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task force_end_of_sim;
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begin
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begin
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repeat(10) @(posedge mclk);
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repeat(10) @(posedge mclk);
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| SIMULATION FAILED |");
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$display("| SIMULATION FAILED |");
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$display("| (some verilog stimulus checks failed) |");
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$display("| (some verilog stimulus checks failed) |");
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$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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end
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end
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endtask
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endtask
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