/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* DIGITAL I/O */
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/* DIGITAL I/O */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the Digital I/O interface: */
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/* Test the Digital I/O interface: */
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/* - Interrupts. */
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/* - Interrupts. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 111 $ */
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/* $Rev: 141 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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.global main
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.include "pmem_defs.asm"
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.set DMEM_BASE, (__data_start )
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.set DMEM_200, (__data_start+0x00)
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.set DMEM_208, (__data_start+0x08)
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.set DMEM_210, (__data_start+0x10)
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.set DMEM_218, (__data_start+0x18)
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.set DMEM_220, (__data_start+0x20)
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.set DMEM_228, (__data_start+0x28)
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.set DMEM_230, (__data_start+0x30)
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.set DMEM_238, (__data_start+0x38)
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.set DMEM_240, (__data_start+0x40)
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.set DMEM_248, (__data_start+0x48)
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.set DMEM_250, (__data_start+0x50)
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.set DMEM_258, (__data_start+0x58)
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.set DMEM_260, (__data_start+0x60)
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.set P1IN, 0x0020
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.global main
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.set P1OUT, 0x0021
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.set P1DIR, 0x0022
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.set P1IFG, 0x0023
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.set P1IES, 0x0024
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.set P1IE, 0x0025
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.set P1SEL, 0x0026
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.set P2IN, 0x0028
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.set P2OUT, 0x0029
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.set P2DIR, 0x002A
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.set P2IFG, 0x002B
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.set P2IES, 0x002C
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.set P2IE, 0x002D
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.set P2SEL, 0x002E
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main:
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main:
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; Disable interrupts
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; Disable interrupts
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dint
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dint
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mov.b #0x00, &P1IE
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mov.b #0x00, &P1IE
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mov.b #0x00, &P2IE
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mov.b #0x00, &P2IE
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/* -------------- PORT 1: TEST INTERRUPT FLAGS --------------- */
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/* -------------- PORT 1: TEST INTERRUPT FLAGS --------------- */
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mov.b #0x00, &P1IES ;# TEST IF RISING EDGE ENABLED
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mov.b #0x00, &P1IES ;# TEST IF RISING EDGE ENABLED
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mov #DMEM_200, r15 ;# Make sure rising edge is detected test 1
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mov #DMEM_200, r15 ;# Make sure rising edge is detected test 1
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p1ifg_re_loop1:
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p1ifg_re_loop1:
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nop
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nop
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nop
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nop
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mov.b &P1IFG, 0(r15)
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mov.b &P1IFG, 0(r15)
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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inc r15
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inc r15
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cmp #DMEM_208, r15
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cmp #DMEM_208, r15
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jne p1ifg_re_loop1
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jne p1ifg_re_loop1
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mov #DMEM_210, r15 ;# Make sure falling edge is ignored
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mov #DMEM_210, r15 ;# Make sure falling edge is ignored
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p1ifg_fe_loop1:
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p1ifg_fe_loop1:
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nop
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nop
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nop
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nop
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mov.b &P1IFG, 0(r15)
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mov.b &P1IFG, 0(r15)
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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inc r15
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inc r15
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cmp #DMEM_218, r15
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cmp #DMEM_218, r15
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jne p1ifg_fe_loop1
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jne p1ifg_fe_loop1
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mov #DMEM_220, r15 ;# Make sure rising edge is detected test 2
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mov #DMEM_220, r15 ;# Make sure rising edge is detected test 2
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p1ifg_re_loop2:
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p1ifg_re_loop2:
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nop
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nop
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nop
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nop
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mov.b &P1IFG, 0(r15)
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mov.b &P1IFG, 0(r15)
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inc r15
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inc r15
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cmp #DMEM_228, r15
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cmp #DMEM_228, r15
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jne p1ifg_re_loop2
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jne p1ifg_re_loop2
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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mov.b #0xff, &P1IES ;# TEST IF FALLING EDGE ENABLED
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mov.b #0xff, &P1IES ;# TEST IF FALLING EDGE ENABLED
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mov #DMEM_230, r15 ;# Make sure falling edge is detected test 1
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mov #DMEM_230, r15 ;# Make sure falling edge is detected test 1
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p1ifg_fe_loop2:
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p1ifg_fe_loop2:
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nop
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nop
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nop
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nop
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mov.b &P1IFG, 0(r15)
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mov.b &P1IFG, 0(r15)
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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inc r15
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inc r15
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cmp #DMEM_238, r15
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cmp #DMEM_238, r15
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jne p1ifg_fe_loop2
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jne p1ifg_fe_loop2
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mov #DMEM_240, r15 ;# Make sure rising edge is ignored
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mov #DMEM_240, r15 ;# Make sure rising edge is ignored
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p1ifg_re_loop3:
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p1ifg_re_loop3:
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nop
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nop
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nop
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nop
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mov.b &P1IFG, 0(r15)
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mov.b &P1IFG, 0(r15)
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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inc r15
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inc r15
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cmp #DMEM_248, r15
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cmp #DMEM_248, r15
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jne p1ifg_re_loop3
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jne p1ifg_re_loop3
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mov #DMEM_250, r15 ;# Make sure falling edge is detected test 2
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mov #DMEM_250, r15 ;# Make sure falling edge is detected test 2
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p1ifg_fe_loop3:
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p1ifg_fe_loop3:
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nop
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nop
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nop
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nop
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mov.b &P1IFG, 0(r15)
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mov.b &P1IFG, 0(r15)
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inc r15
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inc r15
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cmp #DMEM_258, r15
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cmp #DMEM_258, r15
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jne p1ifg_fe_loop3
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jne p1ifg_fe_loop3
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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/* -------------- PORT 2: TEST INTERRUPT FLAGS --------------- */
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/* -------------- PORT 2: TEST INTERRUPT FLAGS --------------- */
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mov.b #0x00, &P2IES ;# TEST IF RISING EDGE ENABLED
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mov.b #0x00, &P2IES ;# TEST IF RISING EDGE ENABLED
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mov #DMEM_200, r15 ;# Make sure rising edge is detected test 1
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mov #DMEM_200, r15 ;# Make sure rising edge is detected test 1
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p2ifg_re_loop1:
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p2ifg_re_loop1:
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nop
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nop
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nop
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nop
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mov.b &P2IFG, 0(r15)
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mov.b &P2IFG, 0(r15)
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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inc r15
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inc r15
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cmp #DMEM_208, r15
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cmp #DMEM_208, r15
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jne p2ifg_re_loop1
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jne p2ifg_re_loop1
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mov #DMEM_210, r15 ;# Make sure falling edge is ignored
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mov #DMEM_210, r15 ;# Make sure falling edge is ignored
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p2ifg_fe_loop1:
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p2ifg_fe_loop1:
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nop
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nop
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nop
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nop
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mov.b &P2IFG, 0(r15)
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mov.b &P2IFG, 0(r15)
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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inc r15
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inc r15
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cmp #DMEM_218, r15
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cmp #DMEM_218, r15
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jne p2ifg_fe_loop1
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jne p2ifg_fe_loop1
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mov #DMEM_220, r15 ;# Make sure rising edge is detected test 2
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mov #DMEM_220, r15 ;# Make sure rising edge is detected test 2
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p2ifg_re_loop2:
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p2ifg_re_loop2:
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nop
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nop
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nop
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nop
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mov.b &P2IFG, 0(r15)
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mov.b &P2IFG, 0(r15)
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inc r15
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inc r15
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cmp #DMEM_228, r15
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cmp #DMEM_228, r15
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jne p2ifg_re_loop2
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jne p2ifg_re_loop2
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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mov.b #0xff, &P2IES ;# TEST IF FALLING EDGE ENABLED
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mov.b #0xff, &P2IES ;# TEST IF FALLING EDGE ENABLED
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mov #DMEM_230, r15 ;# Make sure falling edge is detected test 1
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mov #DMEM_230, r15 ;# Make sure falling edge is detected test 1
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p2ifg_fe_loop2:
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p2ifg_fe_loop2:
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nop
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nop
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nop
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nop
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mov.b &P2IFG, 0(r15)
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mov.b &P2IFG, 0(r15)
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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inc r15
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inc r15
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cmp #DMEM_238, r15
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cmp #DMEM_238, r15
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jne p2ifg_fe_loop2
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jne p2ifg_fe_loop2
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mov #DMEM_240, r15 ;# Make sure rising edge is ignored
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mov #DMEM_240, r15 ;# Make sure rising edge is ignored
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p2ifg_re_loop3:
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p2ifg_re_loop3:
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nop
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nop
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nop
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nop
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mov.b &P2IFG, 0(r15)
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mov.b &P2IFG, 0(r15)
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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inc r15
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inc r15
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cmp #DMEM_248, r15
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cmp #DMEM_248, r15
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jne p2ifg_re_loop3
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jne p2ifg_re_loop3
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mov #DMEM_250, r15 ;# Make sure falling edge is detected test 2
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mov #DMEM_250, r15 ;# Make sure falling edge is detected test 2
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p2ifg_fe_loop3:
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p2ifg_fe_loop3:
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nop
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nop
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nop
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nop
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mov.b &P2IFG, 0(r15)
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mov.b &P2IFG, 0(r15)
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inc r15
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inc r15
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cmp #DMEM_258, r15
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cmp #DMEM_258, r15
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jne p2ifg_fe_loop3
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jne p2ifg_fe_loop3
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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/* -------------- CLEAR MEMORY --------------- */
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/* -------------- CLEAR MEMORY --------------- */
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mov #DMEM_200, r5
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mov #DMEM_200, r5
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mem_clear_loop:
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mem_clear_loop:
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mov #0x00, 0(r5)
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mov #0x00, 0(r5)
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incd r5
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incd r5
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cmp #DMEM_260, r5
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cmp #DMEM_260, r5
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jne mem_clear_loop
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jne mem_clear_loop
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/* -------------- PORT 1: TEST INTERRUPT VECTOR --------------- */
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/* -------------- PORT 1: TEST INTERRUPT VECTOR --------------- */
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mov #DMEM_250, r1 ; Initialize stack
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mov #DMEM_250, r1 ; Initialize stack
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eint ; Enable interrupts
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eint ; Enable interrupts
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mov.b #0x0001, r6
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mov.b #0x0001, r6
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mov.b r6, &P1IE
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mov.b r6, &P1IE
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mov #DMEM_200, r15;
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mov #DMEM_200, r15;
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p1_irq_loop:
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p1_irq_loop:
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mov.b r6, &P1IFG ; Generate soft interrupt
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mov.b r6, &P1IFG ; Generate soft interrupt
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nop
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nop
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nop
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nop
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nop
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nop
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rla r6
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rla r6
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mov.b r6, &P1IE
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mov.b r6, &P1IE
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inc r15
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inc r15
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cmp #DMEM_208, r15
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cmp #DMEM_208, r15
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jne p1_irq_loop
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jne p1_irq_loop
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/* -------------- PORT 2: TEST INTERRUPT VECTOR --------------- */
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/* -------------- PORT 2: TEST INTERRUPT VECTOR --------------- */
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mov #DMEM_250, r1 ; Initialize stack
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mov #DMEM_250, r1 ; Initialize stack
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eint ; Enable interrupts
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eint ; Enable interrupts
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mov.b #0x0001, r6
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mov.b #0x0001, r6
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mov.b r6, &P2IE
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mov.b r6, &P2IE
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mov #DMEM_210, r15;
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mov #DMEM_210, r15;
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p2_irq_loop:
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p2_irq_loop:
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mov.b r6, &P2IFG ; Generate soft interrupt
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mov.b r6, &P2IFG ; Generate soft interrupt
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nop
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nop
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nop
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nop
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nop
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nop
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rla r6
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rla r6
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mov.b r6, &P2IE
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mov.b r6, &P2IE
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inc r15
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inc r15
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cmp #DMEM_218, r15
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cmp #DMEM_218, r15
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jne p2_irq_loop
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jne p2_irq_loop
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/* ---------------------- END OF TEST --------------- */
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/* ---------------------- END OF TEST --------------- */
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end_of_test:
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end_of_test:
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nop
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nop
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br #0xffff
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br #0xffff
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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PORT1_VECTOR:
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PORT1_VECTOR:
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mov.b &P1IFG, 0(r15)
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mov.b &P1IFG, 0(r15)
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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reti
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reti
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PORT2_VECTOR:
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PORT2_VECTOR:
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mov.b &P2IFG, 0(r15)
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mov.b &P2IFG, 0(r15)
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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reti
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reti
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/* ---------------------- INTERRUPT VECTORS --------------- */
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/* ---------------------- INTERRUPT VECTORS --------------- */
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.section .vectors, "a"
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.section .vectors, "a"
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 1
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.word PORT1_VECTOR ; Interrupt 2
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.word PORT1_VECTOR ; Interrupt 2
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.word PORT2_VECTOR ; Interrupt 3
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.word PORT2_VECTOR ; Interrupt 3
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 9
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.word end_of_test ; Interrupt 9
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.word end_of_test ; Interrupt 10 Watchdog timer
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.word end_of_test ; Interrupt 10 Watchdog timer
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 14 NMI
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.word end_of_test ; Interrupt 14 NMI
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.word main ; Interrupt 15 (highest priority) RESET
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.word main ; Interrupt 15 (highest priority) RESET
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