/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* DIGITAL I/O */
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/* DIGITAL I/O */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the Digital I/O interface: */
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/* Test the Digital I/O interface: */
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/* - Read/Write register access. */
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/* - Read/Write register access. */
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/* - I/O Functionality. */
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/* - I/O Functionality. */
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/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 17 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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.global main
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.global main
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.set P1IN, 0x0020
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.set P1IN, 0x0020
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.set P1OUT, 0x0021
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.set P1OUT, 0x0021
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.set P1DIR, 0x0022
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.set P1DIR, 0x0022
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.set P1IFG, 0x0023
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.set P1IFG, 0x0023
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.set P1IES, 0x0024
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.set P1IES, 0x0024
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.set P1IE, 0x0025
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.set P1IE, 0x0025
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.set P1SEL, 0x0026
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.set P1SEL, 0x0026
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.set P2IN, 0x0028
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.set P2IN, 0x0028
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.set P2OUT, 0x0029
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.set P2OUT, 0x0029
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.set P2DIR, 0x002A
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.set P2DIR, 0x002A
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.set P2IFG, 0x002B
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.set P2IFG, 0x002B
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.set P2IES, 0x002C
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.set P2IES, 0x002C
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.set P2IE, 0x002D
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.set P2IE, 0x002D
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.set P2SEL, 0x002E
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.set P2SEL, 0x002E
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.set P3IN, 0x0018
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.set P3IN, 0x0018
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.set P3OUT, 0x0019
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.set P3OUT, 0x0019
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.set P3DIR, 0x001A
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.set P3DIR, 0x001A
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.set P3SEL, 0x001B
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.set P3SEL, 0x001B
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.set P4IN, 0x001C
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.set P4IN, 0x001C
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.set P4OUT, 0x001D
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.set P4OUT, 0x001D
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.set P4DIR, 0x001E
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.set P4DIR, 0x001E
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.set P4SEL, 0x001F
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.set P4SEL, 0x001F
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.set P5IN, 0x0030
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.set P5IN, 0x0030
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.set P5OUT, 0x0031
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.set P5OUT, 0x0031
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.set P5DIR, 0x0032
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.set P5DIR, 0x0032
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.set P5SEL, 0x0033
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.set P5SEL, 0x0033
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.set P6IN, 0x0034
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.set P6IN, 0x0034
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.set P6OUT, 0x0035
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.set P6OUT, 0x0035
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.set P6DIR, 0x0036
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.set P6DIR, 0x0036
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.set P6SEL, 0x0037
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.set P6SEL, 0x0037
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main:
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main:
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/* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */
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/* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */
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mov.b #0xaa, &P1IN ; P1IN
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mov.b #0xaa, &P1IN ; P1IN
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mov.b &P1IN, &0x0200
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mov.b &P1IN, &0x0200
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mov.b #0x55, &P1IN
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mov.b #0x55, &P1IN
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mov.b &P1IN, &0x0201
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mov.b &P1IN, &0x0201
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mov.b #0xaa, &P1OUT ; P1OUT
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mov.b #0xaa, &P1OUT ; P1OUT
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mov.b &P1OUT, &0x0202
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mov.b &P1OUT, &0x0202
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mov.b #0x55, &P1OUT
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mov.b #0x55, &P1OUT
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mov.b &P1OUT, &0x0203
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mov.b &P1OUT, &0x0203
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mov.b #0x5a, &P1DIR ; P1DIR
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mov.b #0x5a, &P1DIR ; P1DIR
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mov.b &P1DIR, &0x0204
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mov.b &P1DIR, &0x0204
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mov.b #0xa5, &P1DIR
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mov.b #0xa5, &P1DIR
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mov.b &P1DIR, &0x0205
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mov.b &P1DIR, &0x0205
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mov.b #0x55, &P1IFG ; P1IFG
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mov.b #0x55, &P1IFG ; P1IFG
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mov.b &P1IFG, &0x0206
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mov.b &P1IFG, &0x0206
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mov.b #0xaa, &P1IFG
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mov.b #0xaa, &P1IFG
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mov.b &P1IFG, &0x0207
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mov.b &P1IFG, &0x0207
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mov.b #0xa5, &P1IES ; P1IES
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mov.b #0xa5, &P1IES ; P1IES
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mov.b &P1IES, &0x0208
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mov.b &P1IES, &0x0208
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mov.b #0x5a, &P1IES
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mov.b #0x5a, &P1IES
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mov.b &P1IES, &0x0209
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mov.b &P1IES, &0x0209
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mov.b #0xaa, &P1IE ; P1IE
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mov.b #0xaa, &P1IE ; P1IE
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mov.b &P1IE, &0x020A
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mov.b &P1IE, &0x020A
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mov.b #0x55, &P1IE
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mov.b #0x55, &P1IE
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mov.b &P1IE, &0x020B
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mov.b &P1IE, &0x020B
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mov.b #0xcd, &P1SEL ; P1SEL
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mov.b #0xcd, &P1SEL ; P1SEL
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mov.b &P1SEL, &0x020C
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mov.b &P1SEL, &0x020C
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mov.b #0x32, &P1SEL
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mov.b #0x32, &P1SEL
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mov.b &P1SEL, &0x020D
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mov.b &P1SEL, &0x020D
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mov.b #0x00, &P1IN ; Re-Initialize
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mov.b #0x00, &P1IN ; Re-Initialize
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mov.b #0x00, &P1OUT
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mov.b #0x00, &P1OUT
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mov.b #0x00, &P1DIR
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mov.b #0x00, &P1DIR
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IES
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mov.b #0x00, &P1IES
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mov.b #0x00, &P1IE
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mov.b #0x00, &P1IE
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mov.b #0x00, &P1SEL
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mov.b #0x00, &P1SEL
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mov #0x0001, r15
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mov #0x0001, r15
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/* -------------- PORT 2: TEST RD/WR REGISTER ACCESS --------------- */
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/* -------------- PORT 2: TEST RD/WR REGISTER ACCESS --------------- */
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mov.b #0xaa, &P2IN ; P2IN
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mov.b #0xaa, &P2IN ; P2IN
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mov.b &P2IN, &0x0210
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mov.b &P2IN, &0x0210
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mov.b #0x55, &P2IN
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mov.b #0x55, &P2IN
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mov.b &P2IN, &0x0211
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mov.b &P2IN, &0x0211
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mov.b #0xaa, &P2OUT ; P2OUT
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mov.b #0xaa, &P2OUT ; P2OUT
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mov.b &P2OUT, &0x0212
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mov.b &P2OUT, &0x0212
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mov.b #0x55, &P2OUT
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mov.b #0x55, &P2OUT
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mov.b &P2OUT, &0x0213
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mov.b &P2OUT, &0x0213
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mov.b #0x5a, &P2DIR ; P2DIR
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mov.b #0x5a, &P2DIR ; P2DIR
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mov.b &P2DIR, &0x0214
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mov.b &P2DIR, &0x0214
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mov.b #0xa5, &P2DIR
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mov.b #0xa5, &P2DIR
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mov.b &P2DIR, &0x0215
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mov.b &P2DIR, &0x0215
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mov.b #0x55, &P2IFG ; P2IFG
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mov.b #0x55, &P2IFG ; P2IFG
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mov.b &P2IFG, &0x0216
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mov.b &P2IFG, &0x0216
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mov.b #0xaa, &P2IFG
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mov.b #0xaa, &P2IFG
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mov.b &P2IFG, &0x0217
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mov.b &P2IFG, &0x0217
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mov.b #0xa5, &P2IES ; P2IES
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mov.b #0xa5, &P2IES ; P2IES
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mov.b &P2IES, &0x0218
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mov.b &P2IES, &0x0218
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mov.b #0x5a, &P2IES
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mov.b #0x5a, &P2IES
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mov.b &P2IES, &0x0219
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mov.b &P2IES, &0x0219
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mov.b #0xaa, &P2IE ; P2IE
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mov.b #0xaa, &P2IE ; P2IE
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mov.b &P2IE, &0x021A
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mov.b &P2IE, &0x021A
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mov.b #0x55, &P2IE
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mov.b #0x55, &P2IE
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mov.b &P2IE, &0x021B
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mov.b &P2IE, &0x021B
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mov.b #0xcd, &P2SEL ; P2SEL
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mov.b #0xcd, &P2SEL ; P2SEL
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mov.b &P2SEL, &0x021C
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mov.b &P2SEL, &0x021C
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mov.b #0x32, &P2SEL
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mov.b #0x32, &P2SEL
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mov.b &P2SEL, &0x021D
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mov.b &P2SEL, &0x021D
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mov.b #0x00, &P2IN ; Re-Initialize
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mov.b #0x00, &P2IN ; Re-Initialize
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mov.b #0x00, &P2OUT
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mov.b #0x00, &P2OUT
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mov.b #0x00, &P2DIR
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mov.b #0x00, &P2DIR
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IES
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mov.b #0x00, &P2IES
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mov.b #0x00, &P2IE
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mov.b #0x00, &P2IE
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mov.b #0x00, &P2SEL
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mov.b #0x00, &P2SEL
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mov #0x0002, r15
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mov #0x0002, r15
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/* -------------- PORT 3: TEST RD/WR REGISTER ACCESS --------------- */
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/* -------------- PORT 3: TEST RD/WR REGISTER ACCESS --------------- */
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mov.b #0xaa, &P3IN ; P3IN
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mov.b #0xaa, &P3IN ; P3IN
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mov.b &P3IN, &0x0220
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mov.b &P3IN, &0x0220
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mov.b #0x55, &P3IN
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mov.b #0x55, &P3IN
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mov.b &P3IN, &0x0221
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mov.b &P3IN, &0x0221
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mov.b #0xaa, &P3OUT ; P3OUT
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mov.b #0xaa, &P3OUT ; P3OUT
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mov.b &P3OUT, &0x0222
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mov.b &P3OUT, &0x0222
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mov.b #0x55, &P3OUT
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mov.b #0x55, &P3OUT
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mov.b &P3OUT, &0x0223
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mov.b &P3OUT, &0x0223
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mov.b #0x5a, &P3DIR ; P3DIR
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mov.b #0x5a, &P3DIR ; P3DIR
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mov.b &P3DIR, &0x0224
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mov.b &P3DIR, &0x0224
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mov.b #0xa5, &P3DIR
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mov.b #0xa5, &P3DIR
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mov.b &P3DIR, &0x0225
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mov.b &P3DIR, &0x0225
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mov.b #0xcd, &P3SEL ; P3SEL
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mov.b #0xcd, &P3SEL ; P3SEL
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mov.b &P3SEL, &0x0226
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mov.b &P3SEL, &0x0226
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mov.b #0x32, &P3SEL
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mov.b #0x32, &P3SEL
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mov.b &P3SEL, &0x0227
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mov.b &P3SEL, &0x0227
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mov.b #0x00, &P3IN ; Re-Initialize
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mov.b #0x00, &P3IN ; Re-Initialize
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mov.b #0x00, &P3OUT
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mov.b #0x00, &P3OUT
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mov.b #0x00, &P3DIR
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mov.b #0x00, &P3DIR
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mov.b #0x00, &P3SEL
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mov.b #0x00, &P3SEL
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mov #0x0003, r15
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mov #0x0003, r15
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/* -------------- PORT 4: TEST RD/WR REGISTER ACCESS --------------- */
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/* -------------- PORT 4: TEST RD/WR REGISTER ACCESS --------------- */
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mov.b #0xaa, &P4IN ; P4IN
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mov.b #0xaa, &P4IN ; P4IN
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mov.b &P4IN, &0x0230
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mov.b &P4IN, &0x0230
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mov.b #0x55, &P4IN
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mov.b #0x55, &P4IN
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mov.b &P4IN, &0x0231
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mov.b &P4IN, &0x0231
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mov.b #0xaa, &P4OUT ; P4OUT
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mov.b #0xaa, &P4OUT ; P4OUT
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mov.b &P4OUT, &0x0232
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mov.b &P4OUT, &0x0232
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mov.b #0x55, &P4OUT
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mov.b #0x55, &P4OUT
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mov.b &P4OUT, &0x0233
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mov.b &P4OUT, &0x0233
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mov.b #0x5a, &P4DIR ; P4DIR
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mov.b #0x5a, &P4DIR ; P4DIR
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mov.b &P4DIR, &0x0234
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mov.b &P4DIR, &0x0234
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mov.b #0xa5, &P4DIR
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mov.b #0xa5, &P4DIR
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mov.b &P4DIR, &0x0235
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mov.b &P4DIR, &0x0235
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mov.b #0xcd, &P4SEL ; P4SEL
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mov.b #0xcd, &P4SEL ; P4SEL
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mov.b &P4SEL, &0x0236
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mov.b &P4SEL, &0x0236
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mov.b #0x32, &P4SEL
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mov.b #0x32, &P4SEL
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mov.b &P4SEL, &0x0237
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mov.b &P4SEL, &0x0237
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mov.b #0x00, &P4IN ; Re-Initialize
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mov.b #0x00, &P4IN ; Re-Initialize
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mov.b #0x00, &P4OUT
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mov.b #0x00, &P4OUT
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mov.b #0x00, &P4DIR
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mov.b #0x00, &P4DIR
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mov.b #0x00, &P4SEL
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mov.b #0x00, &P4SEL
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mov #0x0004, r15
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mov #0x0004, r15
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/* -------------- PORT 5: TEST RD/WR REGISTER ACCESS --------------- */
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/* -------------- PORT 5: TEST RD/WR REGISTER ACCESS --------------- */
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mov.b #0xaa, &P5IN ; P5IN
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mov.b #0xaa, &P5IN ; P5IN
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mov.b &P5IN, &0x0240
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mov.b &P5IN, &0x0240
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mov.b #0x55, &P5IN
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mov.b #0x55, &P5IN
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mov.b &P5IN, &0x0241
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mov.b &P5IN, &0x0241
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mov.b #0xaa, &P5OUT ; P5OUT
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mov.b #0xaa, &P5OUT ; P5OUT
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mov.b &P5OUT, &0x0242
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mov.b &P5OUT, &0x0242
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mov.b #0x55, &P5OUT
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mov.b #0x55, &P5OUT
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mov.b &P5OUT, &0x0243
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mov.b &P5OUT, &0x0243
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mov.b #0x5a, &P5DIR ; P5DIR
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mov.b #0x5a, &P5DIR ; P5DIR
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mov.b &P5DIR, &0x0244
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mov.b &P5DIR, &0x0244
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mov.b #0xa5, &P5DIR
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mov.b #0xa5, &P5DIR
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mov.b &P5DIR, &0x0245
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mov.b &P5DIR, &0x0245
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mov.b #0xcd, &P5SEL ; P5SEL
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mov.b #0xcd, &P5SEL ; P5SEL
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mov.b &P5SEL, &0x0246
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mov.b &P5SEL, &0x0246
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mov.b #0x32, &P5SEL
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mov.b #0x32, &P5SEL
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mov.b &P5SEL, &0x0247
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mov.b &P5SEL, &0x0247
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mov.b #0x00, &P5IN ; Re-Initialize
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mov.b #0x00, &P5IN ; Re-Initialize
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mov.b #0x00, &P5OUT
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mov.b #0x00, &P5OUT
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mov.b #0x00, &P5DIR
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mov.b #0x00, &P5DIR
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mov.b #0x00, &P5SEL
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mov.b #0x00, &P5SEL
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mov #0x0005, r15
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mov #0x0005, r15
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/* -------------- PORT 6: TEST RD/WR REGISTER ACCESS --------------- */
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/* -------------- PORT 6: TEST RD/WR REGISTER ACCESS --------------- */
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mov.b #0xaa, &P6IN ; P6IN
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mov.b #0xaa, &P6IN ; P6IN
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mov.b &P6IN, &0x0250
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mov.b &P6IN, &0x0250
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mov.b #0x55, &P6IN
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mov.b #0x55, &P6IN
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mov.b &P6IN, &0x0251
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mov.b &P6IN, &0x0251
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mov.b #0xaa, &P6OUT ; P6OUT
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mov.b #0xaa, &P6OUT ; P6OUT
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mov.b &P6OUT, &0x0252
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mov.b &P6OUT, &0x0252
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mov.b #0x55, &P6OUT
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mov.b #0x55, &P6OUT
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mov.b &P6OUT, &0x0253
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mov.b &P6OUT, &0x0253
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mov.b #0x5a, &P6DIR ; P6DIR
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mov.b #0x5a, &P6DIR ; P6DIR
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mov.b &P6DIR, &0x0254
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mov.b &P6DIR, &0x0254
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mov.b #0xa5, &P6DIR
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mov.b #0xa5, &P6DIR
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mov.b &P6DIR, &0x0255
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mov.b &P6DIR, &0x0255
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mov.b #0xcd, &P6SEL ; P6SEL
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mov.b #0xcd, &P6SEL ; P6SEL
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mov.b &P6SEL, &0x0256
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mov.b &P6SEL, &0x0256
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mov.b #0x32, &P6SEL
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mov.b #0x32, &P6SEL
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mov.b &P6SEL, &0x0257
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mov.b &P6SEL, &0x0257
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mov.b #0x00, &P6IN ; Re-Initialize
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mov.b #0x00, &P6IN ; Re-Initialize
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mov.b #0x00, &P6OUT
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mov.b #0x00, &P6OUT
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mov.b #0x00, &P6DIR
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mov.b #0x00, &P6DIR
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mov.b #0x00, &P6SEL
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mov.b #0x00, &P6SEL
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mov #0x0006, r15
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mov #0x0006, r15
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|
|
/* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */
|
/* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */
|
|
|
mov #0x0200, r15 ;# Test Input path
|
mov #0x0200, r15 ;# Test Input path
|
p1_din_loop:
|
p1_din_loop:
|
mov.b &P1IN, 0(r15)
|
mov.b &P1IN, 0(r15)
|
inc r15
|
inc r15
|
cmp #0x0208, r15
|
cmp #0x0208, r15
|
jne p1_din_loop
|
jne p1_din_loop
|
|
|
|
|
mov.b #0x01, &P1OUT ; Test Output path
|
mov.b #0x01, &P1OUT ; Test Output path
|
mov #0x1100, r15
|
mov #0x1100, r15
|
p1_dout_loop:
|
p1_dout_loop:
|
rla.b &P1OUT
|
rla.b &P1OUT
|
inc r15
|
inc r15
|
cmp #0x1107, r15
|
cmp #0x1107, r15
|
jne p1_dout_loop
|
jne p1_dout_loop
|
|
|
|
|
mov.b #0x01, &P1DIR ; Test Direction register
|
mov.b #0x01, &P1DIR ; Test Direction register
|
mov #0x1200, r15
|
mov #0x1200, r15
|
p1_dir_loop:
|
p1_dir_loop:
|
rla.b &P1DIR
|
rla.b &P1DIR
|
inc r15
|
inc r15
|
cmp #0x1207, r15
|
cmp #0x1207, r15
|
jne p1_dir_loop
|
jne p1_dir_loop
|
|
|
|
|
mov.b #0x01, &P1SEL ; Test Function Select register
|
mov.b #0x01, &P1SEL ; Test Function Select register
|
mov #0x1300, r15
|
mov #0x1300, r15
|
p1_sel_loop:
|
p1_sel_loop:
|
rla.b &P1SEL
|
rla.b &P1SEL
|
inc r15
|
inc r15
|
cmp #0x1307, r15
|
cmp #0x1307, r15
|
jne p1_sel_loop
|
jne p1_sel_loop
|
|
|
|
|
mov.b #0x00, &P1OUT ; Re-Initialize
|
mov.b #0x00, &P1OUT ; Re-Initialize
|
mov.b #0x00, &P1DIR
|
mov.b #0x00, &P1DIR
|
mov.b #0x00, &P1SEL
|
mov.b #0x00, &P1SEL
|
|
|
|
|
/* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */
|
/* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */
|
|
|
mov #0x0210, r15 ;# Test Input path
|
mov #0x0210, r15 ;# Test Input path
|
p2_din_loop:
|
p2_din_loop:
|
mov.b &P2IN, 0(r15)
|
mov.b &P2IN, 0(r15)
|
inc r15
|
inc r15
|
cmp #0x0218, r15
|
cmp #0x0218, r15
|
jne p2_din_loop
|
jne p2_din_loop
|
|
|
|
|
mov.b #0x01, &P2OUT ; Test Output path
|
mov.b #0x01, &P2OUT ; Test Output path
|
mov #0x2100, r15
|
mov #0x2100, r15
|
p2_dout_loop:
|
p2_dout_loop:
|
rla.b &P2OUT
|
rla.b &P2OUT
|
inc r15
|
inc r15
|
cmp #0x2107, r15
|
cmp #0x2107, r15
|
jne p2_dout_loop
|
jne p2_dout_loop
|
|
|
|
|
mov.b #0x01, &P2DIR ; Test Direction register
|
mov.b #0x01, &P2DIR ; Test Direction register
|
mov #0x2200, r15
|
mov #0x2200, r15
|
p2_dir_loop:
|
p2_dir_loop:
|
rla.b &P2DIR
|
rla.b &P2DIR
|
inc r15
|
inc r15
|
cmp #0x2207, r15
|
cmp #0x2207, r15
|
jne p2_dir_loop
|
jne p2_dir_loop
|
|
|
|
|
mov.b #0x01, &P2SEL ; Test Function Select register
|
mov.b #0x01, &P2SEL ; Test Function Select register
|
mov #0x2300, r15
|
mov #0x2300, r15
|
p2_sel_loop:
|
p2_sel_loop:
|
rla.b &P2SEL
|
rla.b &P2SEL
|
inc r15
|
inc r15
|
cmp #0x2307, r15
|
cmp #0x2307, r15
|
jne p2_sel_loop
|
jne p2_sel_loop
|
|
|
|
|
mov.b #0x00, &P2OUT ; Re-Initialize
|
mov.b #0x00, &P2OUT ; Re-Initialize
|
mov.b #0x00, &P2DIR
|
mov.b #0x00, &P2DIR
|
mov.b #0x00, &P2SEL
|
mov.b #0x00, &P2SEL
|
|
|
|
|
/* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */
|
/* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */
|
|
|
mov #0x0220, r15 ;# Test Input path
|
mov #0x0220, r15 ;# Test Input path
|
p3_din_loop:
|
p3_din_loop:
|
mov.b &P3IN, 0(r15)
|
mov.b &P3IN, 0(r15)
|
inc r15
|
inc r15
|
cmp #0x0228, r15
|
cmp #0x0228, r15
|
jne p3_din_loop
|
jne p3_din_loop
|
|
|
|
|
mov.b #0x01, &P3OUT ; Test Output path
|
mov.b #0x01, &P3OUT ; Test Output path
|
mov #0x3100, r15
|
mov #0x3100, r15
|
p3_dout_loop:
|
p3_dout_loop:
|
rla.b &P3OUT
|
rla.b &P3OUT
|
inc r15
|
inc r15
|
cmp #0x3107, r15
|
cmp #0x3107, r15
|
jne p3_dout_loop
|
jne p3_dout_loop
|
|
|
|
|
mov.b #0x01, &P3DIR ; Test Direction register
|
mov.b #0x01, &P3DIR ; Test Direction register
|
mov #0x3200, r15
|
mov #0x3200, r15
|
p3_dir_loop:
|
p3_dir_loop:
|
rla.b &P3DIR
|
rla.b &P3DIR
|
inc r15
|
inc r15
|
cmp #0x3207, r15
|
cmp #0x3207, r15
|
jne p3_dir_loop
|
jne p3_dir_loop
|
|
|
|
|
mov.b #0x01, &P3SEL ; Test Function Select register
|
mov.b #0x01, &P3SEL ; Test Function Select register
|
mov #0x3300, r15
|
mov #0x3300, r15
|
p3_sel_loop:
|
p3_sel_loop:
|
rla.b &P3SEL
|
rla.b &P3SEL
|
inc r15
|
inc r15
|
cmp #0x3307, r15
|
cmp #0x3307, r15
|
jne p3_sel_loop
|
jne p3_sel_loop
|
|
|
|
|
mov.b #0x00, &P3OUT ; Re-Initialize
|
mov.b #0x00, &P3OUT ; Re-Initialize
|
mov.b #0x00, &P3DIR
|
mov.b #0x00, &P3DIR
|
mov.b #0x00, &P3SEL
|
mov.b #0x00, &P3SEL
|
|
|
|
|
/* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */
|
/* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */
|
|
|
mov #0x0230, r15 ;# Test Input path
|
mov #0x0230, r15 ;# Test Input path
|
p4_din_loop:
|
p4_din_loop:
|
mov.b &P4IN, 0(r15)
|
mov.b &P4IN, 0(r15)
|
inc r15
|
inc r15
|
cmp #0x0238, r15
|
cmp #0x0238, r15
|
jne p4_din_loop
|
jne p4_din_loop
|
|
|
|
|
mov.b #0x01, &P4OUT ; Test Output path
|
mov.b #0x01, &P4OUT ; Test Output path
|
mov #0x4100, r15
|
mov #0x4100, r15
|
p4_dout_loop:
|
p4_dout_loop:
|
rla.b &P4OUT
|
rla.b &P4OUT
|
inc r15
|
inc r15
|
cmp #0x4107, r15
|
cmp #0x4107, r15
|
jne p4_dout_loop
|
jne p4_dout_loop
|
|
|
|
|
mov.b #0x01, &P4DIR ; Test Direction register
|
mov.b #0x01, &P4DIR ; Test Direction register
|
mov #0x4200, r15
|
mov #0x4200, r15
|
p4_dir_loop:
|
p4_dir_loop:
|
rla.b &P4DIR
|
rla.b &P4DIR
|
inc r15
|
inc r15
|
cmp #0x4207, r15
|
cmp #0x4207, r15
|
jne p4_dir_loop
|
jne p4_dir_loop
|
|
|
|
|
mov.b #0x01, &P4SEL ; Test Function Select register
|
mov.b #0x01, &P4SEL ; Test Function Select register
|
mov #0x4300, r15
|
mov #0x4300, r15
|
p4_sel_loop:
|
p4_sel_loop:
|
rla.b &P4SEL
|
rla.b &P4SEL
|
inc r15
|
inc r15
|
cmp #0x4307, r15
|
cmp #0x4307, r15
|
jne p4_sel_loop
|
jne p4_sel_loop
|
|
|
|
|
mov.b #0x00, &P4OUT ; Re-Initialize
|
mov.b #0x00, &P4OUT ; Re-Initialize
|
mov.b #0x00, &P4DIR
|
mov.b #0x00, &P4DIR
|
mov.b #0x00, &P4SEL
|
mov.b #0x00, &P4SEL
|
|
|
|
|
/* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */
|
/* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */
|
|
|
mov #0x0240, r15 ;# Test Input path
|
mov #0x0240, r15 ;# Test Input path
|
p5_din_loop:
|
p5_din_loop:
|
mov.b &P5IN, 0(r15)
|
mov.b &P5IN, 0(r15)
|
inc r15
|
inc r15
|
cmp #0x0248, r15
|
cmp #0x0248, r15
|
jne p5_din_loop
|
jne p5_din_loop
|
|
|
|
|
mov.b #0x01, &P5OUT ; Test Output path
|
mov.b #0x01, &P5OUT ; Test Output path
|
mov #0x5100, r15
|
mov #0x5100, r15
|
p5_dout_loop:
|
p5_dout_loop:
|
rla.b &P5OUT
|
rla.b &P5OUT
|
inc r15
|
inc r15
|
cmp #0x5107, r15
|
cmp #0x5107, r15
|
jne p5_dout_loop
|
jne p5_dout_loop
|
|
|
|
|
mov.b #0x01, &P5DIR ; Test Direction register
|
mov.b #0x01, &P5DIR ; Test Direction register
|
mov #0x5200, r15
|
mov #0x5200, r15
|
p5_dir_loop:
|
p5_dir_loop:
|
rla.b &P5DIR
|
rla.b &P5DIR
|
inc r15
|
inc r15
|
cmp #0x5207, r15
|
cmp #0x5207, r15
|
jne p5_dir_loop
|
jne p5_dir_loop
|
|
|
|
|
mov.b #0x01, &P5SEL ; Test Function Select register
|
mov.b #0x01, &P5SEL ; Test Function Select register
|
mov #0x5300, r15
|
mov #0x5300, r15
|
p5_sel_loop:
|
p5_sel_loop:
|
rla.b &P5SEL
|
rla.b &P5SEL
|
inc r15
|
inc r15
|
cmp #0x5307, r15
|
cmp #0x5307, r15
|
jne p5_sel_loop
|
jne p5_sel_loop
|
|
|
|
|
mov.b #0x00, &P5OUT ; Re-Initialize
|
mov.b #0x00, &P5OUT ; Re-Initialize
|
mov.b #0x00, &P5DIR
|
mov.b #0x00, &P5DIR
|
mov.b #0x00, &P5SEL
|
mov.b #0x00, &P5SEL
|
|
|
|
|
/* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */
|
/* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */
|
|
|
mov #0x0250, r15 ;# Test Input path
|
mov #0x0250, r15 ;# Test Input path
|
p6_din_loop:
|
p6_din_loop:
|
mov.b &P6IN, 0(r15)
|
mov.b &P6IN, 0(r15)
|
inc r15
|
inc r15
|
cmp #0x0258, r15
|
cmp #0x0258, r15
|
jne p6_din_loop
|
jne p6_din_loop
|
|
|
|
|
mov.b #0x01, &P6OUT ; Test Output path
|
mov.b #0x01, &P6OUT ; Test Output path
|
mov #0x6100, r15
|
mov #0x6100, r15
|
p6_dout_loop:
|
p6_dout_loop:
|
rla.b &P6OUT
|
rla.b &P6OUT
|
inc r15
|
inc r15
|
cmp #0x6107, r15
|
cmp #0x6107, r15
|
jne p6_dout_loop
|
jne p6_dout_loop
|
|
|
|
|
mov.b #0x01, &P6DIR ; Test Direction register
|
mov.b #0x01, &P6DIR ; Test Direction register
|
mov #0x6200, r15
|
mov #0x6200, r15
|
p6_dir_loop:
|
p6_dir_loop:
|
rla.b &P6DIR
|
rla.b &P6DIR
|
inc r15
|
inc r15
|
cmp #0x6207, r15
|
cmp #0x6207, r15
|
jne p6_dir_loop
|
jne p6_dir_loop
|
|
|
|
|
mov.b #0x01, &P6SEL ; Test Function Select register
|
mov.b #0x01, &P6SEL ; Test Function Select register
|
mov #0x6300, r15
|
mov #0x6300, r15
|
p6_sel_loop:
|
p6_sel_loop:
|
rla.b &P6SEL
|
rla.b &P6SEL
|
inc r15
|
inc r15
|
cmp #0x6307, r15
|
cmp #0x6307, r15
|
jne p6_sel_loop
|
jne p6_sel_loop
|
|
|
|
|
mov.b #0x00, &P6OUT ; Re-Initialize
|
mov.b #0x00, &P6OUT ; Re-Initialize
|
mov.b #0x00, &P6DIR
|
mov.b #0x00, &P6DIR
|
mov.b #0x00, &P6SEL
|
mov.b #0x00, &P6SEL
|
|
|
|
|
|
|
/* ---------------------- END OF TEST --------------- */
|
/* ---------------------- END OF TEST --------------- */
|
end_of_test:
|
end_of_test:
|
nop
|
nop
|
br #0xffff
|
br #0xffff
|
|
|
|
|
/* ---------------------- INTERRUPT VECTORS --------------- */
|
/* ---------------------- INTERRUPT VECTORS --------------- */
|
|
|
.section .vectors, "a"
|
.section .vectors, "a"
|
.word end_of_test ; Interrupt 0 (lowest priority)
|
.word end_of_test ; Interrupt 0 (lowest priority)
|
.word end_of_test ; Interrupt 1
|
.word end_of_test ; Interrupt 1
|
.word end_of_test ; Interrupt 2
|
.word end_of_test ; Interrupt 2
|
.word end_of_test ; Interrupt 3
|
.word end_of_test ; Interrupt 3
|
.word end_of_test ; Interrupt 4
|
.word end_of_test ; Interrupt 4
|
.word end_of_test ; Interrupt 5
|
.word end_of_test ; Interrupt 5
|
.word end_of_test ; Interrupt 6
|
.word end_of_test ; Interrupt 6
|
.word end_of_test ; Interrupt 7
|
.word end_of_test ; Interrupt 7
|
.word end_of_test ; Interrupt 8
|
.word end_of_test ; Interrupt 8
|
.word end_of_test ; Interrupt 9
|
.word end_of_test ; Interrupt 9
|
.word end_of_test ; Interrupt 10 Watchdog timer
|
.word end_of_test ; Interrupt 10 Watchdog timer
|
.word end_of_test ; Interrupt 11
|
.word end_of_test ; Interrupt 11
|
.word end_of_test ; Interrupt 12
|
.word end_of_test ; Interrupt 12
|
.word end_of_test ; Interrupt 13
|
.word end_of_test ; Interrupt 13
|
.word end_of_test ; Interrupt 14 NMI
|
.word end_of_test ; Interrupt 14 NMI
|
.word main ; Interrupt 15 (highest priority) RESET
|
.word main ; Interrupt 15 (highest priority) RESET
|
|
|
