/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* CPU OPERATING MODES */
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/* CPU OPERATING MODES */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the CPU Operating modes: */
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/* Test the CPU Operating modes: */
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/* - CPUOFF (<=> R2[4]): turn off CPU. */
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/* - CPUOFF (<=> R2[4]): turn off CPU. */
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/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
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/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
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/* - SCG1 (<=> R2[7]): turn off SMCLK. */
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/* - SCG1 (<=> R2[7]): turn off SMCLK. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 111 $ */
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/* $Rev: 141 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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.global main
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.include "pmem_defs.asm"
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.set DMEM_BASE, (__data_start )
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.set DMEM_200, (__data_start+0x00)
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.set DMEM_250, (__data_start+0x50)
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.set P1IN, 0x0020
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.set P1OUT, 0x0021
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.set P1DIR, 0x0022
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.set P1IFG, 0x0023
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.set P1IES, 0x0024
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.set P1IE, 0x0025
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.set P1SEL, 0x0026
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.set P2IN, 0x0028
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.set P2OUT, 0x0029
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.set P2DIR, 0x002A
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.set P2IFG, 0x002B
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.set P2IES, 0x002C
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.set P2IE, 0x002D
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.set P2SEL, 0x002E
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.set BCSCTL1, 0x0057
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.set BCSCTL2, 0x0058
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.global main
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WAIT_FUNC:
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WAIT_FUNC:
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dec r14
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dec r14
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jnz WAIT_FUNC
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jnz WAIT_FUNC
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ret
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ret
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main:
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main:
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; Enable GPIO interrupts on P1[0]
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; Enable GPIO interrupts on P1[0]
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mov.b #0x00, &P1DIR
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mov.b #0x00, &P1DIR
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IES
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mov.b #0x00, &P1IES
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mov.b #0x01, &P1IE
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mov.b #0x01, &P1IE
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; Initialize stack and enable global interrupts
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; Initialize stack and enable global interrupts
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mov #DMEM_250, r1
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mov #DMEM_250, r1
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eint
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eint
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mov #0x1000, r15
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mov #0x1000, r15
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/* -------------- SCG1 (<=> R2[7]): turn off SMCLK --------------- */
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/* -------------- SCG1 (<=> R2[7]): turn off SMCLK --------------- */
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mov.b #0x06, &BCSCTL2 ; # Div /8
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mov.b #0x06, &BCSCTL2 ; # Div /8
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mov #0x0008, r2 ; # SCG1=0 (SMCLK on)
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mov #0x0008, r2 ; # SCG1=0 (SMCLK on)
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mov #0x1001, r15
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mov #0x1001, r15
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0088, r2 ; # SCG1=1 (SMCLK off)
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mov #0x0088, r2 ; # SCG1=1 (SMCLK off)
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mov #0x1002, r15
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mov #0x1002, r15
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x1003, r15 ; # SCG1=1 (SMCLK off) with IRQ
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mov #0x1003, r15 ; # SCG1=1 (SMCLK off) with IRQ
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x1004, r15 ; # SCG1=1 (SMCLK off) return from IRQ
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mov #0x1004, r15 ; # SCG1=1 (SMCLK off) return from IRQ
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0008, r2 ; # SCG1=0 (SMCLK on)
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mov #0x0008, r2 ; # SCG1=0 (SMCLK on)
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mov #0x1005, r15
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mov #0x1005, r15
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x2000, r15
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mov #0x2000, r15
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/* -------------- OSCOFF (<=> R2[5]): turn off LFXT1CLK --------------- */
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/* -------------- OSCOFF (<=> R2[5]): turn off LFXT1CLK --------------- */
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mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
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mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
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mov #0x0008, r2 ; # OSCOFF=0 (LFXT1 on)
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mov #0x0008, r2 ; # OSCOFF=0 (LFXT1 on)
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mov #0x2001, r15
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mov #0x2001, r15
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
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mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
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mov #0x0028, r2 ; # OSCOFF=1 (LFXT1 off)
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mov #0x0028, r2 ; # OSCOFF=1 (LFXT1 off)
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mov #0x2002, r15
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mov #0x2002, r15
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x2003, r15 ; # OSCOFF=1 (LFXT1 off) with IRQ
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mov #0x2003, r15 ; # OSCOFF=1 (LFXT1 off) with IRQ
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x2004, r15 ; # OSCOFF=1 (LFXT1 off) return from IRQ
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mov #0x2004, r15 ; # OSCOFF=1 (LFXT1 off) return from IRQ
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov.b #0x08, &BCSCTL2 ; # Div /1 --> select LFXT1CLK
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mov.b #0x08, &BCSCTL2 ; # Div /1 --> select LFXT1CLK
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mov #0x0028, r2 ; # OSCOFF=1 (LFXT1 off)
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mov #0x0028, r2 ; # OSCOFF=1 (LFXT1 off)
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mov #0x2005, r15
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mov #0x2005, r15
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
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mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
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mov #0x0008, r2 ; # OSCOFF=0 (LFXT1 on)
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mov #0x0008, r2 ; # OSCOFF=0 (LFXT1 on)
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mov #0x2006, r15
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mov #0x2006, r15
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x3000, r15
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mov #0x3000, r15
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/* -------------- CPUOFF (<=> R2[4]): turn off CPU --------------- */
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/* -------------- CPUOFF (<=> R2[4]): turn off CPU --------------- */
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; Enable GPIO interrupts on P2[0]
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; Enable GPIO interrupts on P2[0]
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mov.b #0x00, &P2DIR
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mov.b #0x00, &P2DIR
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IES
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mov.b #0x00, &P2IES
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mov.b #0x01, &P2IE
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mov.b #0x01, &P2IE
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mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
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mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK
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mov #0x3001, r15
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mov #0x3001, r15
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mov #0x0008, r2 ; # CPUOFF=0 (CPU on)
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mov #0x0008, r2 ; # CPUOFF=0 (CPU on)
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x3002, r15
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mov #0x3002, r15
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mov #0x0018, r2 ; # CPUOFF=1 (CPU off)
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mov #0x0018, r2 ; # CPUOFF=1 (CPU off)
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x3003, r15
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mov #0x3003, r15
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mov #0x0008, r2 ; # CPUOFF=0 (CPU on)
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mov #0x0008, r2 ; # CPUOFF=0 (CPU on)
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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/* ---------------------- END OF TEST --------------- */
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/* ---------------------- END OF TEST --------------- */
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end_of_test:
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end_of_test:
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nop
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nop
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br #0xffff
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br #0xffff
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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PORT1_VECTOR:
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PORT1_VECTOR:
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push r14
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push r14
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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pop r14
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pop r14
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mov.b #0x00, &P1IFG
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mov.b #0x00, &P1IFG
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reti
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reti
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PORT2_VECTOR:
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PORT2_VECTOR:
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push r14
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push r14
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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pop r14
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pop r14
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mov.b #0x00, &P2IFG
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mov.b #0x00, &P2IFG
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bic #0x10, 0(r1) ;exit lowpower mode
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bic #0x10, 0(r1) ;exit lowpower mode
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reti
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reti
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/* ---------------------- INTERRUPT VECTORS --------------- */
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/* ---------------------- INTERRUPT VECTORS --------------- */
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.section .vectors, "a"
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.section .vectors, "a"
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 1
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.word PORT1_VECTOR ; Interrupt 2
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.word PORT1_VECTOR ; Interrupt 2
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.word PORT2_VECTOR ; Interrupt 3
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.word PORT2_VECTOR ; Interrupt 3
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 9
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.word end_of_test ; Interrupt 9
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.word end_of_test ; Interrupt 10 Watchdog timer
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.word end_of_test ; Interrupt 10 Watchdog timer
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 14 NMI
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.word end_of_test ; Interrupt 14 NMI
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.word main ; Interrupt 15 (highest priority) RESET
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.word main ; Interrupt 15 (highest priority) RESET
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