/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* TIMER A */
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/* TIMER A */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the timer A: */
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/* Test the timer A: */
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/* - Check RD/WR register access. */
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/* - Check RD/WR register access. */
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/* - Check the clock divider. */
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/* - Check the clock divider. */
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/* - Check the timer modes. */
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/* - Check the timer modes. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 111 $ */
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/* $Rev: 141 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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.global main
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.include "pmem_defs.asm"
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.set DMEM_BASE, (__data_start )
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.set DMEM_200, (__data_start+0x00)
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.set DMEM_202, (__data_start+0x02)
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.set DMEM_204, (__data_start+0x04)
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.set DMEM_206, (__data_start+0x06)
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.set DMEM_208, (__data_start+0x08)
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.set DMEM_20A, (__data_start+0x0A)
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.set DMEM_20C, (__data_start+0x0C)
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.set DMEM_20E, (__data_start+0x0E)
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.set DMEM_210, (__data_start+0x10)
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.set DMEM_212, (__data_start+0x12)
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.set DMEM_214, (__data_start+0x14)
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.set DMEM_216, (__data_start+0x16)
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.set DMEM_218, (__data_start+0x18)
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.set DMEM_21A, (__data_start+0x1A)
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.set DMEM_21E, (__data_start+0x1E)
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.set DMEM_220, (__data_start+0x20)
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.set DMEM_222, (__data_start+0x22)
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.set DMEM_224, (__data_start+0x24)
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.set DMEM_226, (__data_start+0x26)
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.set DMEM_228, (__data_start+0x28)
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.set DMEM_22A, (__data_start+0x2A)
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.set DMEM_230, (__data_start+0x30)
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.set DMEM_232, (__data_start+0x32)
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.set DMEM_234, (__data_start+0x34)
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.set DMEM_236, (__data_start+0x36)
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.set DMEM_238, (__data_start+0x38)
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.set DMEM_23A, (__data_start+0x3A)
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.set DMEM_240, (__data_start+0x40)
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.set DMEM_242, (__data_start+0x42)
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.set DMEM_244, (__data_start+0x44)
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.set DMEM_246, (__data_start+0x46)
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.set DMEM_248, (__data_start+0x48)
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.set DMEM_24A, (__data_start+0x4A)
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.set DMEM_250, (__data_start+0x50)
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.set DMEM_254, (__data_start+0x54)
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.set DMEM_256, (__data_start+0x56)
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.set DMEM_262, (__data_start+0x62)
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.set DMEM_296, (__data_start+0x96)
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.set DMEM_2D6, (__data_start+0xD6)
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.set TACTL, 0x0160
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.set TAR, 0x0170
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.set TACCTL0, 0x0162
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.set TACCR0, 0x0172
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.set TACCTL1, 0x0164
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.set TACCR1, 0x0174
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.set TACCTL2, 0x0166
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.set TACCR2, 0x0176
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.set TAIV, 0x012E
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.global main
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WAIT_FUNC:
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WAIT_FUNC:
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dec r14
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dec r14
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jnz WAIT_FUNC
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jnz WAIT_FUNC
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ret
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ret
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main:
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main:
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mov #DMEM_250, r1 ; # Initialize stack pointer
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mov #DMEM_250, r1 ; # Initialize stack pointer
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mov #0x0000, &DMEM_200
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mov #0x0000, &DMEM_200
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/* -------------- TIMER A TEST: RD/WR ACCESS --------------- */
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/* -------------- TIMER A TEST: RD/WR ACCESS --------------- */
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mov #0xaaaa, &TACTL ; # TACTL
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mov #0xaaaa, &TACTL ; # TACTL
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mov &TACTL, &DMEM_200
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mov &TACTL, &DMEM_200
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mov #0x5555, &TACTL
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mov #0x5555, &TACTL
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mov &TACTL, &DMEM_202
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mov &TACTL, &DMEM_202
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mov #0x0000, &TACTL
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mov #0x0000, &TACTL
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mov &TACTL, &DMEM_204
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mov &TACTL, &DMEM_204
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mov #0x0000, &TACTL
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mov #0x0000, &TACTL
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mov &TACTL, &DMEM_206
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mov &TACTL, &DMEM_206
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mov #0xaaaa, &TAR ; # TAR
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mov #0xaaaa, &TAR ; # TAR
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mov &TAR, &DMEM_208
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mov &TAR, &DMEM_208
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mov #0x5555, &TAR
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mov #0x5555, &TAR
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mov &TAR, &DMEM_20A
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mov &TAR, &DMEM_20A
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mov #0x0000, &TAR
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mov #0x0000, &TAR
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mov &TAR, &DMEM_20C
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mov &TAR, &DMEM_20C
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mov #0xaaaa, &TACCTL0 ; # TACCTL0
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mov #0xaaaa, &TACCTL0 ; # TACCTL0
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mov &TACCTL0, &DMEM_210
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mov &TACCTL0, &DMEM_210
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mov #0x5555, &TACCTL0
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mov #0x5555, &TACCTL0
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mov &TACCTL0, &DMEM_212
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mov &TACCTL0, &DMEM_212
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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mov &TACCTL0, &DMEM_214
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mov &TACCTL0, &DMEM_214
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mov #0xaaaa, &TACCR0 ; # TACCR0
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mov #0xaaaa, &TACCR0 ; # TACCR0
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mov &TACCR0, &DMEM_216
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mov &TACCR0, &DMEM_216
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mov #0x5555, &TACCR0
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mov #0x5555, &TACCR0
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mov &TACCR0, &DMEM_218
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mov &TACCR0, &DMEM_218
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mov #0x0000, &TACCR0
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mov #0x0000, &TACCR0
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mov &TACCR0, &DMEM_21A
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mov &TACCR0, &DMEM_21A
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mov #0xaaaa, &TACCTL1 ; # TACCTL1
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mov #0xaaaa, &TACCTL1 ; # TACCTL1
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mov &TACCTL1, &DMEM_220
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mov &TACCTL1, &DMEM_220
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mov #0x5555, &TACCTL1
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mov #0x5555, &TACCTL1
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mov &TACCTL1, &DMEM_222
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mov &TACCTL1, &DMEM_222
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mov #0x0000, &TACCTL1
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mov #0x0000, &TACCTL1
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mov &TACCTL1, &DMEM_224
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mov &TACCTL1, &DMEM_224
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mov #0xaaaa, &TACCR1 ; # TACCR1
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mov #0xaaaa, &TACCR1 ; # TACCR1
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mov &TACCR1, &DMEM_226
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mov &TACCR1, &DMEM_226
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mov #0x5555, &TACCR1
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mov #0x5555, &TACCR1
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mov &TACCR1, &DMEM_228
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mov &TACCR1, &DMEM_228
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mov #0x0000, &TACCR1
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mov #0x0000, &TACCR1
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mov &TACCR1, &DMEM_22A
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mov &TACCR1, &DMEM_22A
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mov #0xaaaa, &TACCTL2 ; # TACCTL2
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mov #0xaaaa, &TACCTL2 ; # TACCTL2
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mov &TACCTL2, &DMEM_230
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mov &TACCTL2, &DMEM_230
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mov #0x5555, &TACCTL2
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mov #0x5555, &TACCTL2
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mov &TACCTL2, &DMEM_232
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mov &TACCTL2, &DMEM_232
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mov #0x0000, &TACCTL2
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mov #0x0000, &TACCTL2
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mov &TACCTL2, &DMEM_234
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mov &TACCTL2, &DMEM_234
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mov #0xaaaa, &TACCR2 ; # TACCR2
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mov #0xaaaa, &TACCR2 ; # TACCR2
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mov &TACCR2, &DMEM_236
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mov &TACCR2, &DMEM_236
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mov #0x5555, &TACCR2
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mov #0x5555, &TACCR2
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mov &TACCR2, &DMEM_238
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mov &TACCR2, &DMEM_238
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mov #0x0000, &TACCR2
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mov #0x0000, &TACCR2
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mov &TACCR2, &DMEM_23A
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mov &TACCR2, &DMEM_23A
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mov #0xaaaa, &TAIV ; # TAIV
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mov #0xaaaa, &TAIV ; # TAIV
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mov &TAIV, &DMEM_240
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mov &TAIV, &DMEM_240
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mov #0x5555, &TAIV
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mov #0x5555, &TAIV
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mov &TAIV, &DMEM_242
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mov &TAIV, &DMEM_242
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mov #0x0000, &TAIV
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mov #0x0000, &TAIV
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mov &TAIV, &DMEM_244
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mov &TAIV, &DMEM_244
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mov #0x1000, r15
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mov #0x1000, r15
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/* -------------- TIMER A TEST: INPUT DIVIDER --------------- */
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/* -------------- TIMER A TEST: INPUT DIVIDER --------------- */
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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eint
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eint
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0020, &TACCR0
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mov #0x0020, &TACCR0
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mov #0x0216, &TACTL ; # /1
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mov #0x0216, &TACTL ; # /1
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mov #0x0001, &DMEM_200
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mov #0x0001, &DMEM_200
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mov #0x0010, r14
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mov #0x0010, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0010, &TACCR0
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mov #0x0010, &TACCR0
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mov #0x0256, &TACTL ; # /2
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mov #0x0256, &TACTL ; # /2
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mov #0x0002, &DMEM_200
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mov #0x0002, &DMEM_200
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mov #0x0010, r14
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mov #0x0010, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0008, &TACCR0
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mov #0x0008, &TACCR0
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mov #0x0296, &TACTL ; # /4
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mov #0x0296, &TACTL ; # /4
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mov #0x0003, &DMEM_200
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mov #0x0003, &DMEM_200
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mov #0x0010, r14
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mov #0x0010, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0004, &TACCR0
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mov #0x0004, &TACCR0
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mov #0x02D6, &TACTL ; # /8
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mov #0x02D6, &TACTL ; # /8
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mov #0x0004, &DMEM_200
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mov #0x0004, &DMEM_200
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mov #0x0010, r14
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mov #0x0010, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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dint
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dint
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mov #0x0000, &DMEM_200
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mov #0x0000, &DMEM_200
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mov #0x2000, r15
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mov #0x2000, r15
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/* -------------- TIMER A TEST: UP MODE ----------------- */
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/* -------------- TIMER A TEST: UP MODE ----------------- */
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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eint
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eint
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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mov #0x0012, &TACCR0 ; # Check timing for period = 0x12 +1
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mov #0x0012, &TACCR0 ; # Check timing for period = 0x12 +1
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mov #0x0256, &TACTL
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mov #0x0256, &TACTL
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mov #0x0001, &DMEM_200
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mov #0x0001, &DMEM_200
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mov #0x0010, r14
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mov #0x0010, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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mov #0x001E, &TACCR0 ; # Check timing for period = 0x1E +1
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mov #0x001E, &TACCR0 ; # Check timing for period = 0x1E +1
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mov #0x0256, &TACTL
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mov #0x0256, &TACTL
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mov #0x0002, &DMEM_200
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mov #0x0002, &DMEM_200
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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mov #0x0012, &TACCR0 ; # Check timing for period = 0x12 +1
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mov #0x0012, &TACCR0 ; # Check timing for period = 0x12 +1
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mov #0x0254, &TACTL
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mov #0x0254, &TACTL
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mov #0x0010, &TACCTL0
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mov #0x0010, &TACCTL0
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mov #0x0003, &DMEM_200
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mov #0x0003, &DMEM_200
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mov #0x0010, r14
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mov #0x0010, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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mov #0x001E, &TACCR0 ; # Check timing for period = 0x1E +1
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mov #0x001E, &TACCR0 ; # Check timing for period = 0x1E +1
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mov #0x0254, &TACTL
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mov #0x0254, &TACTL
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mov #0x0010, &TACCTL0
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mov #0x0010, &TACCTL0
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mov #0x0004, &DMEM_200
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mov #0x0004, &DMEM_200
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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dint
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dint
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mov #0x0000, &DMEM_200
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mov #0x0000, &DMEM_200
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mov #0x3000, r15
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mov #0x3000, r15
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/* -------------- TIMER A TEST: CONTINUOUS MODES ----------------- */
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/* -------------- TIMER A TEST: CONTINUOUS MODES ----------------- */
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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eint
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eint
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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mov #0xfff0, &TAR ; # Continuous mode
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mov #0xfff0, &TAR ; # Continuous mode
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mov #0x0262, &TACTL
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mov #0x0262, &TACTL
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mov #0x0001, &DMEM_200
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mov #0x0001, &DMEM_200
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mov #0x0020, r14
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mov #0x0020, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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dint
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dint
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mov #0x0000, &DMEM_200
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mov #0x0000, &DMEM_200
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mov #0x4000, r15
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mov #0x4000, r15
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/* -------------- TIMER A TEST: UP-DOWN MODE ----------------- */
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/* -------------- TIMER A TEST: UP-DOWN MODE ----------------- */
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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eint
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eint
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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mov #0x0031, &TACCR0 ; # Up-Down mode - timing 1
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mov #0x0031, &TACCR0 ; # Up-Down mode - timing 1
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mov #0x0000, &TAR
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mov #0x0000, &TAR
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mov #0x0236, &TACTL
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mov #0x0236, &TACTL
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mov #0x0010, &TACCTL0
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mov #0x0010, &TACCTL0
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mov #0x0001, &DMEM_200
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mov #0x0001, &DMEM_200
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mov #0x0050, r14
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mov #0x0050, r14
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call #WAIT_FUNC
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call #WAIT_FUNC
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mov #0x0002, &DMEM_200
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mov #0x0002, &DMEM_200
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dint
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dint
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mov #0x0200, &TACTL
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mov #0x0200, &TACTL
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mov #0x0000, &TACCTL0
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mov #0x0000, &TACCTL0
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mov #0x0000, &DMEM_200
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mov #0x0000, &DMEM_200
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mov #0x5000, r15
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mov #0x5000, r15
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/* ---------------------- END OF TEST --------------- */
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/* ---------------------- END OF TEST --------------- */
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end_of_test:
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end_of_test:
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nop
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nop
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br #0xffff
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br #0xffff
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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TIMERA_CCR0_VECTOR:
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TIMERA_CCR0_VECTOR:
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mov &TAR, &DMEM_204
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mov &TAR, &DMEM_204
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reti
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reti
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TIMERA_TAIV_VECTOR:
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TIMERA_TAIV_VECTOR:
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mov &TAR, &DMEM_202
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mov &TAR, &DMEM_202
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bic #0x0001, &TACTL
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bic #0x0001, &TACTL
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reti
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reti
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/* ---------------------- INTERRUPT VECTORS --------------- */
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/* ---------------------- INTERRUPT VECTORS --------------- */
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.section .vectors, "a"
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.section .vectors, "a"
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 2
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.word end_of_test ; Interrupt 2
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.word end_of_test ; Interrupt 3
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.word end_of_test ; Interrupt 3
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 6
|
.word end_of_test ; Interrupt 6
|
.word end_of_test ; Interrupt 7
|
.word end_of_test ; Interrupt 7
|
.word TIMERA_TAIV_VECTOR ; Interrupt 8
|
.word TIMERA_TAIV_VECTOR ; Interrupt 8
|
.word TIMERA_CCR0_VECTOR ; Interrupt 9
|
.word TIMERA_CCR0_VECTOR ; Interrupt 9
|
.word end_of_test ; Interrupt 10 Watchdog timer
|
.word end_of_test ; Interrupt 10 Watchdog timer
|
.word end_of_test ; Interrupt 11
|
.word end_of_test ; Interrupt 11
|
.word end_of_test ; Interrupt 12
|
.word end_of_test ; Interrupt 12
|
.word end_of_test ; Interrupt 13
|
.word end_of_test ; Interrupt 13
|
.word end_of_test ; Interrupt 14 NMI
|
.word end_of_test ; Interrupt 14 NMI
|
.word main ; Interrupt 15 (highest priority) RESET
|
.word main ; Interrupt 15 (highest priority) RESET
|
|
|
