/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* TIMER A */
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/* TIMER A */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the timer A: */
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/* Test the timer A: */
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/* - Check RD/WR register access. */
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/* - Check RD/WR register access. */
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/* - Check the clock divider. */
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/* - Check the clock divider. */
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/* - Check the timer modes. */
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/* - Check the timer modes. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 180 $ */
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/* $Rev: 202 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $ */
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/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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integer test_step;
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integer test_step;
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integer my_counter;
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integer my_counter;
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always @ (posedge mclk)
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always @ (posedge mclk)
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my_counter <= my_counter+1;
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my_counter <= my_counter+1;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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repeat(5) @(posedge mclk);
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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test_step = 0;
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test_step = 0;
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`ifdef ASIC_CLOCKING
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`ifdef ASIC_CLOCKING
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$display(" ===============================================");
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tb_skip_finish("| (this test is not supported in ASIC mode) |");
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$display("| SIMULATION SKIPPED |");
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$display("| (this test is not supported in ASIC mode) |");
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$display(" ===============================================");
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$finish;
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`else
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`else
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// TIMER A TEST: RD/WR ACCESS
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// TIMER A TEST: RD/WR ACCESS
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(r15===16'h1000);
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@(r15===16'h1000);
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if (mem200 !== 16'h02a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
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if (mem200 !== 16'h02a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
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if (mem202 !== 16'h0151) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
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if (mem202 !== 16'h0151) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
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if (mem204 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
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if (mem204 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
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if (mem206 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
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if (mem206 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
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if (mem208 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
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if (mem208 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
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if (mem20A !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
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if (mem20A !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
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if (mem20C !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
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if (mem20C !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
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if (mem210 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
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if (mem210 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
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if (mem212 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
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if (mem212 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
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if (mem214 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
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if (mem214 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
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if (mem216 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
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if (mem216 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
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if (mem218 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
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if (mem218 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
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if (mem21A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
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if (mem21A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
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if (mem220 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
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if (mem220 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
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if (mem222 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
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if (mem222 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
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if (mem224 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
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if (mem224 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
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if (mem226 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
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if (mem226 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
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if (mem228 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
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if (mem228 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
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if (mem22A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
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if (mem22A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
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if (mem230 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
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if (mem230 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
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if (mem232 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
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if (mem232 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
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if (mem234 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
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if (mem234 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
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if (mem236 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
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if (mem236 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
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if (mem238 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
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if (mem238 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
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if (mem23A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
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if (mem23A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
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if (mem240 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
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if (mem240 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
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if (mem242 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
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if (mem242 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
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if (mem244 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
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if (mem244 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
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test_step = 1;
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test_step = 1;
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// TIMER A TEST: INPUT DIVIDER
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// TIMER A TEST: INPUT DIVIDER
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(mem200 === 16'h0001); // Check /1 divider
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@(mem200 === 16'h0001); // Check /1 divider
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h21) tb_error("====== TIMER_A INPUT DIVIDER: /1 ERROR =====");
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if (my_counter !== 32'h21) tb_error("====== TIMER_A INPUT DIVIDER: /1 ERROR =====");
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test_step = 2;
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test_step = 2;
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@(mem200 === 16'h0002); // Check /2 divider
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@(mem200 === 16'h0002); // Check /2 divider
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h22) tb_error("====== TIMER_A INPUT DIVIDER: /2 ERROR =====");
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if (my_counter !== 32'h22) tb_error("====== TIMER_A INPUT DIVIDER: /2 ERROR =====");
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test_step = 3;
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test_step = 3;
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@(mem200 === 16'h0003); // Check /4 divider
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@(mem200 === 16'h0003); // Check /4 divider
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h24) tb_error("====== TIMER_A INPUT DIVIDER: /4 ERROR =====");
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if (my_counter !== 32'h24) tb_error("====== TIMER_A INPUT DIVIDER: /4 ERROR =====");
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test_step = 4;
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test_step = 4;
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@(mem200 === 16'h0004); // Check /8 divider
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@(mem200 === 16'h0004); // Check /8 divider
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h28) tb_error("====== TIMER_A INPUT DIVIDER: /8 ERROR =====");
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if (my_counter !== 32'h28) tb_error("====== TIMER_A INPUT DIVIDER: /8 ERROR =====");
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test_step = 5;
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test_step = 5;
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@(r15===16'h2000);
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@(r15===16'h2000);
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test_step = 6;
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test_step = 6;
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// TIMER A TEST: UP MODE
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// TIMER A TEST: UP MODE
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
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@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TAIFG interrupt =====");
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if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TAIFG interrupt =====");
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test_step = 7;
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test_step = 7;
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@(mem200 === 16'h0002); // Check timing 2 - TAIFG interrupt
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@(mem200 === 16'h0002); // Check timing 2 - TAIFG interrupt
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TAIFG interrupt =====");
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if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TAIFG interrupt =====");
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test_step = 8;
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test_step = 8;
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@(mem200 === 16'h0003); // Check timing 1 - TACCR0 interrupt
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@(mem200 === 16'h0003); // Check timing 1 - TACCR0 interrupt
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@(posedge irq_ta0)
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@(posedge irq_ta0)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta0)
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@(posedge irq_ta0)
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if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TACCR0 interrupt =====");
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if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TACCR0 interrupt =====");
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test_step = 8;
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test_step = 8;
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@(mem200 === 16'h0004); // Check timing 2 - TACCR0 interrupt
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@(mem200 === 16'h0004); // Check timing 2 - TACCR0 interrupt
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@(posedge irq_ta0)
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@(posedge irq_ta0)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta0)
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@(posedge irq_ta0)
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if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TACCR0 interrupt =====");
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if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TACCR0 interrupt =====");
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test_step = 9;
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test_step = 9;
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@(r15===16'h3000);
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@(r15===16'h3000);
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if (mem202 !== 16'h0004) tb_error("====== TIMER_A UP MODE: TAIFG LATENCY ERROR =====");
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if (mem202 !== 16'h0004) tb_error("====== TIMER_A UP MODE: TAIFG LATENCY ERROR =====");
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if (mem204 !== 16'h0003) tb_error("====== TIMER_A UP MODE: TACCR0 LATENCY ERROR =====");
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if (mem204 !== 16'h0003) tb_error("====== TIMER_A UP MODE: TACCR0 LATENCY ERROR =====");
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test_step = 10;
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test_step = 10;
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// TIMER A TEST: CONTINUOUS MODE
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// TIMER A TEST: CONTINUOUS MODE
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
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@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h1C) tb_error("====== TIMER_A CONTINUOUS MODE: TIMING 1 - TAIFG interrupt =====");
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if (my_counter !== 32'h1C) tb_error("====== TIMER_A CONTINUOUS MODE: TIMING 1 - TAIFG interrupt =====");
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test_step = 11;
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test_step = 11;
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// TIMER A TEST: UP-DOWN MODE
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// TIMER A TEST: UP-DOWN MODE
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
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@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
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@(posedge irq_ta0)
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@(posedge irq_ta0)
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta0)
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@(posedge irq_ta0)
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if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG interrupt =====");
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if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG interrupt =====");
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test_step = 12;
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test_step = 12;
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@(posedge irq_ta1) // Check timing 1 - TACCR0 interrupt
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@(posedge irq_ta1) // Check timing 1 - TACCR0 interrupt
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TACCR0 interrupt =====");
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if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TACCR0 interrupt =====");
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test_step = 13;
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test_step = 13;
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@(posedge irq_ta0) // Check timing 1 - TAIFG->TACCR0 interrupt
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@(posedge irq_ta0) // Check timing 1 - TAIFG->TACCR0 interrupt
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@(negedge mclk)
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@(negedge mclk)
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my_counter = 0;
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my_counter = 0;
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@(posedge irq_ta1)
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@(posedge irq_ta1)
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if (my_counter !== 32'h31) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG->TACCR0 interrupt =====");
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if (my_counter !== 32'h31) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG->TACCR0 interrupt =====");
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test_step = 14;
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test_step = 14;
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@(mem200===16'h0002);
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@(mem200===16'h0002);
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if (mem202 !== 16'h0008) tb_error("====== TIMER_A UP-DOWN MODE: TAIFG LATENCY ERROR =====");
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if (mem202 !== 16'h0008) tb_error("====== TIMER_A UP-DOWN MODE: TAIFG LATENCY ERROR =====");
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if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
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if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
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test_step = 15;
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test_step = 15;
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`endif
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`endif
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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No newline at end of file
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No newline at end of file
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