/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* WATCHDOG TIMER */
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/* WATCHDOG TIMER */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the Watdog timer: */
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/* Test the Watdog timer: */
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/* - Interval timer mode. */
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/* - Interval timer mode. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 111 $ */
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/* $Rev: 134 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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.global main
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.global main
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.set DMEM_BASE, (__data_start )
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.set DMEM_BASE, (__data_start )
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.set DMEM_200, (__data_start+0x00)
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.set DMEM_200, (__data_start+0x00)
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.set DMEM_250, (__data_start+0x50)
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.set DMEM_250, (__data_start+0x50)
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.set IE1, 0x0000
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.set IE1, 0x0000
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.set IFG1, 0x0002
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.set IFG1, 0x0002
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.set WDTCTL, 0x0120
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.set WDTCTL, 0x0120
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main:
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main:
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/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */
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/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */
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mov &WDTCTL, r4
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mov &WDTCTL, r4
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mov #0x5aff, &WDTCTL
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mov #0x5aff, &WDTCTL
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mov &WDTCTL, r5
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mov &WDTCTL, r5
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mov #0x5a55, &WDTCTL
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mov #0x5a55, &WDTCTL
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mov &WDTCTL, r6
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mov &WDTCTL, r6
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mov #0x5aaa, &WDTCTL
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mov #0x5aaa, &WDTCTL
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mov &WDTCTL, r7
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mov &WDTCTL, r7
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mov #0x5a00, &WDTCTL
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mov #0x5a00, &WDTCTL
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mov &WDTCTL, r8
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mov &WDTCTL, r8
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mov &IFG1, r9
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mov.b #0x00, &IFG1
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mov #0x1000, r15
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mov #0x1000, r15
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/* -------------- WATCHDOG TEST: INTERVAL MODE /64 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /64 ------------ */
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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eint
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eint
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bis.b #0x01, &IE1
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bis.b #0x01, &IE1
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mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
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mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
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mov #0x0000, r4
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mov #0x0000, r4
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mov #0x0001, r5
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mov #0x0001, r5
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wait_loop_64:
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wait_loop_64:
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inc r4
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inc r4
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cmp #0x3401, r5
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cmp #0x3401, r5
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jne wait_loop_64
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jne wait_loop_64
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mov #0x2000, r15
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mov #0x2000, r15
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bic.b #0x01, &IE1 ;# Disable watchdog interrupt
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bic.b #0x01, &IE1 ;# Disable watchdog interrupt
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mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
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mov #0x0205, r4
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mov &WDTCTL, r5 ;# Check if ACLK is selected
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bit #0x0004, r5
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jnz aclk_sel_64
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mov #0x0012, r4
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aclk_sel_64:
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mov #0x0010, r4
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mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
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mov #0x0002, r5
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mov #0x0002, r5
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wait_loop_64_no_irq:
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wait_loop_64_no_irq:
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dec r4
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dec r4
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cmp #0x0000, r4
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cmp #0x0000, r4
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jne wait_loop_64_no_irq
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jne wait_loop_64_no_irq
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mov &IFG1, r6
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mov &IFG1, r6
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mov r4, r7
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mov r4, r7
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bic.b #0x01, &IFG1 ;# Clear flag
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bic.b #0x01, &IFG1 ;# Clear flag
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mov &IFG1, r8
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mov &IFG1, r8
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mov #0x2001, r15
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mov #0x2001, r15
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mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold
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mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold
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mov #0x0020, r4
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mov #0x0020, r4
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mov #0x0022, r5
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mov #0x0022, r5
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wait_loop_64_no_irq_hold:
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wait_loop_64_no_irq_hold:
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dec r4
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dec r4
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cmp #0x0000, r4
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cmp #0x0000, r4
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jne wait_loop_64_no_irq_hold
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jne wait_loop_64_no_irq_hold
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mov &IFG1, r6
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mov &IFG1, r6
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mov r4, r7
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mov r4, r7
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mov #0x2002, r15
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mov #0x2002, r15
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mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter / Check counter clear
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mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter / Check counter clear
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mov #0x0033, r4
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mov #0x0033, r4
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mov #0x000C, r5
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mov #0x000C, r5
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wait_loop_64_no_irq_clear1:
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wait_loop_64_no_irq_clear1:
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dec r5
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dec r5
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cmp #0x0000, r5
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cmp #0x0000, r5
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jne wait_loop_64_no_irq_clear1
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jne wait_loop_64_no_irq_clear1
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mov #0x5a1b, &WDTCTL ;# Clear counter
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mov #0x5a1b, &WDTCTL ;# Clear counter
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mov &IFG1, r6
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mov &IFG1, r6
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mov #0x000C, r5
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mov #0x000C, r5
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wait_loop_64_no_irq_clear2:
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wait_loop_64_no_irq_clear2:
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dec r5
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dec r5
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cmp #0x0000, r5
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cmp #0x0000, r5
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jne wait_loop_64_no_irq_clear2
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jne wait_loop_64_no_irq_clear2
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mov &IFG1, r7 ;# Don't Clear counter
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mov &IFG1, r7 ;# Don't Clear counter
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mov #0x000C, r5
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mov #0x000C, r5
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wait_loop_64_no_irq_clear3:
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wait_loop_64_no_irq_clear3:
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dec r5
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dec r5
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cmp #0x0000, r5
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cmp #0x0000, r5
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jne wait_loop_64_no_irq_clear3
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jne wait_loop_64_no_irq_clear3
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mov &IFG1, r8
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mov &IFG1, r8
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bic.b #0x01, &IFG1 ;# Clear flag
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bic.b #0x01, &IFG1 ;# Clear flag
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mov #0x2003, r15
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mov #0x2003, r15
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/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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eint
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eint
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bis.b #0x01, &IE1
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bis.b #0x01, &IE1
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mov #0x5a1a, &WDTCTL ;# Enable interval mode /512 & clear counter
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mov #0x5a1a, &WDTCTL ;# Enable interval mode /512 & clear counter
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mov #0x0000, r4
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mov #0x0000, r4
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mov #0x0003, r5
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mov #0x0003, r5
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wait_loop_512:
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wait_loop_512:
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inc r4
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inc r4
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cmp #0x3403, r5
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cmp #0x3403, r5
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jne wait_loop_512
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jne wait_loop_512
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mov #0x3000, r15
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mov #0x3000, r15
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/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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eint
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eint
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bis.b #0x01, &IE1
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bis.b #0x01, &IE1
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mov #0x5a19, &WDTCTL ;# Enable interval mode /8192 & clear counter
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mov #0x5a19, &WDTCTL ;# Enable interval mode /8192 & clear counter
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mov #0x0000, r4
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mov #0x0000, r4
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mov #0x0004, r5
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mov #0x0004, r5
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wait_loop_8192:
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wait_loop_8192:
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inc r4
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inc r4
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cmp #0x3404, r5
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cmp #0x3404, r5
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jne wait_loop_8192
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jne wait_loop_8192
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mov #0x4000, r15
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mov #0x4000, r15
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/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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eint
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eint
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bis.b #0x01, &IE1
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bis.b #0x01, &IE1
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mov #0x5a18, &WDTCTL ;# Enable interval mode /32768 & clear counter
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mov #0x5a18, &WDTCTL ;# Enable interval mode /32768 & clear counter
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mov #0x0000, r4
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mov #0x0000, r4
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mov #0x0005, r5
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mov #0x0005, r5
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wait_loop_32768:
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wait_loop_32768:
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inc r4
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inc r4
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cmp #0x3405, r5
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cmp #0x3405, r5
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jne wait_loop_32768
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jne wait_loop_32768
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mov #0x5000, r15
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mov #0x5000, r15
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/* ---------------------- END OF TEST --------------- */
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/* ---------------------- END OF TEST --------------- */
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end_of_test:
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end_of_test:
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nop
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nop
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br #0xffff
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br #0xffff
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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WDOG_VECTOR:
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WDOG_VECTOR:
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bis #0x3400, r5
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bis #0x3400, r5
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mov &IFG1, r6
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mov &IFG1, r6
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mov r4, r7
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mov r4, r7
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reti
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reti
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/* ---------------------- INTERRUPT VECTORS --------------- */
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/* ---------------------- INTERRUPT VECTORS --------------- */
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.section .vectors, "a"
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.section .vectors, "a"
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 2
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.word end_of_test ; Interrupt 2
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.word end_of_test ; Interrupt 3
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.word end_of_test ; Interrupt 3
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 9
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.word end_of_test ; Interrupt 9
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.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
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.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 14 NMI
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.word end_of_test ; Interrupt 14 NMI
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.word main ; Interrupt 15 (highest priority) RESET
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.word main ; Interrupt 15 (highest priority) RESET
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