/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* WATCHDOG TIMER */
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/* WATCHDOG TIMER */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the Watdog timer: */
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/* Test the Watdog timer: */
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/* - Watchdog mode. */
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/* - Watchdog mode. */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 17 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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.global main
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.global main
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.set IE1, 0x0000
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.set IE1, 0x0000
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.set IFG1, 0x0002
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.set IFG1, 0x0002
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.set WDTCTL, 0x0120
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.set WDTCTL, 0x0120
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main:
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main:
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/* -------------- WATCHDOG TEST: STARTUP SEQUENCE --------------- */
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/* -------------- WATCHDOG TEST: STARTUP SEQUENCE --------------- */
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mov &IFG1, r4 ;# Check if we come out of a watchdog reset
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mov &IFG1, r4 ;# Check if we come out of a watchdog reset
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cmp #0x0000, r4
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cmp #0x0000, r4
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jeq RD_WR_ACCESS
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jeq RD_WR_ACCESS
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mov &0x0250, r15 ;# If yes, check RAM variable to see where to go next
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mov &0x0250, r15 ;# If yes, check RAM variable to see where to go next
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cmp #0x0000, r15
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cmp #0x0000, r15
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jeq RESET_64
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jeq RESET_64
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cmp #0x1000, r15
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cmp #0x1000, r15
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jeq RESET_512
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jeq RESET_512
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cmp #0x2000, r15
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cmp #0x2000, r15
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jeq RESET_8192
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jeq RESET_8192
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cmp #0x3000, r15
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cmp #0x3000, r15
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jeq RESET_32768
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jeq RESET_32768
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cmp #0x4000, r15
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cmp #0x4000, r15
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jeq CHECK_32768
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jeq CHECK_32768
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jmp end_of_test
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jmp end_of_test
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/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */
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/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */
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RD_WR_ACCESS:
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RD_WR_ACCESS:
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mov #0x0000, &0x0250
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mov #0x0000, &0x0250
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mov &WDTCTL, &0x0200
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mov &WDTCTL, &0x0200
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mov #0x5aff, &WDTCTL
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mov #0x5aff, &WDTCTL
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mov &WDTCTL, &0x0202
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mov &WDTCTL, &0x0202
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mov #0x5a55, &WDTCTL
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mov #0x5a55, &WDTCTL
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mov &WDTCTL, &0x0204
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mov &WDTCTL, &0x0204
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mov #0x5aaa, &WDTCTL
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mov #0x5aaa, &WDTCTL
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mov &WDTCTL, &0x0206
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mov &WDTCTL, &0x0206
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mov #0x5a00, &WDTCTL
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mov #0x5a00, &WDTCTL
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mov &WDTCTL, &0x0208
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mov &WDTCTL, &0x0208
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mov #0xDEAD, &WDTCTL ;# Generate reset through wrong password
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mov #0xDEAD, &WDTCTL ;# Generate reset through wrong password
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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/* -------------- WATCHDOG TEST: WATCHODG MODE /64 ------------ */
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/* -------------- WATCHDOG TEST: WATCHODG MODE /64 ------------ */
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RESET_64:
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RESET_64:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x1000, &0x0250
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mov #0x1000, &0x0250
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mov #0x5a0b, &WDTCTL ;# Enable watchdog mode /64 & clear counter
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mov #0x5a0b, &WDTCTL ;# Enable watchdog mode /64 & clear counter
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mov #0x0000, &0x0200
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mov #0x0000, &0x0200
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wait_loop_64:
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wait_loop_64:
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inc &0x0200
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inc &0x0200
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jmp wait_loop_64
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jmp wait_loop_64
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */
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RESET_512:
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RESET_512:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x2000, &0x0250
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mov #0x2000, &0x0250
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mov #0x5a0a, &WDTCTL ;# Enable watchdog mode /512 & clear counter
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mov #0x5a0a, &WDTCTL ;# Enable watchdog mode /512 & clear counter
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mov #0x0000, &0x0202
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mov #0x0000, &0x0202
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wait_loop_512:
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wait_loop_512:
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inc &0x0202
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inc &0x0202
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jmp wait_loop_512
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jmp wait_loop_512
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */
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RESET_8192:
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RESET_8192:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x3000, &0x0250
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mov #0x3000, &0x0250
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mov #0x5a09, &WDTCTL ;# Enable watchdog mode /8192 & clear counter
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mov #0x5a09, &WDTCTL ;# Enable watchdog mode /8192 & clear counter
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mov #0x0000, &0x0204
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mov #0x0000, &0x0204
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wait_loop_8192:
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wait_loop_8192:
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inc &0x0204
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inc &0x0204
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jmp wait_loop_8192
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jmp wait_loop_8192
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */
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RESET_32768:
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RESET_32768:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x4000, &0x0250
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mov #0x4000, &0x0250
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mov #0x5a08, &WDTCTL ;# Enable interval mode /32768 & clear counter
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mov #0x5a08, &WDTCTL ;# Enable interval mode /32768 & clear counter
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mov #0x0000, &0x0206
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mov #0x0000, &0x0206
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wait_loop_32768:
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wait_loop_32768:
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inc &0x0206
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inc &0x0206
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jmp wait_loop_32768
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jmp wait_loop_32768
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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CHECK_32768:
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CHECK_32768:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x5000, &0x0250
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mov #0x5000, &0x0250
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/* ---------------------- END OF TEST --------------- */
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/* ---------------------- END OF TEST --------------- */
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end_of_test:
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end_of_test:
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nop
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nop
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br #0xffff
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br #0xffff
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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WDOG_VECTOR:
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WDOG_VECTOR:
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bis #0x3400, r5
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bis #0x3400, r5
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mov &IFG1, r6
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mov &IFG1, r6
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mov r4, r7
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mov r4, r7
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reti
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reti
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/* ---------------------- INTERRUPT VECTORS --------------- */
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/* ---------------------- INTERRUPT VECTORS --------------- */
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.section .vectors, "a"
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.section .vectors, "a"
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 2
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.word end_of_test ; Interrupt 2
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.word end_of_test ; Interrupt 3
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.word end_of_test ; Interrupt 3
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 9
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.word end_of_test ; Interrupt 9
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.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
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.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 14 NMI
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.word end_of_test ; Interrupt 14 NMI
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.word main ; Interrupt 15 (highest priority) RESET
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.word main ; Interrupt 15 (highest priority) RESET
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