/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* WATCHDOG TIMER */
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/* WATCHDOG TIMER */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the Watdog timer: */
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/* Test the Watdog timer: */
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/* - Interval timer mode. */
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/* - Interval timer mode. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $ */
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/* $Rev: 19 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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/* */
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/* */
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/* Low Power modes: */
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/* Low Power modes: */
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/* - LPM0 <=> CPUOFF */
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/* - LPM0 <=> CPUOFF */
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/* - LPM1 <=> CPUOFF + SCG0 */
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/* - LPM1 <=> CPUOFF + SCG0 */
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/* - LPM2 <=> CPUOFF + SCG1 */
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/* - LPM2 <=> CPUOFF + SCG1 */
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/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */
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/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */
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/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */
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/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */
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/* */
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/* */
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/* Reminder: */
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/* Reminder: */
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/* - CPUOFF <=> turns off CPU. */
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/* - CPUOFF <=> turns off CPU. */
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/* - SCG0 <=> turns off DCO. */
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/* - SCG0 <=> turns off DCO. */
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/* - SCG1 <=> turns off SMCLK. */
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/* - SCG1 <=> turns off SMCLK. */
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/* - OSCOFF <=> turns off LFXT_CLK. */
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/* - OSCOFF <=> turns off LFXT_CLK. */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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.global main
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.include "pmem_defs.asm"
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.set DMEM_BASE, (__data_start )
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.set DMEM_200, (__data_start+0x00)
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.set DMEM_250, (__data_start+0x50)
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.set IE1, 0x0000
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.global main
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.set IFG1, 0x0002
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.set WDTCTL, 0x0120
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.macro LPM0
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.macro LPM0
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bis #0x0010, r2
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bis #0x0010, r2
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.endm
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.endm
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.macro LPM1
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.macro LPM1
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bis #0x0050, r2
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bis #0x0050, r2
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.endm
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.endm
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.macro LPM2
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.macro LPM2
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bis #0x0090, r2
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bis #0x0090, r2
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.endm
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.endm
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.macro LPM3
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.macro LPM3
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bis #0x00D0, r2
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bis #0x00D0, r2
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.endm
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.endm
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.macro LPM4
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.macro LPM4
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bis #0x00F0, r2
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bis #0x00F0, r2
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.endm
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.endm
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.macro LPM0_exit
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.macro LPM0_exit
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bic #0x0010, @r1
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bic #0x0010, @r1
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.endm
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.endm
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.macro LPM1_exit
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.macro LPM1_exit
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bic #0x0050, @r1
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bic #0x0050, @r1
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.endm
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.endm
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.macro LPM2_exit
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.macro LPM2_exit
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bic #0x0090, @r1
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bic #0x0090, @r1
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.endm
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.endm
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.macro LPM3_exit
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.macro LPM3_exit
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bic #0x00D0, @r1
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bic #0x00D0, @r1
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.endm
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.endm
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.macro LPM4_exit
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.macro LPM4_exit
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bic #0x00F0, @r1
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bic #0x00F0, @r1
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.endm
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.endm
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main:
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main:
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/* -------------- WATCHDOG TEST: WAKE-UP INTERVAL MODE ------------ */
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/* -------------- WATCHDOG TEST: WAKE-UP INTERVAL MODE ------------ */
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mov &IFG1, r4
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mov &IFG1, r4
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cmp #0x0001, &IFG1 ;# Check if we come out of a watchdog reset
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cmp #0x0001, &IFG1 ;# Check if we come out of a watchdog reset
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jeq end_of_test
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jeq end_of_test
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
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eint
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eint
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bis.b #0x01, &IE1
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bis.b #0x01, &IE1
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mov #0x0000, r6
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mov #0x0000, r6
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mov #0x5a1f, &WDTCTL ;# Enable interval mode /64 and select ACLK
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mov #0x5a1f, &WDTCTL ;# Enable interval mode /64 and select ACLK
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mov &WDTCTL, r5 ;# If ACLK is selected, go to LPM3... otherwhise go to LPM0
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mov &WDTCTL, r5 ;# If ACLK is selected, go to LPM3... otherwhise go to LPM0
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bit #0x0004, r5
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bit #0x0004, r5
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jnz lpm3_test
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jnz lpm3_test
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lpm0_test:
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lpm0_test:
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mov #0x1000, r15
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mov #0x1000, r15
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LPM0
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LPM0
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jmp lpm_test_done
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jmp lpm_test_done
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lpm3_test:
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lpm3_test:
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mov #0x1000, r15
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mov #0x1000, r15
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LPM3
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LPM3
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lpm_test_done:
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lpm_test_done:
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/* -------------- WATCHDOG TEST: WAKE-UP RESET MODE ------------ */
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/* -------------- WATCHDOG TEST: WAKE-UP RESET MODE ------------ */
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mov #0x5a0f, &WDTCTL ;# Enable reset mode /64 and select ACLK
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mov #0x5a0f, &WDTCTL ;# Enable reset mode /64 and select ACLK
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mov #0x5555, r7
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mov #0x5555, r7
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mov &WDTCTL, r5 ;# If ACLK is selected, go to LPM3... otherwhise go to LPM0
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mov &WDTCTL, r5 ;# If ACLK is selected, go to LPM3... otherwhise go to LPM0
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bit #0x0004, r5
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bit #0x0004, r5
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jnz lpm3_rst_test
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jnz lpm3_rst_test
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lpm0_rst_test:
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lpm0_rst_test:
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mov #0x1000, r15
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mov #0x1000, r15
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LPM0
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LPM0
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jmp lpm_rst_test_done
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jmp lpm_rst_test_done
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lpm3_rst_test:
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lpm3_rst_test:
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mov #0x1000, r15
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mov #0x1000, r15
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LPM3
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LPM3
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lpm_rst_test_done:
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lpm_rst_test_done:
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/* ---------------------- END OF TEST --------------- */
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/* ---------------------- END OF TEST --------------- */
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end_of_test:
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end_of_test:
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mov #0x5000, r15
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mov #0x5000, r15
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nop
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nop
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br #0xffff
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br #0xffff
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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/* ---------------------- INTERRUPT ROUTINES --------------- */
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WDOG_VECTOR:
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WDOG_VECTOR:
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inc r6 ;# Increment counter variable
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inc r6 ;# Increment counter variable
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cmp #10, r6
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cmp #10, r6
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jl end_of_irq
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jl end_of_irq
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mov &WDTCTL, r5 ;# If ACLK is selected, exit LPM3... otherwhise exit LPM0
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mov &WDTCTL, r5 ;# If ACLK is selected, exit LPM3... otherwhise exit LPM0
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bit #0x0004, r5
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bit #0x0004, r5
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jnz lpm3_test_exit
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jnz lpm3_test_exit
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lpm0_test_exit:
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lpm0_test_exit:
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mov #0x2000, r15
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mov #0x2000, r15
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LPM0_exit
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LPM0_exit
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reti
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reti
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lpm3_test_exit:
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lpm3_test_exit:
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mov #0x2000, r15
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mov #0x2000, r15
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LPM3_exit
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LPM3_exit
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end_of_irq:
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end_of_irq:
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mov #0x6666, r7
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mov #0x6666, r7
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reti
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reti
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/* ---------------------- INTERRUPT VECTORS --------------- */
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/* ---------------------- INTERRUPT VECTORS --------------- */
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.section .vectors, "a"
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.section .vectors, "a"
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 0 (lowest priority)
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 1
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.word end_of_test ; Interrupt 2
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.word end_of_test ; Interrupt 2
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.word end_of_test ; Interrupt 3
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.word end_of_test ; Interrupt 3
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 4
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 5
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 6
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 7
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 8
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.word end_of_test ; Interrupt 9
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.word end_of_test ; Interrupt 9
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.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
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.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 11
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 12
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 13
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.word end_of_test ; Interrupt 14 NMI
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.word end_of_test ; Interrupt 14 NMI
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.word main ; Interrupt 15 (highest priority) RESET
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.word main ; Interrupt 15 (highest priority) RESET
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