#!/usr/bin/tclsh
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#!/usr/bin/tclsh
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# Copyright (C) 2001 Authors
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# Copyright (C) 2001 Authors
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#
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#
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# This source file may be used and distributed without restriction provided
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# This source file may be used and distributed without restriction provided
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# that this copyright statement is not removed from the file and that any
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# that this copyright statement is not removed from the file and that any
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# derivative work contains the original copyright notice and the associated
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# derivative work contains the original copyright notice and the associated
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# disclaimer.
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# disclaimer.
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#
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#
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# This source file is free software; you can redistribute it and/or modify
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# This source file is free software; you can redistribute it and/or modify
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# it under the terms of the GNU Lesser General Public License as published
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# it under the terms of the GNU Lesser General Public License as published
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# by the Free Software Foundation; either version 2.1 of the License, or
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# by the Free Software Foundation; either version 2.1 of the License, or
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# (at your option) any later version.
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# (at your option) any later version.
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#
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#
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# This source is distributed in the hope that it will be useful, but WITHOUT
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# This source is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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# License for more details.
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# License for more details.
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#
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#
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# You should have received a copy of the GNU Lesser General Public License
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# You should have received a copy of the GNU Lesser General Public License
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# along with this source; if not, write to the Free Software Foundation,
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# along with this source; if not, write to the Free Software Foundation,
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# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#
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#
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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#
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#
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# File Name: run_analysis.tcl
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# File Name: run_analysis.tcl
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#
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#
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# Author(s):
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# Author(s):
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# - Olivier Girard, olgirard@gmail.com
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# - Olivier Girard, olgirard@gmail.com
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#
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#
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# $Rev: 17 $
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# $Rev: 17 $
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# $LastChangedBy: olivier.girard $
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# $LastChangedBy: olivier.girard $
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# $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
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# $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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###############################################################################
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###############################################################################
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# SET SOME GLOBAL VARIABLES #
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# SET SOME GLOBAL VARIABLES #
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###############################################################################
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###############################################################################
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# Analysis type
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# Analysis type
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set analysisType SPEED
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set analysisType SPEED
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#set analysisType AREA
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#set analysisType AREA
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# Set the different FPGA architectures & models to be checked
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# Set the different FPGA architectures & models to be checked
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set fpgaConfigs {{"Cyclone II" EP2C20F484C {6 7 8}}
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set fpgaConfigs {{"Cyclone II" EP2C20F484C {6 7 8}}
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{"Cyclone III" EP3C55F484C {6 7 8}}
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{"Cyclone III" EP3C55F484C {6 7 8}}
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{"Cyclone IV GX" EP4CGX22CF19C {6 7 8}}
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{"Cyclone IV GX" EP4CGX22CF19C {6 7 8}}
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{"Arria GX" EP1AGX50CF484C {6}}
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{"Arria GX" EP1AGX50CF484C {6}}
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{"Arria II GX" EP2AGX45DF29C {4 5 6}}
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{"Arria II GX" EP2AGX45DF29C {4 5 6}}
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{"Stratix" EP1S10F484C {5 6 7}}
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{"Stratix" EP1S10F484C {5 6 7}}
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{"Stratix II" EP2S15F484C {3 4 5}}
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{"Stratix II" EP2S15F484C {3 4 5}}
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{"Stratix III" EP3SE50F484C {2 3 4}}}
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{"Stratix III" EP3SE50F484C {2 3 4}}}
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set fpgaConfigs {{"Cyclone II" EP2C20F484C {7}}}
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# Set the different RTL configurations to be analysed
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# Set the different RTL configurations to be analysed
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set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3}
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set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER}
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set rtlConfigs {{ 12 10 0 0 0 0 0 }
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set rtlConfigs {{ 12 10 0 0 0 0 0 0}
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{ 12 10 1 0 0 0 0 }
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{ 12 10 1 0 0 0 0 0}
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{ 12 10 1 1 0 0 0 }
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{ 12 10 1 1 0 0 0 0}
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{ 12 10 1 1 1 0 0 }
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{ 12 10 1 1 1 0 0 0}
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{ 12 10 1 1 1 1 0 }
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{ 12 10 1 1 1 1 0 0}
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{ 12 10 1 1 1 1 1 }}
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{ 12 10 1 1 1 1 1 0}}
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set rtlConfigs {{ 12 10 0 0 0 0 0 }}
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set rtlConfigs {{ 12 10 0 0 0 0 0 1}}
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# RTL configuration files
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# RTL configuration files
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set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
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set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
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set rtlConfigFile "./src/arch.v"
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set rtlConfigFile "./src/arch.v"
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###############################################################################
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###############################################################################
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# PERFORM ANALYSIS #
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# PERFORM ANALYSIS #
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###############################################################################
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###############################################################################
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foreach rtlConfig $rtlConfigs {
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foreach rtlConfig $rtlConfigs {
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#-------------------------------------------------------------------------#
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#-------------------------------------------------------------------------#
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# Generate RTL configuration #
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# Generate RTL configuration #
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#-------------------------------------------------------------------------#
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#-------------------------------------------------------------------------#
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# Read original define file
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# Read original define file
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if [catch {open $omspConfigFile r} f_omspConfigFile] {
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if [catch {open $omspConfigFile r} f_omspConfigFile] {
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puts "ERROR: Cannot open file $omspConfigFile"
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puts "ERROR: Cannot open file $omspConfigFile"
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exit 1
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exit 1
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}
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}
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set configFile [read $f_omspConfigFile]
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set configFile [read $f_omspConfigFile]
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close $f_omspConfigFile
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close $f_omspConfigFile
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# Update defines
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# Update defines
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set idx 0
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set idx 0
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foreach rtlDefine $rtlDefines {
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foreach rtlDefine $rtlDefines {
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if {[regsub "`define\\s+$rtlDefine\\s+\\d+" $configFile "`define $rtlDefine [lindex $rtlConfig $idx]" configFile]} {
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if {[regsub "`define\\s+$rtlDefine\\s+\\d+" $configFile "`define $rtlDefine [lindex $rtlConfig $idx]" configFile]} {
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} else {
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} else {
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if {[lindex $rtlConfig $idx]==0} {
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if {[lindex $rtlConfig $idx]==0} {
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regsub "\\n`define\\s+$rtlDefine" $configFile "\n//`define $rtlDefine" configFile
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regsub "\\n`define\\s+$rtlDefine" $configFile "\n//`define $rtlDefine" configFile
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}
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}
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}
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}
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set idx [expr $idx+1]
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set idx [expr $idx+1]
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}
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}
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# Write the new file
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# Write the new file
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set f_configFile [open "./src/[file tail $omspConfigFile]" w]
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set f_configFile [open "./src/[file tail $omspConfigFile]" w]
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puts $f_configFile $configFile
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puts $f_configFile $configFile
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close $f_configFile
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close $f_configFile
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#-------------------------------------------------------------------------#
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#-------------------------------------------------------------------------#
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# Perform analysis for each FPGA #
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# Perform analysis for each FPGA #
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#-------------------------------------------------------------------------#
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#-------------------------------------------------------------------------#
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foreach fpgaConfig $fpgaConfigs {
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foreach fpgaConfig $fpgaConfigs {
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foreach speedGrade [lindex $fpgaConfig 2] {
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foreach speedGrade [lindex $fpgaConfig 2] {
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# Create verilog arch define
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# Create verilog arch define
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set f_configFile [open $rtlConfigFile w]
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set f_configFile [open $rtlConfigFile w]
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regsub -all {\s} [lindex $fpgaConfig 0] {_} defineName
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regsub -all {\s} [lindex $fpgaConfig 0] {_} defineName
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set defineName [string toupper $defineName]
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set defineName [string toupper $defineName]
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puts $f_configFile "\n`define $defineName\n"
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puts $f_configFile "\n`define $defineName\n"
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close $f_configFile
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close $f_configFile
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# Cleanup
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# Cleanup
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file delete -force ./WORK
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file delete -force ./WORK
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file mkdir ./WORK
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file mkdir ./WORK
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cd ./WORK
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cd ./WORK
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# Copy Quartus tcl command file
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# Copy Quartus tcl command file
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if [catch {open "../openMSP430_fpga.tcl" r} f_quartus_tcl] {
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if [catch {open "../openMSP430_fpga.tcl" r} f_quartus_tcl] {
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puts "ERROR: Cannot open Quartus command file file ../openMSP430_fpga.tcl"
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puts "ERROR: Cannot open Quartus command file file ../openMSP430_fpga.tcl"
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exit 1
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exit 1
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}
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}
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set quartus_tcl [read $f_quartus_tcl]
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set quartus_tcl [read $f_quartus_tcl]
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close $f_quartus_tcl
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close $f_quartus_tcl
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set fpgaName "[lindex $fpgaConfig 1]$speedGrade"
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set fpgaName "[lindex $fpgaConfig 1]$speedGrade"
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regsub -all {<DEVICE_NAME>} $quartus_tcl "$fpgaName" quartus_tcl
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regsub -all {<DEVICE_NAME>} $quartus_tcl "$fpgaName" quartus_tcl
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regsub -all {<DEVICE_FAMILY>} $quartus_tcl "[lindex $fpgaConfig 0]" quartus_tcl
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regsub -all {<DEVICE_FAMILY>} $quartus_tcl "[lindex $fpgaConfig 0]" quartus_tcl
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regsub -all {<SPEED_AREA>} $quartus_tcl "$analysisType" quartus_tcl
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regsub -all {<SPEED_AREA>} $quartus_tcl "$analysisType" quartus_tcl
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set f_quartus_tcl [open "openMSP430_fpga.tcl" w]
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set f_quartus_tcl [open "openMSP430_fpga.tcl" w]
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puts $f_quartus_tcl $quartus_tcl
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puts $f_quartus_tcl $quartus_tcl
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close $f_quartus_tcl
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close $f_quartus_tcl
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# Run synthesis
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# Run synthesis
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puts "#####################################################################################"
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puts "#####################################################################################"
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puts "# START SYNTHESIS ($analysisType optimized)"
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puts "# START SYNTHESIS ($analysisType optimized)"
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puts "#===================================================================================="
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puts "#===================================================================================="
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puts "# [lindex $fpgaConfig 0] ([lindex $fpgaConfig 1]), speedgrade: -$speedGrade"
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puts "# [lindex $fpgaConfig 0] ([lindex $fpgaConfig 1]), speedgrade: -$speedGrade"
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puts "#===================================================================================="
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puts "#===================================================================================="
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puts "# $rtlDefines"
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puts "# $rtlDefines"
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puts "# $rtlConfig"
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puts "# $rtlConfig"
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puts "#===================================================================================="
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puts "#===================================================================================="
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if {[catch "exec quartus_sh -t openMSP430_fpga.tcl | tee quartus_sh.log"]} {
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if {[catch "exec quartus_sh -t openMSP430_fpga.tcl | tee quartus_sh.log"]} {
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puts "ERROR: Synthesis error !!!!!!"
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puts "ERROR: Synthesis error !!!!!!"
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exit 1
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exit 1
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}
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}
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# Extract timing information
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# Extract timing information
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if [catch {open "openMSP430_fpga.tan.summary" r} f_timing] {
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if [catch {open "openMSP430_fpga.tan.summary" r} f_timing] {
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if [catch {open "openMSP430_fpga.sta.rpt" r} f_timing] {
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if [catch {open "openMSP430_fpga.sta.rpt" r} f_timing] {
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puts "ERROR: Cannot open timing file"
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puts "ERROR: Cannot open timing file"
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exit 1
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exit 1
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}
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}
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}
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}
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set timingFile [read $f_timing]
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set timingFile [read $f_timing]
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close $f_timing
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close $f_timing
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if {![regexp {(Type\s+?: Clock Setup: 'dco_clk'.*?)From} $timingFile whole_match timing]} {
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if {![regexp {(Type\s+?: Clock Setup: 'dco_clk'.*?)From} $timingFile whole_match timing]} {
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regexp {([^\n]+?\n;\s+Slow .*?Model Fmax Summary[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n)} $timingFile whole_match timing
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regexp {([^\n]+?\n;\s+Slow .*?Model Fmax Summary[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n)} $timingFile whole_match timing
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}
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}
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puts $timing
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puts $timing
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puts "===================================================================================="
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puts "===================================================================================="
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# Extract size information
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# Extract size information
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if [catch {open "openMSP430_fpga.fit.summary" r} f_log] {
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if [catch {open "openMSP430_fpga.fit.summary" r} f_log] {
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puts "ERROR: Cannot open timing file openMSP430_fpga.fit.summary"
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puts "ERROR: Cannot open timing file openMSP430_fpga.fit.summary"
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exit 1
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exit 1
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}
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}
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set logFile [read $f_log]
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set logFile [read $f_log]
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close $f_log
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close $f_log
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regexp {Timing Models[^\n]+\n(.+)} $logFile whole_match area
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regexp {Timing Models[^\n]+\n(.+)} $logFile whole_match area
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puts $area
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puts $area
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puts "===================================================================================="
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puts "===================================================================================="
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puts "# SYNTHESIS DONE"
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puts "# SYNTHESIS DONE"
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puts "#####################################################################################"
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puts "#####################################################################################"
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puts ""
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puts ""
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cd ../
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cd ../
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}
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}
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}
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}
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}
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}
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exit 0
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exit 0
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