##############################################################################
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##############################################################################
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# #
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# #
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# READ DESING RTL #
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# READ DESING RTL #
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# #
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# #
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##############################################################################
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##############################################################################
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|
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set DESIGN_NAME "openMSP430"
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set DESIGN_NAME "openMSP430"
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set RTL_SOURCE_FILES {../../rtl/verilog/openMSP430.v
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set RTL_SOURCE_FILES {../../rtl/verilog/openMSP430_defines.v
|
|
../../rtl/verilog/openMSP430.v
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../../rtl/verilog/omsp_frontend.v
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../../rtl/verilog/omsp_frontend.v
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../../rtl/verilog/omsp_execution_unit.v
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../../rtl/verilog/omsp_execution_unit.v
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../../rtl/verilog/omsp_register_file.v
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../../rtl/verilog/omsp_register_file.v
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../../rtl/verilog/omsp_alu.v
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../../rtl/verilog/omsp_alu.v
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../../rtl/verilog/omsp_sfr.v
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../../rtl/verilog/omsp_sfr.v
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../../rtl/verilog/omsp_clock_module.v
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../../rtl/verilog/omsp_clock_module.v
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../../rtl/verilog/omsp_mem_backbone.v
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../../rtl/verilog/omsp_mem_backbone.v
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../../rtl/verilog/omsp_watchdog.v
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../../rtl/verilog/omsp_watchdog.v
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../../rtl/verilog/omsp_dbg.v
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../../rtl/verilog/omsp_dbg.v
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../../rtl/verilog/omsp_dbg_uart.v
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../../rtl/verilog/omsp_dbg_uart.v
|
../../rtl/verilog/omsp_dbg_hwbrk.v
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../../rtl/verilog/omsp_dbg_hwbrk.v
|
../../rtl/verilog/omsp_multiplier.v
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../../rtl/verilog/omsp_multiplier.v
|
|
../../rtl/verilog/omsp_sync_reset.v
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../../rtl/verilog/omsp_sync_cell.v
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../../rtl/verilog/omsp_sync_cell.v
|
|
../../rtl/verilog/omsp_scan_mux.v
|
|
../../rtl/verilog/omsp_and_gate.v
|
|
../../rtl/verilog/omsp_wakeup_cell.v
|
|
../../rtl/verilog/omsp_clock_gate.v
|
|
../../rtl/verilog/omsp_clock_mux.v
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}
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}
|
|
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set_svf ./results/$DESIGN_NAME.svf
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set_svf ./results/$DESIGN_NAME.svf
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define_design_lib WORK -path ./WORK
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define_design_lib WORK -path ./WORK
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analyze -format verilog $RTL_SOURCE_FILES
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analyze -format verilog $RTL_SOURCE_FILES
|
|
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elaborate $DESIGN_NAME
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elaborate $DESIGN_NAME
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link
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link
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|
|
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# Check design structure after reading verilog
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# Check design structure after reading verilog
|
current_design $DESIGN_NAME
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current_design $DESIGN_NAME
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redirect ./results/report.check {check_design}
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redirect ./results/report.check {check_design}
|
|
|
