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#=============================================================================#
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#=============================================================================#
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# Read technology library #
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# Read technology library #
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#=============================================================================#
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#=============================================================================#
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source -echo -verbose ./library.tcl
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source -echo -verbose ./library.tcl
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#=============================================================================#
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#=============================================================================#
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# Read design RTL #
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# Read design RTL #
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#=============================================================================#
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#=============================================================================#
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source -echo -verbose ./read.tcl
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source -echo -verbose ./read.tcl
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#=============================================================================#
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#=============================================================================#
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# Set design constraints #
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# Set design constraints #
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#=============================================================================#
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#=============================================================================#
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source -echo -verbose ./constraints.tcl
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source -echo -verbose ./constraints.tcl
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#=============================================================================#
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#=============================================================================#
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# Set operating conditions & wire-load models #
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# Set operating conditions & wire-load models #
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#=============================================================================#
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#=============================================================================#
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# Set operating conditions
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# Set operating conditions
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set_operating_conditions -max $LIB_WC_OPCON -max_library $LIB_WC_NAME \
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set_operating_conditions -max $LIB_WC_OPCON -max_library $LIB_WC_NAME \
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-min $LIB_WC_OPCON -min_library $LIB_BC_NAME
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-min $LIB_WC_OPCON -min_library $LIB_BC_NAME
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# Set wire-load models
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# Set wire-load models
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set_wire_load_mode top
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set_wire_load_mode top
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set_wire_load_model -name $LIB_WIRE_LOAD -max -library $LIB_WC_NAME
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set_wire_load_model -name $LIB_WIRE_LOAD -max -library $LIB_WC_NAME
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set_wire_load_model -name $LIB_WIRE_LOAD -min -library $LIB_BC_NAME
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set_wire_load_model -name $LIB_WIRE_LOAD -min -library $LIB_BC_NAME
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#=============================================================================#
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#=============================================================================#
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# Synthesize #
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# Synthesize #
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#=============================================================================#
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#=============================================================================#
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# Prevent assignment statements in the Verilog netlist.
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# Prevent assignment statements in the Verilog netlist.
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set_fix_multiple_port_nets -all -buffer_constants
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set_fix_multiple_port_nets -all -buffer_constants
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# Configure & Synthesize
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# Configure & Synthesize
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current_design $DESIGN_NAME
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current_design $DESIGN_NAME
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set_max_area 0.0
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set_max_area 0.0
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set_flatten false
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set_flatten false
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set_structure true -timing true -boolean false
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set_structure true -timing true -boolean false
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compile -map_effort high -area_effort high
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compile -map_effort high -area_effort high
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#compile_ultra -area_high_effort_script
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#compile_ultra -area_high_effort_script
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#compile_ultra -area_high_effort_script -no_autoungroup -no_boundary_optimization
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#compile_ultra -area_high_effort_script -no_autoungroup -no_boundary_optimization
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#=============================================================================#
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#=============================================================================#
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# Reports generation #
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# Reports generation #
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#=============================================================================#
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#=============================================================================#
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redirect ./results/report.timing {check_timing}
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redirect ./results/report.timing {check_timing}
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redirect ./results/report.constraints {report_constraints -all_violators -verbose}
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redirect ./results/report.constraints {report_constraints -all_violators -verbose}
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redirect ./results/report.paths.max {report_timing -path end -delay max -max_paths 200 -nworst 2}
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redirect ./results/report.paths.max {report_timing -path end -delay max -max_paths 200 -nworst 2}
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redirect ./results/report.full_paths.max {report_timing -path full -delay max -max_paths 5 -nworst 2}
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redirect ./results/report.full_paths.max {report_timing -path full -delay max -max_paths 5 -nworst 2}
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redirect ./results/report.paths.min {report_timing -path end -delay min -max_paths 200 -nworst 2}
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redirect ./results/report.paths.min {report_timing -path end -delay min -max_paths 200 -nworst 2}
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redirect ./results/report.full_paths.min {report_timing -path full -delay min -max_paths 5 -nworst 2}
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redirect ./results/report.full_paths.min {report_timing -path full -delay min -max_paths 5 -nworst 2}
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redirect ./results/report.area {report_area}
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redirect ./results/report.refs {report_reference}
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redirect ./results/report.refs {report_reference}
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redirect ./results/report.area {report_area}
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# Add NAND2 size equivalent report to the area report file
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if {[info exists NAND2_NAME]} {
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set nand2_area [get_attribute [get_lib_cell $LIB_WC_NAME/$NAND2_NAME] area]
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redirect -variable area {report_area}
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regexp {Total cell area:\s+([^\n]+)\n} $area whole_match area
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set nand2_eq [expr $area/$nand2_area]
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set fp [open "./results/report.area" a]
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puts $fp ""
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puts $fp "NAND2 equivalent cell area: $nand2_eq"
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close $fp
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}
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#=============================================================================#
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#=============================================================================#
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# Dump gate level netlist & final DDC file #
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# Dump gate level netlist & final DDC file #
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#=============================================================================#
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#=============================================================================#
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current_design $DESIGN_NAME
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current_design $DESIGN_NAME
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write -hierarchy -format verilog -output "./results/$DESIGN_NAME.gate.v"
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write -hierarchy -format verilog -output "./results/$DESIGN_NAME.gate.v"
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write -hierarchy -format ddc -output "./results/$DESIGN_NAME.ddc"
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write -hierarchy -format ddc -output "./results/$DESIGN_NAME.ddc"
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quit
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quit
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