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<html><head><title>openMSP430 Integration and Connectivity</title></head><body><br>
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<html><head><title>openMSP430 Integration and Connectivity</title></head><body><br>
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<a name="TOC"></a>
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<a name="TOC"></a>
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<h3>Table of content</h3>
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<h3>Table of content</h3>
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<ul>
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<ul>
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<li><a href="#1.%20Overview"> 1. Overview</a></li>
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<li><a href="#1.%20Overview"> 1. Overview</a></li>
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<li><a href="#2.%20Clocks"> 2. Clocks</a></li>
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<li><a href="#2.%20Clocks"> 2. Clocks</a></li>
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<li><a href="#3.%20Resets"> 3. Resets</a></li>
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<li><a href="#3.%20Resets"> 3. Resets</a></li>
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<li><a href="#4.%20Program%20Memory"> 4. Program Memory</a></li>
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<li><a href="#4.%20Program%20Memory"> 4. Program Memory</a></li>
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<li><a href="#5.%20Data%20Memory"> 5. Data Memory</a></li>
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<li><a href="#5.%20Data%20Memory"> 5. Data Memory</a></li>
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<li><a href="#6.%20Peripherals"> 6. Peripherals</a></li>
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<li><a href="#6.%20Peripherals"> 6. Peripherals</a></li>
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<li><a href="#7.%20Interrupts"> 7. Interrupts</a></li>
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<li><a href="#7.%20DMA%20Interface"> 7. Direct Memory Access Interface</a></li>
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<li><a href="#8.%20Serial%20Debug%20Interface">8. Serial Debug Interface</a></li>
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<li><a href="#8.%20Interrupts"> 8. Interrupts</a></li>
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<li><a href="#9.%20Serial%20Debug%20Interface">9. Serial Debug Interface</a></li>
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<ul>
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<ul>
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<li><a href="#8.1%20UART"> 8.1 UART Configuration</a></li>
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<li><a href="#9.1%20UART"> 9.1 UART Configuration</a></li>
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<li><a href="#8.2%20I2C"> 8.2 I2C Configuration</a></li>
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<li><a href="#9.2%20I2C"> 9.2 I2C Configuration</a></li>
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</ul>
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</ul>
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</ul>
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</ul>
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<a name="1. Overview"></a>
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<a name="1. Overview"></a>
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<h1>1. Overview</h1>
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<h1>1. Overview</h1>
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This chapter aims to give a comprehensive description of all openMSP430
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This chapter aims to give a comprehensive description of all openMSP430
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core interfaces in order to facilitate its integration within an ASIC
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core interfaces in order to facilitate its integration within an ASIC
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or FPGA.<br><br>The
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or FPGA.<br><br>The
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following diagram shows an overview of the openMSP430 core connectivity
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following diagram shows an overview of the openMSP430 core connectivity
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in an FPGA system (i.e. all ASIC specific pins are left unused):<br><br>
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in an FPGA system (i.e. all ASIC specific pins are left unused):<br><br>
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<img src="http://opencores.org/usercontent,img,1353268529" alt="Core Integration" title="Core Integration" width="100%">
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<img src="http://opencores.org/usercontent,img,1430948924" alt="Core Integration" title="Core Integration" width="100%">
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<br><br>
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<br><br>
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The full pinout of the core is summarized in the following table.<br>
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The full pinout of the core is summarized in the following table.<br>
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<br>
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<br>
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<table border="1">
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<table border="1">
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<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td style="vertical-align: top; text-align: center;"><span style="font-weight: bold;">Clock</span><br style="font-weight: bold;">
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<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td style="vertical-align: top; text-align: center;"><span style="font-weight: bold;">Clock</span><br style="font-weight: bold;">
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<span style="font-weight: bold;">Domain</span><br>
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<span style="font-weight: bold;">Domain</span><br>
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</td>
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</td>
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<td align="center"><b>Description</b></td> </tr>
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<td align="center"><b>Description</b></td> </tr>
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<tr> <td colspan="5" align="center"> <b><i>Clocks</i></b> </td></tr>
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<tr> <td colspan="5" align="center"> <b><i>Clocks</i></b> </td></tr>
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<tr>
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<tr>
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<td> <a href="#2.%20Clocks">cpu_en</a> </td>
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<td> <a href="#2.%20Clocks">cpu_en</a> </td>
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<td style="text-align: center;"> Input </td>
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<td style="text-align: center;"> Input </td>
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<td style="text-align: center;"> 1 </td>
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<td style="text-align: center;"> 1 </td>
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<td style="vertical-align: top; text-align: center;"><async><br>
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<td style="vertical-align: top; text-align: center;"><async><br>
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or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
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or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
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<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">Enable CPU code execution (asynchronous and non-glitchy).<br>Set to 1 if unused.</span> </td>
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<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">Enable CPU code execution (asynchronous and non-glitchy).<br>Set to 1 if unused.</span> </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#2.%20Clocks">dco_clk</a> </td>
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<td> <a href="#2.%20Clocks">dco_clk</a> </td>
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<td style="text-align: center;"> Input </td>
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<td style="text-align: center;"> Input </td>
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<td style="text-align: center;"> 1 </td>
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<td style="text-align: center;"> 1 </td>
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<td style="vertical-align: top; text-align: center;">-<br>
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<td style="vertical-align: top; text-align: center;">-<br>
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</td>
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</td>
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<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">Fast oscillator (fast clock)</span> </td>
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<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">Fast oscillator (fast clock)</span> </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#2.%20Clocks">lfxt_clk</a> </td>
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<td> <a href="#2.%20Clocks">lfxt_clk</a> </td>
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<td style="text-align: center;"> Input </td>
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<td style="text-align: center;"> Input </td>
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<td style="text-align: center;"> 1 </td>
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<td style="text-align: center;"> 1 </td>
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<td style="vertical-align: top; text-align: center;">-<br>
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<td style="vertical-align: top; text-align: center;">-<br>
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</td>
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</td>
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<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">Low frequency oscillator (typ. 32kHz)<br>Set to 0 if unused.</span></td>
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<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">Low frequency oscillator (typ. 32kHz)<br>Set to 0 if unused.</span></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#2.%20Clocks">mclk</a> </td>
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<td> <a href="#2.%20Clocks">mclk</a> </td>
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<td style="text-align: center;"> Output </td>
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<td style="text-align: center;"> Output </td>
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<td style="text-align: center;"> 1 </td>
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<td style="text-align: center;"> 1 </td>
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<td style="vertical-align: top; text-align: center;">-<br>
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<td style="vertical-align: top; text-align: center;">-<br>
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</td>
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</td>
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<td> Main system clock </td>
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<td> Main system clock </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#2.%20Clocks">aclk_en</a> </td>
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<td> <a href="#2.%20Clocks">aclk_en</a> </td>
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<td style="text-align: center;"> Output </td>
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<td style="text-align: center;"> Output </td>
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<td style="text-align: center;"> 1 </td>
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<td style="text-align: center;"> 1 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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</td>
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<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">FPGA ONLY: ACLK enable</span> </td>
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<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">FPGA ONLY: ACLK enable</span> </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#2.%20Clocks">smclk_en</a> </td>
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<td> <a href="#2.%20Clocks">smclk_en</a> </td>
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<td style="text-align: center;"> Output </td>
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<td style="text-align: center;"> Output </td>
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<td style="text-align: center;"> 1 </td>
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<td style="text-align: center;"> 1 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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</td>
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<td> <span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">FPGA ONLY: SMCLK enable</span> </td>
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<td> <span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">FPGA ONLY: SMCLK enable</span> </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">dco_enable</a></td>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">dco_enable</a></td>
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<td style="vertical-align: top; text-align: center;">Output<br>
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<td style="vertical-align: top; text-align: center;">Output<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;">1<br>
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<td style="vertical-align: top; text-align: center;">1<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;">dco_clk<br>
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<td style="vertical-align: top; text-align: center;">dco_clk<br>
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</td>
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</td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: Fast oscillator enable</span></td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: Fast oscillator enable</span></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">dco_wkup</a></td>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">dco_wkup</a></td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">1<br>
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<td style="vertical-align: top; text-align: center;">1<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;"><async><br>
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<td style="vertical-align: top; text-align: center;"><async><br>
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</td>
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</td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: Fast oscillator wakeup (asynchronous)</span></td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: Fast oscillator wakeup (asynchronous)</span></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">lfxt_enable</a></td>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">lfxt_enable</a></td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">1<br>
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<td style="vertical-align: top; text-align: center;">1<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;">lfxt_clk<br>
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<td style="vertical-align: top; text-align: center;">lfxt_clk<br>
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</td>
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</td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: Low frequency oscillator enable</span></td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: Low frequency oscillator enable</span></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">lfxt_wkup</a></td>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">lfxt_wkup</a></td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">1<br>
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<td style="vertical-align: top; text-align: center;">1<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;"><async><br>
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<td style="vertical-align: top; text-align: center;"><async><br>
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</td>
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</td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: Low frequency oscillator wakeup (asynchronous)</span></td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: Low frequency oscillator wakeup (asynchronous)</span></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">aclk</a></td>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">aclk</a></td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">1<br>
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<td style="vertical-align: top; text-align: center;">1<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;">-<br>
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<td style="vertical-align: top; text-align: center;">-<br>
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</td>
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</td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: ACLK</span></td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: ACLK</span></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">smclk</a></td>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">smclk</a></td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">Output</td>
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<td style="vertical-align: top; text-align: center;">1<br>
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<td style="vertical-align: top; text-align: center;">1<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;">-<br>
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<td style="vertical-align: top; text-align: center;">-<br>
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</td>
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</td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: SMCLK</span></td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: SMCLK</span></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">wkup</a></td>
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<td style="vertical-align: top;"><a href="integration.html#2.%20Clocks">wkup</a></td>
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<td style="vertical-align: top; text-align: center;">Input<br>
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<td style="vertical-align: top; text-align: center;">Input<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;">1<br>
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<td style="vertical-align: top; text-align: center;">1<br>
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</td>
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</td>
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<td style="vertical-align: top; text-align: center;"><async><br>
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<td style="vertical-align: top; text-align: center;"><async><br>
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</td>
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</td>
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<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: System Wake-up (asynchronous and non-glitchy)<br>Set to 0 if unused.</span></td>
|
<td style="vertical-align: top;"><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">ASIC ONLY: System Wake-up (asynchronous and non-glitchy)<br>Set to 0 if unused.</span></td>
|
</tr>
|
</tr>
|
<tr> <td colspan="5" align="center"> <b><i>Resets</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Resets</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> <a href="#3.%20Resets">puc_rst</a> </td>
|
<td> <a href="#3.%20Resets">puc_rst</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
</td>
|
</td>
|
<td> Main system reset </td>
|
<td> Main system reset </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#3.%20Resets">reset_n</a> </td>
|
<td> <a href="#3.%20Resets">reset_n</a> </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
</td>
|
</td>
|
<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">Reset Pin (active low, asynchronous and non-glitchy)</span> </td>
|
<td><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">Reset Pin (active low, asynchronous and non-glitchy)</span> </td>
|
</tr>
|
</tr>
|
|
|
|
|
<tr> <td colspan="5" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> <a href="#4.%20Program%20Memory">pmem_addr</a> </td>
|
<td> <a href="#4.%20Program%20Memory">pmem_addr</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"><small> `PMEM_AWIDTH</small><sup style="color: red; font-weight: bold;">1</sup> </td>
|
<td style="text-align: center;"><small> `PMEM_AWIDTH</small><sup style="color: red; font-weight: bold;">1</sup> </td>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
</td>
|
</td>
|
<td> Program Memory address </td>
|
<td> Program Memory address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#4.%20Program%20Memory">pmem_cen</a> </td>
|
<td> <a href="#4.%20Program%20Memory">pmem_cen</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Program Memory chip enable (low active) </td>
|
<td> Program Memory chip enable (low active) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#4.%20Program%20Memory">pmem_din</a> </td>
|
<td> <a href="#4.%20Program%20Memory">pmem_din</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Program Memory data input<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"> (optional<span class="Apple-converted-space"> </span><b><sup><font color="#ff0000">2</font></sup></b>)</span> </td>
|
<td> Program Memory data input<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"> (optional<span class="Apple-converted-space"> </span><b><sup><font color="#ff0000">2</font></sup></b>)</span> </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#4.%20Program%20Memory">pmem_dout</a> </td>
|
<td> <a href="#4.%20Program%20Memory">pmem_dout</a> </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Program Memory data output </td>
|
<td> Program Memory data output </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#4.%20Program%20Memory">pmem_wen</a> </td>
|
<td> <a href="#4.%20Program%20Memory">pmem_wen</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 2 </td>
|
<td style="text-align: center;"> 2 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Program Memory write byte enable (low active) <span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">(optional<span class="Apple-converted-space"> </span><b><sup><font color="#ff0000">2</font></sup></b>)</span> </td>
|
<td> Program Memory write byte enable (low active) <span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">(optional<span class="Apple-converted-space"> </span><b><sup><font color="#ff0000">2</font></sup></b>)</span> </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="5" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> <a href="#5.%20Data%20Memory">dmem_addr</a> </td>
|
<td> <a href="#5.%20Data%20Memory">dmem_addr</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"><small> `DMEM_AWIDTH</small><sup style="font-weight: bold; color: red;">1</sup> </td>
|
<td style="text-align: center;"><small> `DMEM_AWIDTH</small><sup style="font-weight: bold; color: red;">1</sup> </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Data Memory address </td>
|
<td> Data Memory address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#5.%20Data%20Memory">dmem_cen</a> </td>
|
<td> <a href="#5.%20Data%20Memory">dmem_cen</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Data Memory chip enable (low active) </td>
|
<td> Data Memory chip enable (low active) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#5.%20Data%20Memory">dmem_din</a> </td>
|
<td> <a href="#5.%20Data%20Memory">dmem_din</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Data Memory data input </td>
|
<td> Data Memory data input </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#5.%20Data%20Memory">dmem_dout</a> </td>
|
<td> <a href="#5.%20Data%20Memory">dmem_dout</a> </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Data Memory data output </td>
|
<td> Data Memory data output </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#5.%20Data%20Memory">dmem_wen</a> </td>
|
<td> <a href="#5.%20Data%20Memory">dmem_wen</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 2 </td>
|
<td style="text-align: center;"> 2 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Data Memory write byte enable (low active) </td>
|
<td> Data Memory write byte enable (low active) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="5" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> <a href="#6.%20Peripherals">per_addr</a> </td>
|
<td> <a href="#6.%20Peripherals">per_addr</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 14 </td>
|
<td style="text-align: center;"> 14 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Peripheral address </td>
|
<td> Peripheral address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#6.%20Peripherals">per_din</a> </td>
|
<td> <a href="#6.%20Peripherals">per_din</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Peripheral data input </td>
|
<td> Peripheral data input </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#6.%20Peripherals">per_dout</a> </td>
|
<td> <a href="#6.%20Peripherals">per_dout</a> </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="text-align: center;"> 16 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Peripheral data output </td>
|
<td> Peripheral data output </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#6.%20Peripherals">per_en</a> </td>
|
<td> <a href="#6.%20Peripherals">per_en</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Peripheral enable (high active) </td>
|
<td> Peripheral enable (high active) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#6.%20Peripherals">per_we</a> </td>
|
<td> <a href="#6.%20Peripherals">per_we</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 2 </td>
|
<td style="text-align: center;"> 2 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Peripheral write byte enable (high active) </td>
|
<td> Peripheral write byte enable (high active) </td>
|
</tr>
|
</tr>
|
|
<tr> <td colspan="5" align="center"> <b><i>Direct Memory Access interface</i></b> </td></tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_addr</a> </td>
|
|
<td style="text-align: center;"> Input </td>
|
|
<td style="text-align: center;"> 15 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Direct Memory Access address </td>
|
|
</tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_din</a> </td>
|
|
<td style="text-align: center;"> Input </td>
|
|
<td style="text-align: center;"> 16 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Direct Memory Access data input </td>
|
|
</tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_dout</a> </td>
|
|
<td style="text-align: center;"> Output </td>
|
|
<td style="text-align: center;"> 16 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Direct Memory Access data output </td>
|
|
</tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_en</a> </td>
|
|
<td style="text-align: center;"> Input </td>
|
|
<td style="text-align: center;"> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Direct Memory Access enable (high active) </td>
|
|
</tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_priority</a> </td>
|
|
<td style="text-align: center;"> Input </td>
|
|
<td style="text-align: center;"> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Direct Memory Access priority (0:low / 1:high) </td>
|
|
</tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_ready</a> </td>
|
|
<td style="text-align: center;"> Output </td>
|
|
<td style="text-align: center;"> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Direct Memory Access is complete </td>
|
|
</tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_resp</a> </td>
|
|
<td style="text-align: center;"> Output </td>
|
|
<td style="text-align: center;"> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Direct Memory Access response (0:Okay / 1:Error) </td>
|
|
</tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_we</a> </td>
|
|
<td style="text-align: center;"> Input </td>
|
|
<td style="text-align: center;"> 2 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Direct Memory Access write byte enable (high active) </td>
|
|
</tr>
|
|
<tr>
|
|
<td> <a href="#7.%20DMA%20Interface">dma_wkup</a> </td>
|
|
<td style="text-align: center;"> Input </td>
|
|
<td style="text-align: center;"> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
</td>
|
|
<td> ASIC ONLY: DMA Wake-up (asynchronous and non-glitchy) </td>
|
|
</tr>
|
|
|
<tr> <td colspan="5" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> <a href="#7.%20Interrupts">irq</a> </td>
|
<td> <a href="#8.%20Interrupts">irq</a> </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> <small>`IRQ_NR-2</small><sup style="font-weight: bold; color: red;">1</sup></td>
|
<td style="text-align: center;"> <small>`IRQ_NR-2</small><sup style="font-weight: bold; color: red;">1</sup></td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Maskable interrupts (one-hot signal) </td>
|
<td> Maskable interrupts (one-hot signal) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#7.%20Interrupts">nmi</a> </td>
|
<td> <a href="#8.%20Interrupts">nmi</a> </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
<td> Non-maskable interrupt (asynchronous) </td>
|
<td> Non-maskable interrupt (asynchronous) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#7.%20Interrupts">irq_acc</a> </td>
|
<td> <a href="#8.%20Interrupts">irq_acc</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> <small>`IRQ_NR-2</small><sup style="font-weight: bold; color: red;">1</sup></td>
|
<td style="text-align: center;"> <small>`IRQ_NR-2</small><sup style="font-weight: bold; color: red;">1</sup></td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Interrupt request accepted (one-hot signal) </td>
|
<td> Interrupt request accepted (one-hot signal) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="5" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> <a href="#8.%20Serial%20Debug%20Interface">dbg_en</a> </td>
|
<td> <a href="#9.%20Serial%20Debug%20Interface">dbg_en</a> </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
<td> Debug interface enable (asynchronous)<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space"> </span><b><sup><font color="#ff0000">3</font></sup></b></span> </td>
|
<td> Debug interface enable (asynchronous)<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space"> </span><b><sup><font color="#ff0000">3</font></sup></b></span> </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#8.%20Serial%20Debug%20Interface">dbg_freeze</a> </td>
|
<td> <a href="#9.%20Serial%20Debug%20Interface">dbg_freeze</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Freeze peripherals </td>
|
<td> Freeze peripherals </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#8.1%20UART">dbg_uart_txd</a> </td>
|
<td> <a href="#9.1%20UART">dbg_uart_txd</a> </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> Output </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td style="vertical-align: top; text-align: center;">mclk</td>
|
<td> Debug interface: UART TXD </td>
|
<td> Debug interface: UART TXD </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> <a href="#8.1%20UART">dbg_uart_rxd</a> </td>
|
<td> <a href="#9.1%20UART">dbg_uart_rxd</a> </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> Input </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="text-align: center;"> 1 </td>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
</td>
|
</td>
|
<td> Debug interface: UART RXD (asynchronous) </td>
|
<td> Debug interface: UART RXD (asynchronous) </td>
|
</tr><tr>
|
</tr><tr>
|
<td><a href="#8.2%20I2C">dbg_i2c_addr</a></td>
|
<td><a href="#9.2%20I2C">dbg_i2c_addr</a></td>
|
<td style="text-align: center;">Input</td>
|
<td style="text-align: center;">Input</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
</td>
|
</td>
|
<td> Debug interface: I2C Address </td>
|
<td> Debug interface: I2C Address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td><a href="#8.2%20I2C">dbg_i2c_broadcast</a></td>
|
<td><a href="#9.2%20I2C">dbg_i2c_broadcast</a></td>
|
<td style="text-align: center;">Input</td>
|
<td style="text-align: center;">Input</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
</td>
|
</td>
|
<td> Debug interface: I2C Broadcast Address (for multicore only) </td>
|
<td> Debug interface: I2C Broadcast Address (for multicore only) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td><a href="#8.2%20I2C">dbg_i2c_scl</a></td>
|
<td><a href="#9.2%20I2C">dbg_i2c_scl</a></td>
|
<td style="text-align: center;">Input</td>
|
<td style="text-align: center;">Input</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="vertical-align: top; text-align: center;"><async></td>
|
<td style="vertical-align: top; text-align: center;"><async></td>
|
<td> Debug interface: I2C SCL </td>
|
<td> Debug interface: I2C SCL </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td><a href="#8.2%20I2C">dbg_i2c_sda_in</a></td>
|
<td><a href="#9.2%20I2C">dbg_i2c_sda_in</a></td>
|
<td style="text-align: center;">Input</td>
|
<td style="text-align: center;">Input</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="vertical-align: top; text-align: center;"><async></td>
|
<td style="vertical-align: top; text-align: center;"><async></td>
|
<td> Debug interface: I2C SDA input </td>
|
<td> Debug interface: I2C SDA input </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td><a href="#8.2%20I2C">dbg_i2c_sda_out</a></td>
|
<td><a href="#9.2%20I2C">dbg_i2c_sda_out</a></td>
|
<td style="text-align: center;">Output</td>
|
<td style="text-align: center;">Output</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="text-align: center;"> 1</td>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
</td>
|
</td>
|
<td> Debug interface: I2C SDA output </td>
|
<td> Debug interface: I2C SDA output </td>
|
</tr>
|
</tr>
|
<tr align="center">
|
<tr align="center">
|
<td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
|
<td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">scan_enable<br>
|
<td style="vertical-align: top;">scan_enable<br>
|
</td>
|
</td>
|
<td style="vertical-align: top; text-align: center;">Input<br>
|
<td style="vertical-align: top; text-align: center;">Input<br>
|
</td>
|
</td>
|
<td style="vertical-align: top; text-align: center;">1<br>
|
<td style="vertical-align: top; text-align: center;">1<br>
|
</td>
|
</td>
|
<td style="vertical-align: top; text-align: center;">dco_clk<br>
|
<td style="vertical-align: top; text-align: center;">dco_clk<br>
|
</td>
|
</td>
|
<td style="vertical-align: top;">ASIC ONLY: Scan enable (active during scan shifting)</td>
|
<td style="vertical-align: top;">ASIC ONLY: Scan enable (active during scan shifting)</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">scan_mode<br>
|
<td style="vertical-align: top;">scan_mode<br>
|
</td>
|
</td>
|
<td style="vertical-align: top; text-align: center;">Input<br>
|
<td style="vertical-align: top; text-align: center;">Input<br>
|
</td>
|
</td>
|
<td style="vertical-align: top; text-align: center;">1<br>
|
<td style="vertical-align: top; text-align: center;">1<br>
|
</td>
|
</td>
|
<td style="vertical-align: top; text-align: center;"><stable><br>
|
<td style="vertical-align: top; text-align: center;"><stable><br>
|
</td>
|
</td>
|
<td style="vertical-align: top;">ASIC ONLY: Scan mode</td>
|
<td style="vertical-align: top;">ASIC ONLY: Scan mode</td>
|
</tr>
|
</tr>
|
|
|
</tbody></table>
|
</tbody></table>
|
<br>
|
<br>
|
<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><b><sup><font color="#ff0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size or the number of interrupts vectors (16, 32 or 64).<br><b><sup><font color="#ff0000">2</font></sup></b>:
|
<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><b><sup><font color="#ff0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size or the number of interrupts vectors (16, 32 or 64).<br><b><sup><font color="#ff0000">2</font></sup></b>:
|
These two optional ports can be connected whenever the program memory
|
These two optional ports can be connected whenever the program memory
|
is a RAM. This will allow the user to load a program through the serial
|
is a RAM. This will allow the user to load a program through the serial
|
debug interface and to use software breakpoints.<br><b><sup><font color="#ff0000">3</font></sup></b>: When disabled, the debug interface is hold into reset (and clock gated in ASIC mode). As a consequence, the<span class="Apple-converted-space"> </span><b><i>dbg_en</i></b><span class="Apple-converted-space"> </span>port can be used to reset the debug interface without disrupting the CPU execution.<br><b><sup><font color="#ff0000">4</font></sup></b>: Clock domain is selectable through configuration in the "openMSP430_defines.v" file (see Advanced System Configuration).</span><sup></sup><br>
|
debug interface and to use software breakpoints.<br><b><sup><font color="#ff0000">3</font></sup></b>: When disabled, the debug interface is hold into reset (and clock gated in ASIC mode). As a consequence, the<span class="Apple-converted-space"> </span><b><i>dbg_en</i></b><span class="Apple-converted-space"> </span>port can be used to reset the debug interface without disrupting the CPU execution.<br><b><sup><font color="#ff0000">4</font></sup></b>: Clock domain is selectable through configuration in the "openMSP430_defines.v" file (see Advanced System Configuration).</span><sup></sup><br>
|
<br>
|
<br>
|
|
|
|
|
<a name="2. Clocks"></a>
|
<a name="2. Clocks"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>2. Clocks</h1>
|
<h1>2. Clocks</h1>
|
|
|
The different clocks in the design are managed by the Basic Clock Module as following in the FPGA configuration:
|
The different clocks in the design are managed by the Basic Clock Module as following in the FPGA configuration:
|
<br><br>
|
<br><br>
|
<img src="http://opencores.org/usercontent,img,1319831724" alt="Clock structure diagram" title="Clock structure diagram" width="75%">
|
<img src="http://opencores.org/usercontent,img,1319831724" alt="Clock structure diagram" title="Clock structure diagram" width="75%">
|
<br>
|
<br>
|
<br>
|
<br>
|
or as following in the ASIC configuration:<br>
|
or as following in the ASIC configuration:<br>
|
<br>
|
<br>
|
<img src="http://opencores.org/usercontent,img,1319832480" alt="Clock structure diagram" title="Clock structure diagram" width="75%">
|
<img src="http://opencores.org/usercontent,img,1319832480" alt="Clock structure diagram" title="Clock structure diagram" width="75%">
|
<br>
|
<br>
|
<ul>
|
<ul>
|
<li>
|
<li>
|
<b><font color="#0000b0">CPU_EN</font></b>: this input port provides a hardware mean to stop or resume CPU execution. When unused, this port should be set to 1.
|
<b><font color="#0000b0">CPU_EN</font></b>: this input port provides a hardware mean to stop or resume CPU execution. When unused, this port should be set to 1.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#0000b0">DCO_CLK</font></b>: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA/ASIC might provide.<br>For the FPGA configuration, from a synthesis tool perspective (ISE, Quartus, Libero, Design
|
<b><font color="#0000b0">DCO_CLK</font></b>: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA/ASIC might provide.<br>For the FPGA configuration, from a synthesis tool perspective (ISE, Quartus, Libero, Design
|
Compiler...), this the only port where a clock needs to be declared. <br><br>
|
Compiler...), this the only port where a clock needs to be declared. <br><br>
|
</li>
|
</li>
|
|
|
<li>
|
<li>
|
<b><font color="#0000b0">LFXT_CLK</font></b>:
|
<b><font color="#0000b0">LFXT_CLK</font></b>:
|
in an FPGA system, if ACLK_EN or SMCLK_EN are going to be used in the project (for example
|
in an FPGA system, if ACLK_EN or SMCLK_EN are going to be used in the project (for example
|
through the Watchdog or TimerA peripherals), then this port needs to be
|
through the Watchdog or TimerA peripherals), then this port needs to be
|
connected to a clock running at least two time slower as DCO_CLK
|
connected to a clock running at least two time slower as DCO_CLK
|
(typically 32kHz). It can be connected to 0 or 1 otherwise.<br>
|
(typically 32kHz). It can be connected to 0 or 1 otherwise.<br>
|
|
|
In an ASIC, if ACLK or SMCLK are used and if the clock muxes are
|
In an ASIC, if ACLK or SMCLK are used and if the clock muxes are
|
included, then this port can be connected to any kind of clock source
|
included, then this port can be connected to any kind of clock source
|
(it doesn't need to be low-frequency. The name was just
|
(it doesn't need to be low-frequency. The name was just
|
kept to be consistent with TI's documentation).<br><br>
|
kept to be consistent with TI's documentation).<br><br>
|
</li>
|
</li>
|
|
|
<li>
|
<li>
|
<b><font color="#00b000">MCLK</font></b>:
|
<b><font color="#00b000">MCLK</font></b>:
|
the main system clock drives the complete openMSP430 clock domain,
|
the main system clock drives the complete openMSP430 clock domain,
|
including program/data memories and the peripheral interfaces. <br><br>
|
including program/data memories and the peripheral interfaces. <br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">ACLK_EN / SMCLK_EN</font></b>:
|
<b><font color="#00b000">ACLK_EN / SMCLK_EN</font></b>:
|
these two clock enable signals can be used in order to emulate the
|
these two clock enable signals can be used in order to emulate the
|
original ACLK and SMCLK from the MSP430 specification when the core is
|
original ACLK and SMCLK from the MSP430 specification when the core is
|
targeting an FPGA.<br>
|
targeting an FPGA.<br>
|
An example of this can be found in the Watchdog and TimerA modules, where it is implemented as following:<br><br>
|
An example of this can be found in the Watchdog and TimerA modules, where it is implemented as following:<br><br>
|
<img src="http://opencores.org/usercontent,img,1246434793" alt="Clock implementation example" title="Clock implementation example"><br>
|
<img src="http://opencores.org/usercontent,img,1246434793" alt="Clock implementation example" title="Clock implementation example"><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
<ul>
|
<ul>
|
<li>
|
<li>
|
<b><font color="#00b000">ACLK / SMCLK</font></b>: ACLK and MCLK are available through these two ports when targeting an ASIC.<br> </li>
|
<b><font color="#00b000">ACLK / SMCLK</font></b>: ACLK and MCLK are available through these two ports when targeting an ASIC.<br> </li>
|
<li>
|
<li>
|
<b><font color="#00b000">DCO_ENABLE / DCO_WKUP</font></b>: ASIC specific signals controlling the fast clock generator for low power mode support (SCG0 bit in the status register).<br><br></li>
|
<b><font color="#00b000">DCO_ENABLE / DCO_WKUP</font></b>: ASIC specific signals controlling the fast clock generator for low power mode support (SCG0 bit in the status register).<br><br></li>
|
<li>
|
<li>
|
<b><font color="#00b000">LFXT_ENABLE / LFXT_WKUP</font></b>:
|
<b><font color="#00b000">LFXT_ENABLE / LFXT_WKUP</font></b>:
|
ASIC specific signals controlling the low frequency clock generator for
|
ASIC specific signals controlling the low frequency clock generator for
|
low power mode support (OSCOFF bit in the status register).<br> </li>
|
low power mode support (OSCOFF bit in the status register).<br> </li>
|
<li><b><font color="#0000b0">WKUP</font></b>:
|
<li><b><font color="#0000b0">WKUP</font></b>:
|
When activated, this signal allows a peripheral to restore all CPU
|
When activated, this signal allows a peripheral to restore all CPU
|
clocks (i.e. wakeup the cpu) prior IRQ generation. Note that IRQs
|
clocks (i.e. wakeup the cpu) prior IRQ generation. Note that IRQs
|
MUST always be generated from the MCLK clock domain. </li>
|
MUST always be generated from the MCLK clock domain. </li>
|
</ul>
|
</ul>
|
|
|
As an FPGA system illustration, the following waveform shows the different
|
As an FPGA system illustration, the following waveform shows the different
|
clocks where the software running on the openMSP430 configures the
|
clocks where the software running on the openMSP430 configures the
|
BCSCTL1 and BCSCTL2 registers so that <i>ACLK_EN</i> and <i>SMCLK_EN</i> are respectively running at <i>LFXT_CLK/2</i> and <i>DCO_CLK/4</i>.<br><br>
|
BCSCTL1 and BCSCTL2 registers so that <i>ACLK_EN</i> and <i>SMCLK_EN</i> are respectively running at <i>LFXT_CLK/2</i> and <i>DCO_CLK/4</i>.<br><br>
|
<img src="http://opencores.org/usercontent,img,1263320613" alt="Waveforms: Clocks - Jan 12. 2010" title="Waveforms: Clocks - Jan 12. 2010" width="100%">
|
<img src="http://opencores.org/usercontent,img,1263320613" alt="Waveforms: Clocks - Jan 12. 2010" title="Waveforms: Clocks - Jan 12. 2010" width="100%">
|
<br><br>
|
<br><br>
|
|
|
<a name="3. Resets"></a>
|
<a name="3. Resets"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>3. Resets</h1>
|
<h1>3. Resets</h1>
|
|
|
<ul>
|
<ul>
|
<li><b><font color="#0000b0">RESET_N</font></b>: this input port is typically connected to a board push button and is generally combined with the system power-on-reset.
|
<li><b><font color="#0000b0">RESET_N</font></b>: this input port is typically connected to a board push button and is generally combined with the system power-on-reset.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">PUC_RST</font></b>: the Power-Up-Clear signal is asynchronously set with the reset pin (<i>RESET_N</i>),
|
<b><font color="#00b000">PUC_RST</font></b>: the Power-Up-Clear signal is asynchronously set with the reset pin (<i>RESET_N</i>),
|
the watchdog reset or the serial debug interface reset. In order to get
|
the watchdog reset or the serial debug interface reset. In order to get
|
clean timings, it is synchronously cleared with MCLK. As
|
clean timings, it is synchronously cleared with MCLK. As
|
a general rule, this signal should be used as the reset of the <i>MCLK</i> clock domain.
|
a general rule, this signal should be used as the reset of the <i>MCLK</i> clock domain.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
The following waveform illustrates this:<br><br>
|
The following waveform illustrates this:<br><br>
|
<img src="http://opencores.org/usercontent,img,1263320655" alt="Waveforms: Resets - Jan 12. 2010" title="Waveforms: Resets - Jan 12. 2010" width="100%">
|
<img src="http://opencores.org/usercontent,img,1263320655" alt="Waveforms: Resets - Jan 12. 2010" title="Waveforms: Resets - Jan 12. 2010" width="100%">
|
<br><br>
|
<br><br>
|
|
|
<a name="4. Program Memory"></a>
|
<a name="4. Program Memory"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>4. Program Memory</h1>
|
<h1>4. Program Memory</h1>
|
|
|
Depending on the project needs, the program memory can be either implemented as a ROM or RAM.<br>
|
Depending on the project needs, the program memory can be either implemented as a ROM or RAM.<br>
|
<br>
|
<br>
|
If a ROM is selected then the <i>PMEM_DIN</i> and <i>PMEM_WEN</i>
|
If a ROM is selected then the <i>PMEM_DIN</i> and <i>PMEM_WEN</i>
|
ports won't be connected. In that case, the software debug capabilities
|
ports won't be connected. In that case, the software debug capabilities
|
are limited because the serial debug interface can only use hardware
|
are limited because the serial debug interface can only use hardware
|
breakpoints in order to stop the program execution. In addition,
|
breakpoints in order to stop the program execution. In addition,
|
updating the software will require a reprogramming of the FPGA... or a new ROM mask for an ASIC.<br>
|
updating the software will require a reprogramming of the FPGA... or a new ROM mask for an ASIC.<br>
|
<br>
|
<br>
|
If the program memory is a RAM, the developer gets full flexibility
|
If the program memory is a RAM, the developer gets full flexibility
|
regarding software debugging. The serial debug interface can be used to
|
regarding software debugging. The serial debug interface can be used to
|
update the program memory and software breakpoints can be used.<br>
|
update the program memory and software breakpoints can be used.<br>
|
<br><br>
|
<br><br>
|
That said, the protocol between the openMSP430 and the program memory is quite standard. Signal description goes as following:
|
That said, the protocol between the openMSP430 and the program memory is quite standard. Signal description goes as following:
|
<ul>
|
<ul>
|
<li><b><font color="#00b000">PMEM_CEN</font></b>: when this signal is active, the read/write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is LOW ACTIVE.
|
<li><b><font color="#00b000">PMEM_CEN</font></b>: when this signal is active, the read/write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is LOW ACTIVE.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">PMEM_ADDR</font></b>: Memory address of the 16 bit word which is going to be accessed.<br>
|
<b><font color="#00b000">PMEM_ADDR</font></b>: Memory address of the 16 bit word which is going to be accessed.<br>
|
<b>Note:</b> in order to calculate the core logical address from the program memory physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@+0x10000-PMEM_SIZE</i>
|
<b>Note:</b> in order to calculate the core logical address from the program memory physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@+0x10000-PMEM_SIZE</i>
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#0000b0">PMEM_DOUT</font></b>: the memory output word will be updated with every valid read/write access (i.e. <i>PMEM_DOUT</i> is not updated if <i>PMEM_CEN</i>=1).
|
<b><font color="#0000b0">PMEM_DOUT</font></b>: the memory output word will be updated with every valid read/write access (i.e. <i>PMEM_DOUT</i> is not updated if <i>PMEM_CEN</i>=1).
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">PMEM_WEN</font></b>:
|
<b><font color="#00b000">PMEM_WEN</font></b>:
|
this signal selects which byte should be written during a valid access.
|
this signal selects which byte should be written during a valid access.
|
PMEM_WEN[0] will activate a write on the lower byte, PMEM_WEN[1] a
|
PMEM_WEN[0] will activate a write on the lower byte, PMEM_WEN[1] a
|
write on the upper byte. Note that these signals are LOW ACTIVE. <br><br>
|
write on the upper byte. Note that these signals are LOW ACTIVE. <br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">PMEM_DIN</font></b>: the memory input word will be written with the valid write access according to the <i>PMEM_WEN</i> value.
|
<b><font color="#00b000">PMEM_DIN</font></b>: the memory input word will be written with the valid write access according to the <i>PMEM_WEN</i> value.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
The following waveform illustrates some read accesses of the program
|
The following waveform illustrates some read accesses of the program
|
memory (write access are illustrated in the data memory section):<br><br>
|
memory (write access are illustrated in the data memory section):<br><br>
|
<img src="http://opencores.org/usercontent,img,1263320706" alt="Waveforms: Program memory - Jan " title="Waveforms: Program memory - Jan " width="100%">
|
<img src="http://opencores.org/usercontent,img,1263320706" alt="Waveforms: Program memory - Jan " title="Waveforms: Program memory - Jan " width="100%">
|
<br><br>
|
<br><br>
|
<a name="5. Data Memory"></a>
|
<a name="5. Data Memory"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>5. Data Memory</h1>
|
<h1>5. Data Memory</h1>
|
|
|
The data memory is always implemented as a RAM.<br>
|
The data memory is always implemented as a RAM.<br>
|
<br>
|
<br>
|
The protocol between the openMSP430 and the data memory is the same as
|
The protocol between the openMSP430 and the data memory is the same as
|
the one of the program memory. Therefore, the signal description is the
|
the one of the program memory. Therefore, the signal description is the
|
same:
|
same:
|
<ul>
|
<ul>
|
<li><b><font color="#00b000">DMEM_CEN</font></b>: when this signal is active, the read/write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is LOW ACTIVE.
|
<li><b><font color="#00b000">DMEM_CEN</font></b>: when this signal is active, the read/write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is LOW ACTIVE.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">DMEM_ADDR</font></b>: Memory address of the 16 bit word which is going to be accessed.<br>
|
<b><font color="#00b000">DMEM_ADDR</font></b>: Memory address of the 16 bit word which is going to be accessed.<br>
|
<b>Note:</b> in order to calculate the core logical address from the data memory physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@+0x200</i>
|
<b>Note:</b> in order to calculate the core logical address from the data memory physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@+0x200</i>
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#0000b0">DMEM_DOUT</font></b>: the memory output word will be updated with every valid read/write access (i.e. <i>DMEM_DOUT</i> is not updated if <i>DMEM_CEN</i>=1).
|
<b><font color="#0000b0">DMEM_DOUT</font></b>: the memory output word will be updated with every valid read/write access (i.e. <i>DMEM_DOUT</i> is not updated if <i>DMEM_CEN</i>=1).
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">DMEM_WEN</font></b>:
|
<b><font color="#00b000">DMEM_WEN</font></b>:
|
this signal selects which byte should be written during a valid access.
|
this signal selects which byte should be written during a valid access.
|
DMEM_WEN[0] will activate a write on the lower byte, DMEM_WEN[1] a
|
DMEM_WEN[0] will activate a write on the lower byte, DMEM_WEN[1] a
|
write on the upper byte. Note that these signals are LOW ACTIVE. <br><br>
|
write on the upper byte. Note that these signals are LOW ACTIVE. <br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">DMEM_DIN</font></b>: the memory input word will be written with the valid write access according to the <i>DMEM_WEN</i> value.
|
<b><font color="#00b000">DMEM_DIN</font></b>: the memory input word will be written with the valid write access according to the <i>DMEM_WEN</i> value.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
The following waveform illustrates some read/write access to the data memory:<br><br>
|
The following waveform illustrates some read/write access to the data memory:<br><br>
|
<img src="http://opencores.org/usercontent,img,1263320770" alt="Waveforms: Data memory - Jan 12." title="Waveforms: Data memory - Jan 12." width="100%">
|
<img src="http://opencores.org/usercontent,img,1263320770" alt="Waveforms: Data memory - Jan 12." title="Waveforms: Data memory - Jan 12." width="100%">
|
<br><br>
|
<br><br>
|
|
|
<a name="6. Peripherals"></a>
|
<a name="6. Peripherals"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>6. Peripherals</h1>
|
<h1>6. Peripherals</h1>
|
The protocol between the openMSP430 core and its peripherals is the
|
The protocol between the openMSP430 core and its peripherals is the
|
exactly same as the one with the data and program memories in regard
|
exactly same as the one with the data and program memories in regard
|
to write access and differs slightly for read access.<br>
|
to write access and differs slightly for read access.<br>
|
<br>
|
<br>
|
On the connectivity side, the specificity is that the read data bus of
|
On the connectivity side, the specificity is that the read data bus of
|
all peripherals should be ORed together before being connected to the
|
all peripherals should be ORed together before being connected to the
|
core, as showed in the diagram of the <a href="#1.%20Overview">Overview</a> section.<br>
|
core, as showed in the diagram of the <a href="#1.%20Overview">Overview</a> section.<br>
|
From the logical point of view, during a read access, each peripheral
|
From the logical point of view, during a read access, each peripheral
|
outputs the combinatorial value of its read mux and returns 0 if it
|
outputs the combinatorial value of its read mux and returns 0 if it
|
doesn't contain the addressed register. On the waveforms, this
|
doesn't contain the addressed register. On the waveforms, this
|
translates by seeing the register value on <i>PER_DOUT</i> while <i>PER_EN</i> is valid and not one clock cycle afterward as it is the case with the program and data memories.<br>
|
translates by seeing the register value on <i>PER_DOUT</i> while <i>PER_EN</i> is valid and not one clock cycle afterward as it is the case with the program and data memories.<br>
|
In any case, it is recommended to use the templates provided with the core in order to develop your own custom peripherals.<br>
|
In any case, it is recommended to use the templates provided with the core in order to develop your own custom peripherals.<br>
|
The signal description therefore goes as following:
|
The signal description therefore goes as following:
|
<ul>
|
<ul>
|
<li><b><font color="#00b000">PER_EN</font></b>: when this signal is active, read access are executed during the current <i>MCLK</i> cycle while write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is HIGH ACTIVE.
|
<li><b><font color="#00b000">PER_EN</font></b>: when this signal is active, read access are executed during the current <i>MCLK</i> cycle while write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is HIGH ACTIVE.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">PER_ADDR</font></b>:
|
<b><font color="#00b000">PER_ADDR</font></b>:
|
peripheral register address of the 16 bit word which is currently
|
peripheral register address of the 16 bit word which is currently
|
accessed. It is to be noted that a 14 bit address will always be
|
accessed. It is to be noted that a 14 bit address will always be
|
provided from the openMSP430 to the peripheral in order to accommodate
|
provided from the openMSP430 to the peripheral in order to accommodate
|
the biggest possible PER_SIZE Verilog configuration option (i.e. 32kB
|
the biggest possible PER_SIZE Verilog configuration option (i.e. 32kB
|
as opposed to 512B by default).<br>
|
as opposed to 512B by default).<br>
|
<b>Note:</b> in order to calculate the core logical address from the peripheral register physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@</i>
|
<b>Note:</b> in order to calculate the core logical address from the peripheral register physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@</i>
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#0000b0">PER_DOUT</font></b>: the peripheral output word will be updated with every valid read/write access, it will be set to 0 otherwise.
|
<b><font color="#0000b0">PER_DOUT</font></b>: the peripheral output word will be updated with every valid read/write access, it will be set to 0 otherwise.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">PER_WE</font></b>:
|
<b><font color="#00b000">PER_WE</font></b>:
|
this signal selects which byte should be written during a valid access.
|
this signal selects which byte should be written during a valid access.
|
PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on
|
PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on
|
the upper byte. Note that these signals are HIGH ACTIVE. <br><br>
|
the upper byte. Note that these signals are HIGH ACTIVE. <br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">PER_DIN</font></b>: the peripheral input word will be written with the valid write access according to the <i>PER_WEN</i> value.
|
<b><font color="#00b000">PER_DIN</font></b>: the peripheral input word will be written with the valid write access according to the <i>PER_WEN</i> value.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
The following waveform illustrates some read/write access to the peripheral registers:<br><br>
|
The following waveform illustrates some read/write access to the peripheral registers:<br><br>
|
<img src="http://opencores.org/usercontent,img,1263320825" alt="Waveforms: Peripherals - Jan 12." title="Waveforms: Peripherals - Jan 12." width="100%">
|
<img src="http://opencores.org/usercontent,img,1263320825" alt="Waveforms: Peripherals - Jan 12." title="Waveforms: Peripherals - Jan 12." width="100%">
|
<br><br>
|
<br><br>
|
|
|
|
<a name="7. DMA Interface"></a>
|
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
|
<h1>7. Direct Memory Access Interface</h1>
|
|
|
|
Before moving on, please note that further details about the DMA interface can
|
|
be found in its <a href="http://opencores.org/project,openmsp430,dma%20interface">dedicated section</a>.<br>
|
|
<br>
|
|
The protocol between the DMA interface master (DMA controller, bootloader, ...) and the openMSP430 core is similar
|
|
to the one followed between the openMSP430 and its data memory.
|
|
<br> However, it comes with a few additional features to support wait states, error response, priority and wakeup (for LPMx modes).<br>
|
|
<br>
|
|
The signal description goes as following:
|
|
<ul>
|
|
<li><b><font color="#0000b0">DMA_EN</font></b>:
|
|
this signal enables a DMA transfer and can be released once the transfer is completed, as signaled by DMA_READY.
|
|
<br><br>
|
|
</li>
|
|
<li>
|
|
<b><font color="#0000b0">DMA_ADDR</font></b>:
|
|
Logical address of the 16bit word currently accessed by the interface. The address must stay valid until the transfer is completed, as signaled by DMA_READY.
|
|
<br><b>Note:</b> the integrated oMSP memory backbone module decode the specified <b>logical</b> DMA address and maps it accordingly to the <b>physical</b> address of the Program, Data or Peripheral memory.
|
|
<br><br>
|
|
</li>
|
|
<li>
|
|
<b><font color="#00b000">DMA_DOUT</font></b>:
|
|
When performing a read acces, the DMA data output is valid during the MCLK cycle immediately following the end of the transfer, as signaled by DMA_READY.
|
|
<br><br>
|
|
</li>
|
|
<li>
|
|
<b><font color="#0000b0">DMA_WE</font></b>:
|
|
This signal, asserted together with DMA_EN, allows to selects which byte should be written during the transfer.
|
|
DMA_WE[0] activates a write on the lower byte, DMA_WE[1] a write on the upper byte.<br><br>
|
|
</li>
|
|
<li>
|
|
<b><font color="#0000b0">DMA_DIN</font></b>:
|
|
When performing a write access, the DMA data input must stay valid until the transfer is completed, as signaled by DMA ready.
|
|
<br><br>
|
|
</li>
|
|
<li>
|
|
<b><font color="#0000b0">DMA_PRIORITY</font></b>:
|
|
When <b>SET</b>, the oMSP memory backbone gives highest priority to the DMA transfer and stops CPU execution.
|
|
<br>When <b>CLEARED</b>, the oMSP memory backbone gives highest priority to CPU execution and the DMA transfer is completed only when the CPU doesn't access the targeted ressource (pmem, dmem or peripheral).
|
|
<br><b>Note</b>: a DMA controller can control the DMA data rate without stalling the CPU by dynamically asserting/deasserting the DMA_PRIORITY port between transfers.
|
|
<br><br>
|
|
</li>
|
|
<li>
|
|
<b><font color="#00b000">DMA_READY</font></b>:
|
|
This port signals that the current DMA transfer is completed.
|
|
<br><b>Note</b>: DMA_READY is typically hold low when the CPU owns the interface of the target ressource.
|
|
<br><br>
|
|
</li>
|
|
<li>
|
|
<b><font color="#00b000">DMA_RESP</font></b>:
|
|
This port signals if the current transfer was successful (0) or if an error occured (1) and is valid together with DMA_READY.
|
|
<br><b>Note</b>: an error is typically signaled when an access is performed outside of any memory mapped area (for example between Program and Data memory).
|
|
<br><br>
|
|
</li>
|
|
<li>
|
|
<b><font color="#0000b0">DMA_WKUP</font></b>:
|
|
For ASIC implementations supporting the Low-Power-Modes, this port is used to asynchronously restore the clocks before performing a DMA transfer.
|
|
<br><b>Note</b>: it is possible to control which clocks are restored during a DMA wakeup using the <b>BCSTL1</b> register of the Basic Clock Module.
|
|
<br><br>
|
|
</li>
|
|
</ul>
|
|
The following waveform illustrates some read/write access using the DMA interface:<br><br>
|
|
<img src="http://opencores.org/usercontent,img,1431293399" alt="Waveforms: DMA transfer" title="Waveforms: DMA transfer" width="100%">
|
|
<br><br>
|
|
|
|
|
<a name="7. Interrupts"></a>
|
<a name="8. Interrupts"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>7. Interrupts</h1> As with the original MSP430, the interrupt
|
<h1>8. Interrupts</h1> As with the original MSP430, the interrupt
|
priorities of the openMSP430 are fixed in hardware accordingly to the
|
priorities of the openMSP430 are fixed in hardware accordingly to the
|
connectivity of the <i>NMI</i> and <i>IRQ</i> ports.<br>
|
connectivity of the <i>NMI</i> and <i>IRQ</i> ports.<br>
|
If two interrupts are pending simultaneously, the higher priority interrupt will be serviced first.<br>
|
If two interrupts are pending simultaneously, the higher priority interrupt will be serviced first.<br>
|
The following table summarize this:<br><br>
|
The following table summarize this:<br><br>
|
<table border="1">
|
<table border="1">
|
<tbody><tr>
|
<tbody><tr>
|
<td align="center"><b> Interrupt Port </b></td>
|
<td align="center"><b> Interrupt Port </b></td>
|
<td align="center"><b> Vector address </b></td>
|
<td align="center"><b> Vector address </b></td>
|
<td align="center"><b> Priority </b></td>
|
<td align="center"><b> Priority </b></td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">RESET_N</td>
|
<td align="center">RESET_N</td>
|
<td align="center">0xFFFE</td>
|
<td align="center">0xFFFE</td>
|
<td align="center">15 (highest)</td>
|
<td align="center">15 (highest)</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">NMI</td>
|
<td align="center">NMI</td>
|
<td align="center">0xFFFC</td>
|
<td align="center">0xFFFC</td>
|
<td align="center">14</td>
|
<td align="center">14</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[13]</td>
|
<td align="center">IRQ[13]</td>
|
<td align="center">0xFFFA</td>
|
<td align="center">0xFFFA</td>
|
<td align="center">13</td>
|
<td align="center">13</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[12]</td>
|
<td align="center">IRQ[12]</td>
|
<td align="center">0xFFF8</td>
|
<td align="center">0xFFF8</td>
|
<td align="center">12</td>
|
<td align="center">12</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[11]</td>
|
<td align="center">IRQ[11]</td>
|
<td align="center">0xFFF6</td>
|
<td align="center">0xFFF6</td>
|
<td align="center">11</td>
|
<td align="center">11</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[10]</td>
|
<td align="center">IRQ[10]</td>
|
<td align="center">0xFFF4</td>
|
<td align="center">0xFFF4</td>
|
<td align="center">10</td>
|
<td align="center">10</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[9]</td>
|
<td align="center">IRQ[9]</td>
|
<td align="center">0xFFF2</td>
|
<td align="center">0xFFF2</td>
|
<td align="center">9</td>
|
<td align="center">9</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[8]</td>
|
<td align="center">IRQ[8]</td>
|
<td align="center">0xFFF0</td>
|
<td align="center">0xFFF0</td>
|
<td align="center">8</td>
|
<td align="center">8</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[7]</td>
|
<td align="center">IRQ[7]</td>
|
<td align="center">0xFFEE</td>
|
<td align="center">0xFFEE</td>
|
<td align="center">7</td>
|
<td align="center">7</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[6]</td>
|
<td align="center">IRQ[6]</td>
|
<td align="center">0xFFEC</td>
|
<td align="center">0xFFEC</td>
|
<td align="center">6</td>
|
<td align="center">6</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[5]</td>
|
<td align="center">IRQ[5]</td>
|
<td align="center">0xFFEA</td>
|
<td align="center">0xFFEA</td>
|
<td align="center">5</td>
|
<td align="center">5</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[4]</td>
|
<td align="center">IRQ[4]</td>
|
<td align="center">0xFFE8</td>
|
<td align="center">0xFFE8</td>
|
<td align="center">4</td>
|
<td align="center">4</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[3]</td>
|
<td align="center">IRQ[3]</td>
|
<td align="center">0xFFE6</td>
|
<td align="center">0xFFE6</td>
|
<td align="center">3</td>
|
<td align="center">3</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[2]</td>
|
<td align="center">IRQ[2]</td>
|
<td align="center">0xFFE4</td>
|
<td align="center">0xFFE4</td>
|
<td align="center">2</td>
|
<td align="center">2</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[1]</td>
|
<td align="center">IRQ[1]</td>
|
<td align="center">0xFFE2</td>
|
<td align="center">0xFFE2</td>
|
<td align="center">1</td>
|
<td align="center">1</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td align="center">IRQ[0]</td>
|
<td align="center">IRQ[0]</td>
|
<td align="center">0xFFE0</td>
|
<td align="center">0xFFE0</td>
|
<td align="center">0 (lowest)</td>
|
<td align="center">0 (lowest)</td>
|
</tr>
|
</tr>
|
</tbody></table>
|
</tbody></table>
|
<br><br>
|
<br><br>
|
The signal description goes as following:
|
The signal description goes as following:
|
<ul>
|
<ul>
|
<li>
|
<li>
|
<b><font color="#0000b0">NMI</font></b>: The <b>N</b>on-<b>M</b>askable <b>I</b>nterrupt has higher priority than other IRQs and is masked by the NMIIE bit instead of GIE.<br>
|
<b><font color="#0000b0">NMI</font></b>: The <b>N</b>on-<b>M</b>askable <b>I</b>nterrupt has higher priority than other IRQs and is masked by the NMIIE bit instead of GIE.<br>
|
It is internally synchronized to the <i>MCLK</i>
|
It is internally synchronized to the <i>MCLK</i>
|
domain and can therefore be connected to any asynchronous signal of the
|
domain and can therefore be connected to any asynchronous signal of the
|
chip (which could for example be a pin of the FPGA). If unused, this
|
chip (which could for example be a pin of the FPGA). If unused, this
|
signal should be connected to 0. <br><br>
|
signal should be connected to 0. <br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#0000b0">IRQ</font></b>: The standard interrupts can be connected to any signal coming from the <i>MCLK</i> domain (typically a peripheral). Priorities can be chosen by selecting the proper bit of the <i>IRQ</i> bus as shown in the table above. Unused interrupts should be connected to 0.<br>
|
<b><font color="#0000b0">IRQ</font></b>: The standard interrupts can be connected to any signal coming from the <i>MCLK</i> domain (typically a peripheral). Priorities can be chosen by selecting the proper bit of the <i>IRQ</i> bus as shown in the table above. Unused interrupts should be connected to 0.<br>
|
<b>Note</b>: <i>IRQ[10]</i> is internally connected to the Watchdog
|
<b>Note</b>: <i>IRQ[10]</i> is internally connected to the Watchdog
|
interrupt. If this bit is also used by an external peripheral, they
|
interrupt. If this bit is also used by an external peripheral, they
|
will both share the same interrupt vector. <br><br>
|
will both share the same interrupt vector. <br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">IRQ_ACC</font></b>:
|
<b><font color="#00b000">IRQ_ACC</font></b>:
|
Whenever an interrupt request is serviced, some peripheral
|
Whenever an interrupt request is serviced, some peripheral
|
automatically clear their pending flag in hardware. In order to do so,
|
automatically clear their pending flag in hardware. In order to do so,
|
the <i>IRQ_ACC</i> bus can be used by using the bit matching the corresponding <i>IRQ</i> bit. An example of this is shown in the implementation of the TACCR0 Timer A interrupt.
|
the <i>IRQ_ACC</i> bus can be used by using the bit matching the corresponding <i>IRQ</i> bit. An example of this is shown in the implementation of the TACCR0 Timer A interrupt.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
The following waveform illustrates a TAIV interrupt issued by the Timer-A, which is connected to <i>IRQ[8]</i> :<br><br>
|
The following waveform illustrates a TAIV interrupt issued by the Timer-A, which is connected to <i>IRQ[8]</i> :<br><br>
|
<img src="http://opencores.org/usercontent,img,1263320861" alt="Waveforms: Interrupts - Jan 12. " title="Waveforms: Interrupts - Jan 12. " width="100%">
|
<img src="http://opencores.org/usercontent,img,1263320861" alt="Waveforms: Interrupts - Jan 12. " title="Waveforms: Interrupts - Jan 12. " width="100%">
|
|
|
<br><br>
|
<br><br>
|
|
|
|
|
<a name="8. Serial Debug Interface"></a>
|
<a name="9. Serial Debug Interface"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>8. Serial Debug Interface</h1>
|
<h1>9. Serial Debug Interface</h1>
|
The serial debug interface module provides a two-wires communication
|
The serial debug interface module provides a two-wires communication
|
bus (UART or I2C) for remote debugging and an additional freeze signal which might be
|
bus (UART or I2C) for remote debugging and an additional freeze signal which might be
|
useful for some peripherals (typically timers).<br>
|
useful for some peripherals (typically timers).<br>
|
<br>
|
<br>
|
<ul>
|
<ul>
|
<li>
|
<li>
|
<b><font color="#0000b0">DBG_EN</font></b>: this signal
|
<b><font color="#0000b0">DBG_EN</font></b>: this signal
|
allows the user to enable or disable the serial debug interface without
|
allows the user to enable or disable the serial debug interface without
|
interfering with the CPU execution. It is to be noted that when
|
interfering with the CPU execution. It is to be noted that when
|
disabled (i.e. DBG_EN=0), the debug interface is held into reset. <br><br>
|
disabled (i.e. DBG_EN=0), the debug interface is held into reset. <br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">DBG_FREEZE</font></b>: this signal will be set whenever the debug interface stops the CPU (and if the <i>FRZ_BRK_EN</i> field of the <a href="http://www.opencores.org/project,openmsp430,serial%20debug%20interface#2.2.2%20CPU_CTL">CPU_CTL</a> debug register is set). As its name implies, the purpose of <i>DBG_FREEZE</i> is to freeze a peripheral whenever the CPU is stopped by the software debugger.<br>
|
<b><font color="#00b000">DBG_FREEZE</font></b>: this signal will be set whenever the debug interface stops the CPU (and if the <i>FRZ_BRK_EN</i> field of the <a href="http://www.opencores.org/project,openmsp430,serial%20debug%20interface#2.2.2%20CPU_CTL">CPU_CTL</a> debug register is set). As its name implies, the purpose of <i>DBG_FREEZE</i> is to freeze a peripheral whenever the CPU is stopped by the software debugger.<br>
|
For example, it is used by the Watchdog timer in order to stop its
|
For example, it is used by the Watchdog timer in order to stop its
|
free-running counter. This prevents the CPU from being reseted by the
|
free-running counter. This prevents the CPU from being reseted by the
|
watchdog every times the user stops the CPU during a debugging session.
|
watchdog every times the user stops the CPU during a debugging session.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
<a name="8.1 UART"></a>
|
<a name="9.1 UART"></a>
|
<h2>8.1 UART Configuration</h2>
|
<h2>9.1 UART Configuration</h2>
|
<ul>
|
<ul>
|
<li>
|
<li>
|
<b><font color="#00b000">DBG_UART_TXD</font> / <font color="#0000b0">DBG_UART_RXD</font></b>: these signals are typically connected to an RS-232 transceiver and will allow a PC to communicate with the openMSP430 core.
|
<b><font color="#00b000">DBG_UART_TXD</font> / <font color="#0000b0">DBG_UART_RXD</font></b>: these signals are typically connected to an RS-232 transceiver and will allow a PC to communicate with the openMSP430 core.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
The following waveform shows some communication traffic on the UART serial bus :<br><br>
|
The following waveform shows some communication traffic on the UART serial bus :<br><br>
|
<img src="http://opencores.org/usercontent,img,1263320887" alt="Waveforms: SDI - Jan 12. 2010" title="Waveforms: SDI - Jan 12. 2010" width="100%">
|
<img src="http://opencores.org/usercontent,img,1263320887" alt="Waveforms: SDI - Jan 12. 2010" title="Waveforms: SDI - Jan 12. 2010" width="100%">
|
<br><br>
|
<br><br>
|
<a name="8.2 I2C"></a>
|
<a name="9.2 I2C"></a>
|
<h2>8.2 I2C Configuration</h2>
|
<h2>9.2 I2C Configuration</h2>
|
<ul>
|
<ul>
|
<li>
|
<li>
|
<b><font color="#0000b0">DBG_I2C_ADDR</font></b>: I2C Device address of the oMSP core (between 8 and 119). In a multi-core configuration each core has its own address.
|
<b><font color="#0000b0">DBG_I2C_ADDR</font></b>: I2C Device address of the oMSP core (between 8 and 119). In a multi-core configuration each core has its own address.
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#0000b0">DBG_I2C_BROADCAST</font></b>:
|
<b><font color="#0000b0">DBG_I2C_BROADCAST</font></b>:
|
I2C Device broadcast address of the oMSP core (between 8 and 119). In a
|
I2C Device broadcast address of the oMSP core (between 8 and 119). In a
|
multi-core configuration all cores have the same broadcast address. <br><br>
|
multi-core configuration all cores have the same broadcast address. <br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#0000b0">DBG_I2C_SCL</font></b>: I2C bus clock input (SCL).
|
<b><font color="#0000b0">DBG_I2C_SCL</font></b>: I2C bus clock input (SCL).
|
<br><br>
|
<br><br>
|
</li>
|
</li>
|
<li>
|
<li>
|
<b><font color="#00b000">DBG_I2C_SDA_OUT</font> / <font color="#0000b0">DBG_I2C_SDA_IN</font></b>: these signals are connected to the SDA I/O cell as following:<br><br>
|
<b><font color="#00b000">DBG_I2C_SDA_OUT</font> / <font color="#0000b0">DBG_I2C_SDA_IN</font></b>: these signals are connected to the SDA I/O cell as following:<br><br>
|
<div style="text-align: center;"><img src="http://opencores.org/usercontent,img,1353268717" alt="I2C SDA IO Connect" title="I2C SDA IO Connect" width="50%">
|
<div style="text-align: center;"><img src="http://opencores.org/usercontent,img,1353268717" alt="I2C SDA IO Connect" title="I2C SDA IO Connect" width="50%">
|
<br>
|
<br>
|
</div>
|
</div>
|
<br>
|
<br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
|
|
The following waveform shows some communication traffic on the I2C serial bus :<br><br>
|
The following waveform shows some communication traffic on the I2C serial bus :<br><br>
|
<img src="http://opencores.org/usercontent,img,1353272928" alt="Waveforms: SDI I2C" title="Waveforms: SDI I2C" width="100%">
|
<img src="http://opencores.org/usercontent,img,1353272928" alt="Waveforms: SDI I2C" title="Waveforms: SDI I2C" width="100%">
|
<br><br>
|
<br><br>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
|
|
|
|
