//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2001 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: openMSP430.v
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// *File Name: openMSP430.v
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//
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//
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// *Module Description:
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// *Module Description:
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// openMSP430 Top level file
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// openMSP430 Top level file
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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module openMSP430 (
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module openMSP430 (
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// OUTPUTs
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// OUTPUTs
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aclk_en, // ACLK enable
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aclk_en, // ACLK enable
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dbg_freeze, // Freeze peripherals
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dbg_freeze, // Freeze peripherals
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dbg_uart_txd, // Debug interface: UART TXD
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dbg_uart_txd, // Debug interface: UART TXD
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dmem_addr, // Data Memory address
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dmem_addr, // Data Memory address
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dmem_cen, // Data Memory chip enable (low active)
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dmem_cen, // Data Memory chip enable (low active)
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dmem_din, // Data Memory data input
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dmem_din, // Data Memory data input
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dmem_wen, // Data Memory write enable (low active)
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dmem_wen, // Data Memory write enable (low active)
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irq_acc, // Interrupt request accepted (one-hot signal)
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irq_acc, // Interrupt request accepted (one-hot signal)
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mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_wen, // Peripheral write enable (high active)
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per_wen, // Peripheral write enable (high active)
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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pmem_addr, // Program Memory address
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pmem_addr, // Program Memory address
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pmem_cen, // Program Memory chip enable (low active)
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pmem_cen, // Program Memory chip enable (low active)
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pmem_din, // Program Memory data input (optional)
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pmem_din, // Program Memory data input (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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puc, // Main system reset
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puc, // Main system reset
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smclk_en, // SMCLK enable
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smclk_en, // SMCLK enable
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// INPUTs
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// INPUTs
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dbg_uart_rxd, // Debug interface: UART RXD
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dbg_uart_rxd, // Debug interface: UART RXD
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dco_clk, // Fast oscillator (fast clock)
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dco_clk, // Fast oscillator (fast clock)
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dmem_dout, // Data Memory data output
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dmem_dout, // Data Memory data output
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irq, // Maskable interrupts
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irq, // Maskable interrupts
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lfxt_clk, // Low frequency oscillator (typ 32kHz)
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lfxt_clk, // Low frequency oscillator (typ 32kHz)
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nmi, // Non-maskable interrupt (asynchronous)
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nmi, // Non-maskable interrupt (asynchronous)
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per_dout, // Peripheral data output
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per_dout, // Peripheral data output
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pmem_dout, // Program Memory data output
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pmem_dout, // Program Memory data output
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reset_n // Reset Pin (low active)
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reset_n // Reset Pin (low active)
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output aclk_en; // ACLK enable
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output aclk_en; // ACLK enable
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output dbg_freeze; // Freeze peripherals
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output dbg_freeze; // Freeze peripherals
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output dbg_uart_txd; // Debug interface: UART TXD
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output dbg_uart_txd; // Debug interface: UART TXD
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output [`DMEM_MSB:0] dmem_addr; // Data Memory address
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output [`DMEM_MSB:0] dmem_addr; // Data Memory address
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output dmem_cen; // Data Memory chip enable (low active)
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output dmem_cen; // Data Memory chip enable (low active)
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output [15:0] dmem_din; // Data Memory data input
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output [15:0] dmem_din; // Data Memory data input
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
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output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
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output mclk; // Main system clock
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output mclk; // Main system clock
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output [7:0] per_addr; // Peripheral address
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output [7:0] per_addr; // Peripheral address
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output [15:0] per_din; // Peripheral data input
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output [15:0] per_din; // Peripheral data input
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output [1:0] per_wen; // Peripheral write enable (high active)
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output [1:0] per_wen; // Peripheral write enable (high active)
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output per_en; // Peripheral enable (high active)
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output per_en; // Peripheral enable (high active)
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output pmem_cen; // Program Memory chip enable (low active)
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output pmem_cen; // Program Memory chip enable (low active)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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output puc; // Main system reset
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output puc; // Main system reset
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output smclk_en; // SMCLK enable
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output smclk_en; // SMCLK enable
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// INPUTs
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// INPUTs
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//=========
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//=========
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input dbg_uart_rxd; // Debug interface: UART RXD
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input dbg_uart_rxd; // Debug interface: UART RXD
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input dco_clk; // Fast oscillator (fast clock)
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input dco_clk; // Fast oscillator (fast clock)
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input [15:0] dmem_dout; // Data Memory data output
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input [15:0] dmem_dout; // Data Memory data output
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input [13:0] irq; // Maskable interrupts
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input [13:0] irq; // Maskable interrupts
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input lfxt_clk; // Low frequency oscillator (typ 32kHz)
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input lfxt_clk; // Low frequency oscillator (typ 32kHz)
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input nmi; // Non-maskable interrupt (asynchronous)
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input nmi; // Non-maskable interrupt (asynchronous)
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input [15:0] per_dout; // Peripheral data output
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input [15:0] per_dout; // Peripheral data output
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input [15:0] pmem_dout; // Program Memory data output
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input [15:0] pmem_dout; // Program Memory data output
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input reset_n; // Reset Pin (active low)
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input reset_n; // Reset Pin (active low)
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//=============================================================================
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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//=============================================================================
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wire [7:0] inst_ad;
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wire [7:0] inst_ad;
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wire [7:0] inst_as;
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wire [7:0] inst_as;
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wire [11:0] inst_alu;
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wire [11:0] inst_alu;
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wire inst_bw;
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wire inst_bw;
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wire [15:0] inst_dest;
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wire [15:0] inst_dest;
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wire [15:0] inst_dext;
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wire [15:0] inst_dext;
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wire [15:0] inst_sext;
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wire [15:0] inst_sext;
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wire [7:0] inst_so;
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wire [7:0] inst_so;
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wire [15:0] inst_src;
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wire [15:0] inst_src;
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wire [2:0] inst_type;
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wire [2:0] inst_type;
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wire [3:0] e_state;
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wire [3:0] e_state;
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wire exec_done;
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wire exec_done;
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wire [15:0] eu_mab;
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wire [15:0] eu_mab;
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wire [15:0] eu_mdb_in;
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wire [15:0] eu_mdb_in;
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wire [15:0] eu_mdb_out;
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wire [15:0] eu_mdb_out;
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wire [1:0] eu_mb_wr;
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wire [1:0] eu_mb_wr;
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wire [15:0] fe_mab;
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wire [15:0] fe_mab;
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wire [15:0] fe_mdb_in;
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wire [15:0] fe_mdb_in;
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wire [15:0] pc_sw;
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wire [15:0] pc_sw;
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wire [7:0] inst_jmp;
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wire [7:0] inst_jmp;
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wire [15:0] pc;
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wire [15:0] pc;
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wire [15:0] pc_nxt;
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wire [15:0] pc_nxt;
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wire dbg_halt_cmd;
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wire dbg_halt_cmd;
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wire dbg_mem_en;
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wire dbg_mem_en;
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wire dbg_reg_wr;
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wire dbg_reg_wr;
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wire dbg_reset;
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wire dbg_reset;
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wire [15:0] dbg_mem_addr;
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wire [15:0] dbg_mem_addr;
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wire [15:0] dbg_mem_dout;
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wire [15:0] dbg_mem_dout;
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wire [15:0] dbg_mem_din;
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wire [15:0] dbg_mem_din;
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wire [15:0] dbg_reg_din;
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wire [15:0] dbg_reg_din;
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wire [1:0] dbg_mem_wr;
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wire [1:0] dbg_mem_wr;
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wire [15:0] per_dout_or;
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wire [15:0] per_dout_or;
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wire [15:0] per_dout_sfr;
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wire [15:0] per_dout_sfr;
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wire [15:0] per_dout_wdog;
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wire [15:0] per_dout_wdog;
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wire [15:0] per_dout_mpy;
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wire [15:0] per_dout_mpy;
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wire [15:0] per_dout_clk;
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wire [15:0] per_dout_clk;
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//=============================================================================
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//=============================================================================
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// 2) GLOBAL CLOCK & RESET MANAGEMENT
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// 2) GLOBAL CLOCK & RESET MANAGEMENT
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//=============================================================================
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//=============================================================================
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omsp_clock_module clock_module_0 (
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omsp_clock_module clock_module_0 (
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// OUTPUTs
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// OUTPUTs
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.aclk_en (aclk_en), // ACLK enablex
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.aclk_en (aclk_en), // ACLK enablex
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_dout (per_dout_clk), // Peripheral data output
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.per_dout (per_dout_clk), // Peripheral data output
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.por (por), // Power-on reset
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.por (por), // Power-on reset
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.puc (puc), // Main system reset
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.puc (puc), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable
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.smclk_en (smclk_en), // SMCLK enable
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|
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// INPUTs
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// INPUTs
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.dbg_reset (dbg_reset), // Reset CPU from debug interface
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.dbg_reset (dbg_reset), // Reset CPU from debug interface
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.oscoff (oscoff), // Turns off LFXT1 clock input
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.oscoff (oscoff), // Turns off LFXT1 clock input
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.reset_n (reset_n), // Reset Pin (low active)
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.reset_n (reset_n), // Reset Pin (low active)
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.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
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.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
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.wdt_reset (wdt_reset) // Watchdog-timer reset
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.wdt_reset (wdt_reset) // Watchdog-timer reset
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);
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);
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//=============================================================================
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//=============================================================================
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// 3) FRONTEND (<=> FETCH & DECODE)
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// 3) FRONTEND (<=> FETCH & DECODE)
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//=============================================================================
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//=============================================================================
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omsp_frontend frontend_0 (
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omsp_frontend frontend_0 (
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// OUTPUTs
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// OUTPUTs
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.decode_noirq (decode_noirq), // Frontend decode instruction
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.decode_noirq (decode_noirq), // Frontend decode instruction
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.e_state (e_state), // Execution state
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.e_state (e_state), // Execution state
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.exec_done (exec_done), // Execution completed
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.exec_done (exec_done), // Execution completed
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.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
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.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
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.inst_as (inst_as), // Decoded Inst: source addressing mode
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.inst_as (inst_as), // Decoded Inst: source addressing mode
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.inst_alu (inst_alu), // ALU control signals
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.inst_alu (inst_alu), // ALU control signals
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
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.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
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.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
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.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
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.inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt
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.inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt
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.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
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.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
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.inst_mov (inst_mov), // Decoded Inst: mov instruction
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.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
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.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
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.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
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.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
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.inst_src (inst_src), // Decoded Inst: source (one hot)
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.inst_src (inst_src), // Decoded Inst: source (one hot)
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.inst_type (inst_type), // Decoded Instruction type
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.inst_type (inst_type), // Decoded Instruction type
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.irq_acc (irq_acc), // Interrupt request accepted
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.irq_acc (irq_acc), // Interrupt request accepted
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.mab (fe_mab), // Frontend Memory address bus
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.mab (fe_mab), // Frontend Memory address bus
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.mb_en (fe_mb_en), // Frontend Memory bus enable
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.mb_en (fe_mb_en), // Frontend Memory bus enable
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.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
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.pc (pc), // Program counter
|
.pc (pc), // Program counter
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.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
|
|
// INPUTs
|
// INPUTs
|
.cpuoff (cpuoff), // Turns off the CPU
|
.cpuoff (cpuoff), // Turns off the CPU
|
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
|
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
|
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
|
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.gie (gie), // General interrupt enable
|
.gie (gie), // General interrupt enable
|
.irq (irq), // Maskable interrupts
|
.irq (irq), // Maskable interrupts
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.nmi_evt (nmi_evt), // Non-maskable interrupt event
|
.nmi_evt (nmi_evt), // Non-maskable interrupt event
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.puc (puc), // Main system reset
|
.puc (puc), // Main system reset
|
.wdt_irq (wdt_irq) // Watchdog-timer interrupt
|
.wdt_irq (wdt_irq) // Watchdog-timer interrupt
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 4) EXECUTION UNIT
|
// 4) EXECUTION UNIT
|
//=============================================================================
|
//=============================================================================
|
|
|
omsp_execution_unit execution_unit_0 (
|
omsp_execution_unit execution_unit_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.cpuoff (cpuoff), // Turns off the CPU
|
.cpuoff (cpuoff), // Turns off the CPU
|
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
|
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
|
.mab (eu_mab), // Memory address bus
|
.mab (eu_mab), // Memory address bus
|
.mb_en (eu_mb_en), // Memory bus enable
|
.mb_en (eu_mb_en), // Memory bus enable
|
.mb_wr (eu_mb_wr), // Memory bus write transfer
|
.mb_wr (eu_mb_wr), // Memory bus write transfer
|
.mdb_out (eu_mdb_out), // Memory data bus output
|
.mdb_out (eu_mdb_out), // Memory data bus output
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
|
|
// INPUTs
|
// INPUTs
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
|
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
|
.e_state (e_state), // Execution state
|
.e_state (e_state), // Execution state
|
.exec_done (exec_done), // Execution completed
|
.exec_done (exec_done), // Execution completed
|
.gie (gie), // General interrupt enable
|
.gie (gie), // General interrupt enable
|
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
|
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
|
.inst_as (inst_as), // Decoded Inst: source addressing mode
|
.inst_as (inst_as), // Decoded Inst: source addressing mode
|
.inst_alu (inst_alu), // ALU control signals
|
.inst_alu (inst_alu), // ALU control signals
|
.inst_bw (inst_bw), // Decoded Inst: byte width
|
.inst_bw (inst_bw), // Decoded Inst: byte width
|
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
|
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
|
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
|
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
|
.inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt
|
.inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt
|
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
|
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
|
|
.inst_mov (inst_mov), // Decoded Inst: mov instruction
|
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
|
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
|
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
|
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
|
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
.inst_type (inst_type), // Decoded Instruction type
|
.inst_type (inst_type), // Decoded Instruction type
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
.pc (pc), // Program counter
|
.pc (pc), // Program counter
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.puc (puc) // Main system reset
|
.puc (puc) // Main system reset
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 5) MEMORY BACKBONE
|
// 5) MEMORY BACKBONE
|
//=============================================================================
|
//=============================================================================
|
|
|
omsp_mem_backbone mem_backbone_0 (
|
omsp_mem_backbone mem_backbone_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
.dmem_addr (dmem_addr), // Data Memory address
|
.dmem_addr (dmem_addr), // Data Memory address
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
.dmem_din (dmem_din), // Data Memory data input
|
.dmem_din (dmem_din), // Data Memory data input
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
|
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.pmem_addr (pmem_addr), // Program Memory address
|
.pmem_addr (pmem_addr), // Program Memory address
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
|
|
// INPUTs
|
// INPUTs
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
.dmem_dout (dmem_dout), // Data Memory data output
|
.dmem_dout (dmem_dout), // Data Memory data output
|
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
|
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
|
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
|
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
|
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
|
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
|
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
|
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_dout (per_dout_or), // Peripheral data output
|
.per_dout (per_dout_or), // Peripheral data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.puc (puc) // Main system reset
|
.puc (puc) // Main system reset
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 6) SPECIAL FUNCTION REGISTERS
|
// 6) SPECIAL FUNCTION REGISTERS
|
//=============================================================================
|
//=============================================================================
|
|
|
omsp_sfr sfr_0 (
|
omsp_sfr sfr_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.nmie (nmie), // Non-maskable interrupt enable
|
.nmie (nmie), // Non-maskable interrupt enable
|
.per_dout (per_dout_sfr), // Peripheral data output
|
.per_dout (per_dout_sfr), // Peripheral data output
|
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
|
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
|
.wdt_reset (wdt_reset), // Watchdog-timer reset
|
.wdt_reset (wdt_reset), // Watchdog-timer reset
|
.wdtie (wdtie), // Watchdog-timer interrupt enable
|
.wdtie (wdtie), // Watchdog-timer interrupt enable
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.por (por), // Power-on reset
|
.por (por), // Power-on reset
|
.puc (puc), // Main system reset
|
.puc (puc), // Main system reset
|
.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
|
.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
|
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
|
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
|
.wdtpw_error (wdtpw_error), // Watchdog-timer password error
|
.wdtpw_error (wdtpw_error), // Watchdog-timer password error
|
.wdttmsel (wdttmsel) // Watchdog-timer mode select
|
.wdttmsel (wdttmsel) // Watchdog-timer mode select
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 7) WATCHDOG TIMER
|
// 7) WATCHDOG TIMER
|
//=============================================================================
|
//=============================================================================
|
|
|
omsp_watchdog watchdog_0 (
|
omsp_watchdog watchdog_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.nmi_evt (nmi_evt), // NMI Event
|
.nmi_evt (nmi_evt), // NMI Event
|
.per_dout (per_dout_wdog), // Peripheral data output
|
.per_dout (per_dout_wdog), // Peripheral data output
|
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
|
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
|
.wdtpw_error (wdtpw_error), // Watchdog-timer password error
|
.wdtpw_error (wdtpw_error), // Watchdog-timer password error
|
.wdttmsel (wdttmsel), // Watchdog-timer mode select
|
.wdttmsel (wdttmsel), // Watchdog-timer mode select
|
|
|
// INPUTs
|
// INPUTs
|
.aclk_en (aclk_en), // ACLK enable
|
.aclk_en (aclk_en), // ACLK enable
|
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
|
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
.nmie (nmie), // Non-maskable interrupt enable
|
.nmie (nmie), // Non-maskable interrupt enable
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.puc (puc), // Main system reset
|
.puc (puc), // Main system reset
|
.smclk_en (smclk_en), // SMCLK enable
|
.smclk_en (smclk_en), // SMCLK enable
|
.wdtie (wdtie) // Watchdog-timer interrupt enable
|
.wdtie (wdtie) // Watchdog-timer interrupt enable
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 8) HARDWARE MULTIPLIER
|
// 8) HARDWARE MULTIPLIER
|
//=============================================================================
|
//=============================================================================
|
`ifdef MULTIPLIER
|
`ifdef MULTIPLIER
|
omsp_multiplier multiplier_0 (
|
omsp_multiplier multiplier_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.per_dout (per_dout_mpy), // Peripheral data output
|
.per_dout (per_dout_mpy), // Peripheral data output
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.puc (puc) // Main system reset
|
.puc (puc) // Main system reset
|
);
|
);
|
`else
|
`else
|
assign per_dout_mpy = 16'h0000;
|
assign per_dout_mpy = 16'h0000;
|
`endif
|
`endif
|
|
|
//=============================================================================
|
//=============================================================================
|
// 9) PERIPHERALS' OUTPUT BUS
|
// 9) PERIPHERALS' OUTPUT BUS
|
//=============================================================================
|
//=============================================================================
|
|
|
assign per_dout_or = per_dout |
|
assign per_dout_or = per_dout |
|
per_dout_clk |
|
per_dout_clk |
|
per_dout_sfr |
|
per_dout_sfr |
|
per_dout_wdog |
|
per_dout_wdog |
|
per_dout_mpy;
|
per_dout_mpy;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 10) DEBUG INTERFACE
|
// 10) DEBUG INTERFACE
|
//=============================================================================
|
//=============================================================================
|
|
|
`ifdef DBG_EN
|
`ifdef DBG_EN
|
omsp_dbg dbg_0 (
|
omsp_dbg dbg_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.dbg_freeze (dbg_freeze), // Freeze peripherals
|
.dbg_freeze (dbg_freeze), // Freeze peripherals
|
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
|
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
|
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
|
.dbg_reset (dbg_reset), // Reset CPU from debug interface
|
.dbg_reset (dbg_reset), // Reset CPU from debug interface
|
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
|
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
|
|
|
// INPUTs
|
// INPUTs
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
|
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
|
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
|
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
|
.decode_noirq (decode_noirq), // Frontend decode instruction
|
.decode_noirq (decode_noirq), // Frontend decode instruction
|
.eu_mab (eu_mab), // Execution-Unit Memory address bus
|
.eu_mab (eu_mab), // Execution-Unit Memory address bus
|
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
|
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
|
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
|
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
|
.eu_mdb_in (eu_mdb_in), // Memory data bus input
|
.eu_mdb_in (eu_mdb_in), // Memory data bus input
|
.eu_mdb_out (eu_mdb_out), // Memory data bus output
|
.eu_mdb_out (eu_mdb_out), // Memory data bus output
|
.exec_done (exec_done), // Execution completed
|
.exec_done (exec_done), // Execution completed
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.pc (pc), // Program counter
|
.pc (pc), // Program counter
|
.por (por), // Power on reset
|
.por (por), // Power on reset
|
.puc (puc) // Main system reset
|
.puc (puc) // Main system reset
|
);
|
);
|
|
|
`else
|
`else
|
assign dbg_freeze = 1'b0;
|
assign dbg_freeze = 1'b0;
|
assign dbg_halt_cmd = 1'b0;
|
assign dbg_halt_cmd = 1'b0;
|
assign dbg_mem_addr = 16'h0000;
|
assign dbg_mem_addr = 16'h0000;
|
assign dbg_mem_dout = 16'h0000;
|
assign dbg_mem_dout = 16'h0000;
|
assign dbg_mem_en = 1'b0;
|
assign dbg_mem_en = 1'b0;
|
assign dbg_mem_wr = 2'b00;
|
assign dbg_mem_wr = 2'b00;
|
assign dbg_reg_wr = 1'b0;
|
assign dbg_reg_wr = 1'b0;
|
assign dbg_reset = 1'b0;
|
assign dbg_reset = 1'b0;
|
assign dbg_uart_txd = 1'b0;
|
assign dbg_uart_txd = 1'b0;
|
`endif
|
`endif
|
|
|
|
|
endmodule // openMSP430
|
endmodule // openMSP430
|
|
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_undefines.v"
|
`include "openMSP430_undefines.v"
|
`endif
|
`endif
|
|
|