URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [src/] [spacewar.v] - Diff between revs 107 and 136

Rev 107	Rev 136
`/===========================================================================/`	`/===========================================================================/`
`/* DIGITAL I/O */`	`/* DIGITAL I/O */`
`/---------------------------------------------------------------------------/`	`/---------------------------------------------------------------------------/`
`/* Test the Digital I/O interface. */`	`/* Test the Digital I/O interface. */`
`/===========================================================================/`	`/===========================================================================/`

`initial`	`initial`
`begin`	`begin`
`$display(" ===============================================");`	`$display(" ===============================================");`
`$display("\| START SIMULATION \|");`	`$display("\| START SIMULATION \|");`
`$display(" ===============================================");`	`$display(" ===============================================");`
`repeat(5) @(posedge oscclk);`	`repeat(5) @(posedge oscclk);`
`stimulus_done = 0;`	`stimulus_done = 0;`

`repeat(50) @(posedge mclk);`	`repeat(50) @(posedge mclk);`

`// Send uart synchronization frame`	`// Send uart synchronization frame`
`dbg_uart_tx(DBG_SYNC);`	`dbg_uart_sync;`

`// Let the CPU run`	`// Let the CPU run`
`dbg_uart_wr(CPU_CTL, 16'h0002);`	`dbg_uart_wr(CPU_CTL, 16'h0002);`

`stimulus_done = 1;`	`stimulus_done = 1;`
`end`	`end`