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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [synplify.tcl] - Diff between revs 80 and 82

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Rev 80 Rev 82
 
 
 
 
 
 
#add_file options
#add_file options
add_file -verilog    "../design_files.v"
add_file -verilog    "../design_files.v"
add_file -constraint "../design_files.sdc"
add_file -constraint "../design_constraints.pre.sdc"
 
 
 
 
#implementation: "rev_1"
#implementation: "synplify"
impl -add rev_1 -type fpga
impl -add "synplify" -type fpga
 
 
#device options
#device options
set_option -technology  <DEVICE_FAMILY>
set_option -technology  <DEVICE_FAMILY>
set_option -part        <DEVICE_NAME>
set_option -part        <DEVICE_NAME>
set_option -package     <DEVICE_PACKAGE>
set_option -package     <DEVICE_PACKAGE>
set_option -speed_grade <SPEED_GRADE>
set_option -speed_grade <SPEED_GRADE>
set_option -part_companion ""
set_option -part_companion ""
 
 
#compilation/mapping options
#compilation/mapping options
set_option -default_enum_encoding default
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -use_fsm_explorer 1
set_option -top_module <TOP_LEVEL>
set_option -top_module <TOP_LEVEL>
 
 
#map options
#map options
set_option -frequency 30.000
set_option -frequency 50.0
set_option -vendor_xcompatible_mode 0
set_option -vendor_xcompatible_mode 0
set_option -vendor_xcompatible_mode 0
set_option -vendor_xcompatible_mode 0
set_option -run_prop_extract 1
set_option -run_prop_extract 1
set_option -fanout_limit 24
set_option -fanout_limit 24
set_option -globalthreshold 50
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -retiming 1
set_option -report_path 4000
set_option -report_path 4000
set_option -opcond COMWC
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -preserve_registers 0
 
 
 
 
#sequential_optimizations options
#sequential_optimizations options
set_option -symbolic_fsm_compiler 1
set_option -symbolic_fsm_compiler 1
 
 
#simulation options
#simulation options
set_option -write_verilog 0
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -write_vhdl 0
 
 
#automatic place and route (vendor) options
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
set_option -write_apr_constraint 1
 
 
#set result format/file last
#set result format/file last
project -result_format "edif"
project -result_format "edif"
project -result_file "./rev_1/design_files.edn"
project -result_file "./synplify.edn"
 
 
#
#
#implementation attributes
#implementation attributes
 
 
set_option -vlog_std v2001
set_option -vlog_std v2001
set_option -dup 0
set_option -dup 0
set_option -project_relative_includes 1
set_option -project_relative_includes 1
impl -active "rev_1"
impl -active "synplify"
 
 
 
 
# Run synthesis
# Run synthesis
project -run synthesis
project -run synthesis
 
 
# Save and quit
# Save and quit
project -save rev_1.prj
project -save "./synplify.prj"
 
 
#exit 0
 
 
 
 
#exit 0
 
 
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