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#add_file options
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#add_file options
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add_file -verilog "../design_files.v"
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add_file -verilog "../design_files.v"
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add_file -constraint "../design_files.sdc"
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add_file -constraint "../design_constraints.pre.sdc"
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#implementation: "rev_1"
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#implementation: "synplify"
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impl -add rev_1 -type fpga
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impl -add "synplify" -type fpga
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#device options
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#device options
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set_option -technology <DEVICE_FAMILY>
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set_option -technology <DEVICE_FAMILY>
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set_option -part <DEVICE_NAME>
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set_option -part <DEVICE_NAME>
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set_option -package <DEVICE_PACKAGE>
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set_option -package <DEVICE_PACKAGE>
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set_option -speed_grade <SPEED_GRADE>
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set_option -speed_grade <SPEED_GRADE>
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set_option -part_companion ""
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set_option -part_companion ""
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#compilation/mapping options
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#compilation/mapping options
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set_option -default_enum_encoding default
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set_option -default_enum_encoding default
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set_option -resource_sharing 1
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set_option -resource_sharing 1
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set_option -use_fsm_explorer 0
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set_option -use_fsm_explorer 1
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set_option -top_module <TOP_LEVEL>
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set_option -top_module <TOP_LEVEL>
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#map options
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#map options
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set_option -frequency 30.000
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set_option -frequency 50.0
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set_option -vendor_xcompatible_mode 0
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set_option -vendor_xcompatible_mode 0
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set_option -vendor_xcompatible_mode 0
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set_option -vendor_xcompatible_mode 0
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set_option -run_prop_extract 1
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set_option -run_prop_extract 1
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set_option -fanout_limit 24
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set_option -fanout_limit 24
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set_option -globalthreshold 50
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set_option -globalthreshold 50
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set_option -maxfan_hard 0
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set_option -maxfan_hard 0
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set_option -disable_io_insertion 0
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set_option -disable_io_insertion 0
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set_option -retiming 0
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set_option -retiming 1
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set_option -report_path 4000
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set_option -report_path 4000
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set_option -opcond COMWC
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set_option -opcond COMWC
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set_option -update_models_cp 0
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set_option -update_models_cp 0
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set_option -preserve_registers 0
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set_option -preserve_registers 0
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#sequential_optimizations options
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#sequential_optimizations options
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set_option -symbolic_fsm_compiler 1
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set_option -symbolic_fsm_compiler 1
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#simulation options
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#simulation options
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set_option -write_verilog 0
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set_option -write_verilog 0
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set_option -write_vhdl 0
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set_option -write_vhdl 0
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|
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#automatic place and route (vendor) options
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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set_option -write_apr_constraint 1
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|
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#set result format/file last
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#set result format/file last
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project -result_format "edif"
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project -result_format "edif"
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project -result_file "./rev_1/design_files.edn"
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project -result_file "./synplify.edn"
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#
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#
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#implementation attributes
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#implementation attributes
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|
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set_option -vlog_std v2001
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set_option -vlog_std v2001
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set_option -dup 0
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set_option -dup 0
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set_option -project_relative_includes 1
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set_option -project_relative_includes 1
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impl -active "rev_1"
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impl -active "synplify"
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|
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# Run synthesis
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# Run synthesis
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project -run synthesis
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project -run synthesis
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# Save and quit
|
# Save and quit
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project -save rev_1.prj
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project -save "./synplify.prj"
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|
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#exit 0
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#exit 0
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No newline at end of file
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No newline at end of file
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