//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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// Copyright (C) 2015 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: ogfx_backend_lut_fifo.v
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// *File Name: ogfx_backend_lut_fifo.v
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//
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//
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// *Module Description:
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// *Module Description:
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// Mini-cache memory for the LUT memory accesses.
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// Mini-cache memory for the LUT memory accesses.
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev$
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// $Rev$
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// $LastChangedBy$
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// $LastChangedBy$
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// $LastChangedDate$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`ifdef OGFX_NO_INCLUDE
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`else
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`else
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`include "openGFX430_defines.v"
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`include "openGFX430_defines.v"
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`endif
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`endif
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module ogfx_backend_lut_fifo (
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module ogfx_backend_lut_fifo (
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// OUTPUTs
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// OUTPUTs
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frame_data_request_o, // Request for next frame data
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frame_data_request_o, // Request for next frame data
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refresh_data_o, // Display Refresh data
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refresh_data_o, // Display Refresh data
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refresh_data_ready_o, // Display Refresh data ready
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refresh_data_ready_o, // Display Refresh data ready
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`ifdef WITH_PROGRAMMABLE_LUT
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_ram_addr_o, // LUT-RAM address
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lut_ram_addr_o, // LUT-RAM address
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lut_ram_cen_o, // LUT-RAM enable (active low)
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lut_ram_cen_o, // LUT-RAM enable (active low)
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`endif
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`endif
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// INPUTs
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// INPUTs
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mclk, // Main system clock
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mclk, // Main system clock
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puc_rst, // Main system reset
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puc_rst, // Main system reset
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frame_data_i, // Frame data
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frame_data_i, // Frame data
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frame_data_ready_i, // Frame data ready
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frame_data_ready_i, // Frame data ready
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gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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`ifdef WITH_PROGRAMMABLE_LUT
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_ram_dout_i, // LUT-RAM data output
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lut_ram_dout_i, // LUT-RAM data output
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lut_ram_dout_rdy_nxt_i, // LUT-RAM data output ready during next cycle
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lut_ram_dout_rdy_nxt_i, // LUT-RAM data output ready during next cycle
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`endif
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`endif
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refresh_active_i, // Display refresh on going
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refresh_active_i, // Display refresh on going
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refresh_data_request_i, // Request for next refresh data
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refresh_data_request_i, // Request for next refresh data
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refresh_lut_select_i // Refresh LUT bank selection
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hw_lut_palette_sel_i, // Hardware LUT palette configuration
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hw_lut_bgcolor_i, // Hardware LUT background-color selection
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hw_lut_fgcolor_i, // Hardware LUT foreground-color selection
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sw_lut_enable_i, // Refresh LUT-RAM enable
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sw_lut_bank_select_i // Refresh LUT-RAM bank selection
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output frame_data_request_o; // Request for next frame data
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output frame_data_request_o; // Request for next frame data
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output [15:0] refresh_data_o; // Display Refresh data
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output [15:0] refresh_data_o; // Display Refresh data
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output refresh_data_ready_o; // Display Refresh data ready
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output refresh_data_ready_o; // Display Refresh data ready
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`ifdef WITH_PROGRAMMABLE_LUT
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`ifdef WITH_PROGRAMMABLE_LUT
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output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
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output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
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output lut_ram_cen_o; // LUT-RAM enable (active low)
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output lut_ram_cen_o; // LUT-RAM enable (active low)
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`endif
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`endif
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// INPUTs
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// INPUTs
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//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input [15:0] frame_data_i; // Frame data
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input [15:0] frame_data_i; // Frame data
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input frame_data_ready_i; // Frame data ready
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input frame_data_ready_i; // Frame data ready
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input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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`ifdef WITH_PROGRAMMABLE_LUT
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`ifdef WITH_PROGRAMMABLE_LUT
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input [15:0] lut_ram_dout_i; // LUT-RAM data output
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input [15:0] lut_ram_dout_i; // LUT-RAM data output
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input lut_ram_dout_rdy_nxt_i; // LUT-RAM data output ready during next cycle
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input lut_ram_dout_rdy_nxt_i; // LUT-RAM data output ready during next cycle
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`endif
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`endif
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input refresh_active_i; // Display refresh on going
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input refresh_active_i; // Display refresh on going
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input refresh_data_request_i; // Request for next refresh data
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input refresh_data_request_i; // Request for next refresh data
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input [1:0] refresh_lut_select_i; // Refresh LUT bank selection
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input [2:0] hw_lut_palette_sel_i; // Hardware LUT palette configuration
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input [3:0] hw_lut_bgcolor_i; // Hardware LUT background-color selection
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input [3:0] hw_lut_fgcolor_i; // Hardware LUT foreground-color selection
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input sw_lut_enable_i; // Refresh LUT-RAM enable
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input sw_lut_bank_select_i; // Refresh LUT-RAM bank selection
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//=============================================================================
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//=============================================================================
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// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
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// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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// State machine registers
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// State machine registers
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reg [1:0] lut_state;
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reg [1:0] lut_state;
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reg [1:0] lut_state_nxt;
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reg [1:0] lut_state_nxt;
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// State definition
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// State definition
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parameter STATE_IDLE = 0,
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parameter STATE_IDLE = 0,
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STATE_FRAME_DATA = 1,
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STATE_FRAME_DATA = 1,
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STATE_LUT_DATA = 2,
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STATE_LUT_DATA = 2,
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STATE_HOLD = 3;
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STATE_HOLD = 3;
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// Some parameter(s)
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// Some parameter(s)
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parameter FIFO_EMPTY = 3'h0,
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parameter FIFO_EMPTY = 3'h0,
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FIFO_FULL = 3'h5;
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FIFO_FULL = 3'h5;
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// Video modes decoding
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// Video modes decoding
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wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);
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wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);
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wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);
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wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);
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wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);
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wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);
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wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);
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wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);
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wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp |
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wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp |
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gfx_mode_2_bpp | gfx_mode_1_bpp);
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gfx_mode_2_bpp | gfx_mode_1_bpp);
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// Others
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// Others
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reg [2:0] fifo_counter;
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reg [2:0] fifo_counter;
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wire [2:0] fifo_counter_nxt;
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wire [2:0] fifo_counter_nxt;
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//============================================================================
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//============================================================================
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// 2) HARD CODED LOOKUP TABLE
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// 2) HARD CODED LOOKUP TABLE
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//============================================================================
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//============================================================================
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wire [15:0] lut_hw_data_1_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[0] ==1'b0 }}) | // 1 bpp: Black
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// 16 full CGA color selection
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({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[0] ==1'b1 }}) ; // White
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parameter [3:0] CGA_BLACK = 4'h0,
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CGA_BLUE = 4'h1,
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wire [15:0] lut_hw_data_2_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[1:0]==2'b00 }}) | // 2 bpp: Black
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CGA_GREEN = 4'h2,
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({5'b01000, 6'b010000, 5'b01000} & {16{frame_data_i[1:0]==2'b01 }}) | // Dark Gray
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CGA_CYAN = 4'h3,
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({5'b11000, 6'b110000, 5'b11000} & {16{frame_data_i[1:0]==2'b10 }}) | // Light Gray
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CGA_RED = 4'h4,
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({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[1:0]==2'b11 }}) ; // White
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CGA_MAGENTA = 4'h5,
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CGA_BROWN = 4'h6,
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wire [15:0] lut_hw_data_4_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0000}}) | // 4 bpp: Black
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CGA_LIGHT_GRAY = 4'h7,
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({5'b00000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0001}}) | // Dark Blue
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CGA_GRAY = 4'h8,
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({5'b10000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0010}}) | // Dark Red
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CGA_LIGHT_BLUE = 4'h9,
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({5'b10000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0011}}) | // Dark Magenta
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CGA_LIGHT_GREEN = 4'hA,
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({5'b00000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0100}}) | // Dark Green
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CGA_LIGHT_CYAN = 4'hB,
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({5'b00000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0101}}) | // Dark Cyan
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CGA_LIGHT_RED = 4'hC,
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({5'b10000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0110}}) | // Dark Yellow
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CGA_LIGHT_MAGENTA = 4'hD,
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({5'b10000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0111}}) | // Gray
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CGA_YELLOW = 4'hE,
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({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1000}}) | // Black
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CGA_WHITE = 4'hF;
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({5'b00000, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1001}}) | // Blue
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({5'b11111, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1010}}) | // Red
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// Decode CGA 4 color mode (2bpp)
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({5'b11111, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1011}}) | // Magenta
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wire cga_palette0_hi = (hw_lut_palette_sel_i==3'h0);
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({5'b00000, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1100}}) | // Green
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wire cga_palette0_lo = (hw_lut_palette_sel_i==3'h1);
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({5'b00000, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1101}}) | // Cyan
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wire cga_palette1_hi = (hw_lut_palette_sel_i==3'h2);
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({5'b11111, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1110}}) | // Yellow
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wire cga_palette1_lo = (hw_lut_palette_sel_i==3'h3);
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({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1111}}); // White
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wire cga_palette2_hi = (hw_lut_palette_sel_i==3'h4);
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wire cga_palette2_lo = (hw_lut_palette_sel_i==3'h5) | (hw_lut_palette_sel_i==3'h6) | (hw_lut_palette_sel_i==3'h7);
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// LUT color decoding
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// 1 BPP
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wire [3:0] lut_hw_sel_1bpp = ({4{gfx_mode_1_bpp & (frame_data_i[0] ==1'b0 )}} & hw_lut_bgcolor_i ) | // 1 bpp: Black (default bgcolor)
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({4{gfx_mode_1_bpp & (frame_data_i[0] ==1'b1 )}} & hw_lut_fgcolor_i ) ; // White (default fgcolor)
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// 2 BPP (Palette #0, low-intensity)
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wire [3:0] lut_hw_sel_2bpp = ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
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({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b01)}} & CGA_GREEN ) | // Green
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({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED ) | // Red
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({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b11)}} & CGA_BROWN ) | // Brown
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// 2 BPP (Palette #0, high-intensity)
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({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
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({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_GREEN ) | // Light-Green
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({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED ) | // Light-Red
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({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b11)}} & CGA_YELLOW ) | // Yellow
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// 2 BPP (Palette #1, low-intensity)
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({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
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({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN ) | // Cyan
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({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b10)}} & CGA_MAGENTA ) | // Magenta
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({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY ) | // Light-Gray
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// 2 BPP (Palette #1, high-intensity)
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({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
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({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN ) | // Light-Cyan
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({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_MAGENTA) | // Light-Magenta
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({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE ) | // White
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// 2 BPP (Palette #2, low-intensity)
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({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
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({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN ) | // Cyan
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({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED ) | // Red
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({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY ) | // Light-Gray
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// 2 BPP (Palette #2, high-intensity)
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({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
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({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN ) | // Light-Cyan
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({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED ) | // Light-Red
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({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE ) ; // White
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// 4 BPP (full CGA 16-color palette)
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wire [3:0] lut_hw_sel_4bpp = ({4{gfx_mode_4_bpp}} & frame_data_i[3:0]);
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wire [3:0] lut_hw_color_sel = lut_hw_sel_4bpp | lut_hw_sel_2bpp | lut_hw_sel_1bpp;
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// Color encoding for 1-bit / 2-bit and 4-bit modes
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reg [15:0] lut_hw_data_1_2_4_bpp;
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always @(lut_hw_color_sel)
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case(lut_hw_color_sel)
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CGA_BLACK : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b000000, 5'b00000}; // Black
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CGA_BLUE : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b000000, 5'b10101}; // Blue
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CGA_GREEN : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b101011, 5'b00000}; // Green
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CGA_CYAN : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b101011, 5'b10101}; // Cyan
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CGA_RED : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b000000, 5'b00000}; // Red
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CGA_MAGENTA : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b000000, 5'b10101}; // Magenta
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CGA_BROWN : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b010101, 5'b00000}; // Brown
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CGA_LIGHT_GRAY : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b101011, 5'b10101}; // Light Gray
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CGA_GRAY : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b010101, 5'b01011}; // Gray
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CGA_LIGHT_BLUE : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b010101, 5'b11111}; // Light Blue
|
|
CGA_LIGHT_GREEN : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b111111, 5'b01011}; // Light Green
|
|
CGA_LIGHT_CYAN : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b111111, 5'b11111}; // Light Cyan
|
|
CGA_LIGHT_RED : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b010101, 5'b01011}; // Light Red
|
|
CGA_LIGHT_MAGENTA : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b010101, 5'b11111}; // Light Magenta
|
|
CGA_YELLOW : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b111111, 5'b01011}; // Yellow
|
|
CGA_WHITE : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b111111, 5'b11111}; // White
|
|
// pragma coverage off
|
|
default : lut_hw_data_1_2_4_bpp = 16'h0000;
|
|
// pragma coverage on
|
|
endcase
|
|
|
|
// 8-bit truecolor RGB mapping (3-bit red / 3-bit green / 2-bit blue)
|
wire [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5], // 8 bpp: R = D<7,6,5,5,5>
|
wire [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5], // 8 bpp: R = D<7,6,5,5,5>
|
frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2], // G = D<4,3,2,2,2,2>
|
frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2], // G = D<4,3,2,2,2,2>
|
frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]}; // B = D<1,0,0,0,0>
|
frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]}; // B = D<1,0,0,0,0>
|
|
|
wire [15:0] lut_hw_data = (lut_hw_data_1_bpp & {16{gfx_mode_1_bpp}}) |
|
wire [15:0] lut_hw_data = (lut_hw_data_1_2_4_bpp & {16{gfx_mode_1_bpp | gfx_mode_2_bpp | gfx_mode_4_bpp}}) |
|
(lut_hw_data_2_bpp & {16{gfx_mode_2_bpp}}) |
|
|
(lut_hw_data_4_bpp & {16{gfx_mode_4_bpp}}) |
|
|
(lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});
|
(lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});
|
|
|
wire lut_hw_enabled = ~gfx_mode_16_bpp & ~refresh_lut_select_i[0];
|
wire lut_hw_enabled = ~gfx_mode_16_bpp & ~sw_lut_enable_i;
|
wire lut_sw_enabled = ~gfx_mode_16_bpp & refresh_lut_select_i[0];
|
wire lut_sw_enabled = ~gfx_mode_16_bpp & sw_lut_enable_i;
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 3) STATE MACHINE
|
// 3) STATE MACHINE
|
//============================================================================
|
//============================================================================
|
|
|
//--------------------------------
|
//--------------------------------
|
// States Transitions
|
// States Transitions
|
//--------------------------------
|
//--------------------------------
|
always @(lut_state or refresh_active_i or frame_data_ready_i or
|
always @(lut_state or refresh_active_i or frame_data_ready_i or
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
lut_sw_enabled or lut_ram_dout_rdy_nxt_i or
|
lut_sw_enabled or lut_ram_dout_rdy_nxt_i or
|
`endif
|
`endif
|
fifo_counter_nxt)
|
fifo_counter_nxt)
|
case(lut_state)
|
case(lut_state)
|
|
|
STATE_IDLE : lut_state_nxt = ~refresh_active_i ? STATE_IDLE : STATE_FRAME_DATA ;
|
STATE_IDLE : lut_state_nxt = ~refresh_active_i ? STATE_IDLE : STATE_FRAME_DATA ;
|
|
|
STATE_FRAME_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
|
STATE_FRAME_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
|
~frame_data_ready_i ? STATE_FRAME_DATA :
|
~frame_data_ready_i ? STATE_FRAME_DATA :
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
lut_sw_enabled ? STATE_LUT_DATA :
|
lut_sw_enabled ? STATE_LUT_DATA :
|
`endif
|
`endif
|
STATE_HOLD ;
|
STATE_HOLD ;
|
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
STATE_LUT_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
|
STATE_LUT_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
|
lut_ram_dout_rdy_nxt_i ? STATE_HOLD : STATE_LUT_DATA ;
|
lut_ram_dout_rdy_nxt_i ? STATE_HOLD : STATE_LUT_DATA ;
|
`endif
|
`endif
|
|
|
STATE_HOLD : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
|
STATE_HOLD : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
|
(fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD ;
|
(fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD ;
|
|
|
// pragma coverage off
|
// pragma coverage off
|
default : lut_state_nxt = STATE_IDLE;
|
default : lut_state_nxt = STATE_IDLE;
|
// pragma coverage on
|
// pragma coverage on
|
endcase
|
endcase
|
|
|
//--------------------------------
|
//--------------------------------
|
// State machine
|
// State machine
|
//--------------------------------
|
//--------------------------------
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) lut_state <= STATE_IDLE;
|
if (puc_rst) lut_state <= STATE_IDLE;
|
else lut_state <= lut_state_nxt;
|
else lut_state <= lut_state_nxt;
|
|
|
|
|
// Request for the next frame data
|
// Request for the next frame data
|
assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);
|
assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 4) LUT MEMORY INTERFACE
|
// 4) LUT MEMORY INTERFACE
|
//============================================================================
|
//============================================================================
|
|
|
//--------------------------------
|
//--------------------------------
|
// Enable
|
// Enable
|
//--------------------------------
|
//--------------------------------
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
assign lut_ram_cen_o = ~(lut_state == STATE_LUT_DATA);
|
assign lut_ram_cen_o = ~(lut_state == STATE_LUT_DATA);
|
`endif
|
`endif
|
|
|
//--------------------------------
|
//--------------------------------
|
// Address
|
// Address
|
//--------------------------------
|
//--------------------------------
|
// Mask with chip enable to save power
|
// Mask with chip enable to save power
|
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_EXTRA_LUT_BANK
|
`ifdef WITH_EXTRA_LUT_BANK
|
// Allow LUT bank switching only when the refresh is not on going
|
// Allow LUT bank switching only when the refresh is not on going
|
reg refresh_lut_bank_select_sync;
|
reg refresh_lut_bank_select_sync;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) refresh_lut_bank_select_sync <= 1'b0;
|
if (puc_rst) refresh_lut_bank_select_sync <= 1'b0;
|
else if (~refresh_active_i) refresh_lut_bank_select_sync <= refresh_lut_select_i[1];
|
else if (~refresh_active_i) refresh_lut_bank_select_sync <= sw_lut_bank_select_i;
|
|
|
assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
|
assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
|
`else
|
`else
|
assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};
|
assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
//--------------------------------
|
//--------------------------------
|
// Data Ready
|
// Data Ready
|
//--------------------------------
|
//--------------------------------
|
// When filling the FIFO, the data is available on the bus
|
// When filling the FIFO, the data is available on the bus
|
// one cycle after the rdy_nxt signal
|
// one cycle after the rdy_nxt signal
|
reg lut_ram_dout_ready;
|
reg lut_ram_dout_ready;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) lut_ram_dout_ready <= 1'b0;
|
if (puc_rst) lut_ram_dout_ready <= 1'b0;
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
else lut_ram_dout_ready <= lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :
|
else lut_ram_dout_ready <= lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :
|
(frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
|
(frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
|
`else
|
`else
|
else lut_ram_dout_ready <= (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
|
else lut_ram_dout_ready <= (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
|
`endif
|
`endif
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 5) FIFO COUNTER
|
// 5) FIFO COUNTER
|
//============================================================================
|
//============================================================================
|
|
|
// Control signals
|
// Control signals
|
wire fifo_push = lut_ram_dout_ready & (fifo_counter != FIFO_FULL);
|
wire fifo_push = lut_ram_dout_ready & (fifo_counter != FIFO_FULL);
|
wire fifo_pop = refresh_data_request_i & (fifo_counter != FIFO_EMPTY);
|
wire fifo_pop = refresh_data_request_i & (fifo_counter != FIFO_EMPTY);
|
|
|
// Fifo counter
|
// Fifo counter
|
assign fifo_counter_nxt = ~refresh_active_i ? FIFO_EMPTY : // Initialize
|
assign fifo_counter_nxt = ~refresh_active_i ? FIFO_EMPTY : // Initialize
|
(fifo_push & fifo_pop) ? fifo_counter : // Keep value (pop & push at the same time)
|
(fifo_push & fifo_pop) ? fifo_counter : // Keep value (pop & push at the same time)
|
fifo_push ? fifo_counter + 3'h1 : // Push
|
fifo_push ? fifo_counter + 3'h1 : // Push
|
fifo_pop ? fifo_counter - 3'h1 : // Pop
|
fifo_pop ? fifo_counter - 3'h1 : // Pop
|
fifo_counter; // Hold
|
fifo_counter; // Hold
|
|
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) fifo_counter <= FIFO_EMPTY;
|
if (puc_rst) fifo_counter <= FIFO_EMPTY;
|
else fifo_counter <= fifo_counter_nxt;
|
else fifo_counter <= fifo_counter_nxt;
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 6) FIFO MEMORY & RD/WR POINTERS
|
// 6) FIFO MEMORY & RD/WR POINTERS
|
//============================================================================
|
//============================================================================
|
|
|
// Write pointer
|
// Write pointer
|
reg [2:0] wr_ptr;
|
reg [2:0] wr_ptr;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) wr_ptr <= 3'h0;
|
if (puc_rst) wr_ptr <= 3'h0;
|
else if (~refresh_active_i) wr_ptr <= 3'h0;
|
else if (~refresh_active_i) wr_ptr <= 3'h0;
|
else if (fifo_push)
|
else if (fifo_push)
|
begin
|
begin
|
if (wr_ptr==(FIFO_FULL-1)) wr_ptr <= 3'h0;
|
if (wr_ptr==(FIFO_FULL-1)) wr_ptr <= 3'h0;
|
else wr_ptr <= wr_ptr + 3'h1;
|
else wr_ptr <= wr_ptr + 3'h1;
|
end
|
end
|
|
|
// Memory
|
// Memory
|
reg [15:0] fifo_mem [0:4];
|
reg [15:0] fifo_mem [0:4];
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst)
|
if (puc_rst)
|
begin
|
begin
|
fifo_mem[0] <= 16'h0000;
|
fifo_mem[0] <= 16'h0000;
|
fifo_mem[1] <= 16'h0000;
|
fifo_mem[1] <= 16'h0000;
|
fifo_mem[2] <= 16'h0000;
|
fifo_mem[2] <= 16'h0000;
|
fifo_mem[3] <= 16'h0000;
|
fifo_mem[3] <= 16'h0000;
|
fifo_mem[4] <= 16'h0000;
|
fifo_mem[4] <= 16'h0000;
|
end
|
end
|
else if (fifo_push)
|
else if (fifo_push)
|
begin
|
begin
|
fifo_mem[wr_ptr] <= lut_hw_enabled ? lut_hw_data :
|
fifo_mem[wr_ptr] <= lut_hw_enabled ? lut_hw_data :
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
lut_sw_enabled ? lut_ram_dout_i :
|
lut_sw_enabled ? lut_ram_dout_i :
|
`endif
|
`endif
|
frame_data_i;
|
frame_data_i;
|
end
|
end
|
|
|
// Read pointer
|
// Read pointer
|
reg [2:0] rd_ptr;
|
reg [2:0] rd_ptr;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) rd_ptr <= 3'h0;
|
if (puc_rst) rd_ptr <= 3'h0;
|
else if (~refresh_active_i) rd_ptr <= 3'h0;
|
else if (~refresh_active_i) rd_ptr <= 3'h0;
|
else if (fifo_pop)
|
else if (fifo_pop)
|
begin
|
begin
|
if (rd_ptr==(FIFO_FULL-1)) rd_ptr <= 3'h0;
|
if (rd_ptr==(FIFO_FULL-1)) rd_ptr <= 3'h0;
|
else rd_ptr <= rd_ptr + 3'h1;
|
else rd_ptr <= rd_ptr + 3'h1;
|
end
|
end
|
|
|
//============================================================================
|
//============================================================================
|
// 7) REFRESH_DATA
|
// 7) REFRESH_DATA
|
//============================================================================
|
//============================================================================
|
|
|
// Refresh Data is ready
|
// Refresh Data is ready
|
reg refresh_data_ready_o;
|
reg refresh_data_ready_o;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) refresh_data_ready_o <= 1'h0;
|
if (puc_rst) refresh_data_ready_o <= 1'h0;
|
else if (~refresh_active_i) refresh_data_ready_o <= 1'h0;
|
else if (~refresh_active_i) refresh_data_ready_o <= 1'h0;
|
else refresh_data_ready_o <= fifo_pop;
|
else refresh_data_ready_o <= fifo_pop;
|
|
|
// Refresh Data
|
// Refresh Data
|
reg [15:0] refresh_data_o;
|
reg [15:0] refresh_data_o;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) refresh_data_o <= 16'h0000;
|
if (puc_rst) refresh_data_o <= 16'h0000;
|
else if (fifo_pop) refresh_data_o <= fifo_mem[rd_ptr];
|
else if (fifo_pop) refresh_data_o <= fifo_mem[rd_ptr];
|
|
|
|
|
endmodule // ogfx_backend_lut_fifo
|
endmodule // ogfx_backend_lut_fifo
|
|
|
`ifdef OGFX_NO_INCLUDE
|
`ifdef OGFX_NO_INCLUDE
|
`else
|
`else
|
`include "openGFX430_undefines.v"
|
`include "openGFX430_undefines.v"
|
`endif
|
`endif
|
|
|
