#ifndef GFX_CONTROLLER_H
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#ifndef GFX_CONTROLLER_H
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#define GFX_CONTROLLER_H
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#define GFX_CONTROLLER_H
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#include "timerA.h"
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#include "timerA.h"
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#include <in430.h>
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#include <in430.h>
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#include <stdint.h>
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#include <stdint.h>
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//----------------------------------------------------------
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//----------------------------------------------------------
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// GLOBAL CONFIGURATION
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// GLOBAL CONFIGURATION
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//----------------------------------------------------------
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//----------------------------------------------------------
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#ifdef VERILOG_SIMULATION
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#ifdef VERILOG_SIMULATION
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#define SCREEN_WIDTH 5
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#define SCREEN_WIDTH 5
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#define SCREEN_HEIGHT 3
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#define SCREEN_HEIGHT 3
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#else
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#else
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#define SCREEN_WIDTH 320
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#define SCREEN_WIDTH 320
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#define SCREEN_HEIGHT 240
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#define SCREEN_HEIGHT 240
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#endif
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#endif
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#define FRAME_MEMORY_KB_SIZE 75*2
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#define FRAME_MEMORY_KB_SIZE 75*2
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//#define LT24_ROTATE
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//#define LT24_ROTATE
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//----------------------------------------------------------
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//----------------------------------------------------------
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// UTILITY MACROS
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// UTILITY MACROS
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//----------------------------------------------------------
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//----------------------------------------------------------
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// Convert pixel coordinates into memory address
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// Convert pixel coordinates into memory address
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#define PIX_ADDR(X, Y) ((((uint32_t)(Y)) * ((uint32_t)(SCREEN_WIDTH))) + ((uint32_t)(X)))
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#define PIX_ADDR(X, Y) ((((uint32_t)(Y)) * ((uint32_t)(SCREEN_WIDTH))) + ((uint32_t)(X)))
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//----------------------------------------------------------
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//----------------------------------------------------------
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// FUNCTIONS
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// FUNCTIONS
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//----------------------------------------------------------
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//----------------------------------------------------------
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// Initialization functions
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// Initialization functions
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void init_gfx_ctrl (uint16_t gfx_mode, uint16_t refresh_rate);
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void init_gfx_ctrl (uint16_t gfx_mode, uint16_t refresh_rate);
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void start_gfx_ctrl(void);
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void start_gfx_ctrl(void);
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// LT24 specific functions
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// LT24 specific functions
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void init_lt24(uint16_t lt24_clk_div);
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void init_lt24(uint16_t lt24_clk_div);
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void start_lt24(void);
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void start_lt24(void);
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// GPU Functions
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// GPU Functions
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void gpu_fill (uint32_t addr, uint16_t width, uint16_t length, uint16_t color, uint16_t configuration);
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void gpu_fill (uint32_t addr, uint16_t width, uint16_t length, uint16_t color, uint16_t configuration);
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void gpu_copy (uint32_t src_addr, uint32_t dst_addr, uint16_t width, uint16_t length, uint16_t configuration);
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void gpu_copy (uint32_t src_addr, uint32_t dst_addr, uint16_t width, uint16_t length, uint16_t configuration);
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void gpu_copy_transparent (uint32_t src_addr, uint32_t dst_addr, uint16_t width, uint16_t length, uint16_t trans_color, uint16_t configuration);
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void gpu_copy_transparent (uint32_t src_addr, uint32_t dst_addr, uint16_t width, uint16_t length, uint16_t trans_color, uint16_t configuration);
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inline void gpu_wait_done (void);
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inline void gpu_wait_done (void);
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// Other Functions
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// Other Functions
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void sync_screen_refresh_done(void);
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void sync_screen_refresh_done(void);
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void sync_screen_refresh_start(void);
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void sync_screen_refresh_start(void);
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//----------------------------------------------------------
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//----------------------------------------------------------
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// GRAPHIC CONTROLLER REGISTERS
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// GRAPHIC CONTROLLER REGISTERS
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//----------------------------------------------------------
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//----------------------------------------------------------
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#define GFX_CTRL (*(volatile uint16_t *) 0x0200)
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#define GFX_CTRL (*(volatile uint16_t *) 0x0200)
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#define GFX_STATUS (*(volatile uint16_t *) 0x0208)
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#define GFX_STATUS (*(volatile uint16_t *) 0x0208)
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#define GFX_IRQ (*(volatile uint16_t *) 0x020A)
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#define GFX_IRQ (*(volatile uint16_t *) 0x020A)
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#define DISPLAY_WIDTH (*(volatile uint16_t *) 0x0210)
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#define DISPLAY_WIDTH (*(volatile uint16_t *) 0x0210)
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#define DISPLAY_HEIGHT (*(volatile uint16_t *) 0x0212)
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#define DISPLAY_HEIGHT (*(volatile uint16_t *) 0x0212)
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#define DISPLAY_SIZE (*(volatile uint32_t *) 0x0214)
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#define DISPLAY_SIZE (*(volatile uint32_t *) 0x0214)
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#define DISPLAY_CFG (*(volatile uint16_t *) 0x0218)
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#define DISPLAY_CFG (*(volatile uint16_t *) 0x0218)
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#define DISPLAY_REFR_CNT (*(volatile uint16_t *) 0x021A)
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#define DISPLAY_REFR_CNT (*(volatile uint16_t *) 0x021A)
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#define LT24_CFG (*(volatile uint16_t *) 0x0220)
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#define LT24_CFG (*(volatile uint16_t *) 0x0220)
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#define LT24_REFRESH (*(volatile uint16_t *) 0x0222)
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#define LT24_REFRESH (*(volatile uint16_t *) 0x0222)
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#define LT24_REFRESH_SYNC (*(volatile uint16_t *) 0x0224)
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#define LT24_REFRESH_SYNC (*(volatile uint16_t *) 0x0224)
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#define LT24_CMD (*(volatile uint16_t *) 0x0226)
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#define LT24_CMD (*(volatile uint16_t *) 0x0226)
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#define LT24_CMD_PARAM (*(volatile uint16_t *) 0x0228)
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#define LT24_CMD_PARAM (*(volatile uint16_t *) 0x0228)
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#define LT24_CMD_DFILL (*(volatile uint16_t *) 0x022A)
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#define LT24_CMD_DFILL (*(volatile uint16_t *) 0x022A)
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#define LT24_STATUS (*(volatile uint16_t *) 0x022C)
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#define LT24_STATUS (*(volatile uint16_t *) 0x022C)
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#define LUT_RAM_ADDR (*(volatile uint16_t *) 0x0230)
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#define LUT_CFG (*(volatile uint16_t *) 0x0230)
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#define LUT_RAM_DATA (*(volatile uint16_t *) 0x0232)
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#define LUT_RAM_ADDR (*(volatile uint16_t *) 0x0232)
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#define LUT_RAM_DATA (*(volatile uint16_t *) 0x0234)
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#define FRAME_SELECT (*(volatile uint16_t *) 0x023E)
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#define FRAME_SELECT (*(volatile uint16_t *) 0x023E)
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#define FRAME0_PTR (*(volatile uint32_t *) 0x0240)
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#define FRAME0_PTR (*(volatile uint32_t *) 0x0240)
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#define FRAME1_PTR (*(volatile uint32_t *) 0x0244)
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#define FRAME1_PTR (*(volatile uint32_t *) 0x0244)
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#define FRAME2_PTR (*(volatile uint32_t *) 0x0248)
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#define FRAME2_PTR (*(volatile uint32_t *) 0x0248)
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#define FRAME3_PTR (*(volatile uint32_t *) 0x024C)
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#define FRAME3_PTR (*(volatile uint32_t *) 0x024C)
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#define VID_RAM0_CFG (*(volatile uint16_t *) 0x0250)
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#define VID_RAM0_CFG (*(volatile uint16_t *) 0x0250)
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#define VID_RAM0_WIDTH (*(volatile uint16_t *) 0x0252)
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#define VID_RAM0_WIDTH (*(volatile uint16_t *) 0x0252)
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#define VID_RAM0_ADDR (*(volatile uint32_t *) 0x0254)
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#define VID_RAM0_ADDR (*(volatile uint32_t *) 0x0254)
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#define VID_RAM0_DATA (*(volatile uint16_t *) 0x0258)
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#define VID_RAM0_DATA (*(volatile uint16_t *) 0x0258)
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#define VID_RAM1_CFG (*(volatile uint16_t *) 0x0260)
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#define VID_RAM1_CFG (*(volatile uint16_t *) 0x0260)
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#define VID_RAM1_WIDTH (*(volatile uint16_t *) 0x0262)
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#define VID_RAM1_WIDTH (*(volatile uint16_t *) 0x0262)
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#define VID_RAM1_ADDR (*(volatile uint32_t *) 0x0264)
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#define VID_RAM1_ADDR (*(volatile uint32_t *) 0x0264)
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#define VID_RAM1_DATA (*(volatile uint16_t *) 0x0268)
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#define VID_RAM1_DATA (*(volatile uint16_t *) 0x0268)
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#define GPU_CMD (*(volatile uint16_t *) 0x0270)
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#define GPU_CMD (*(volatile uint16_t *) 0x0270)
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#define GPU_CMD32 (*(volatile uint32_t *) 0x0270)
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#define GPU_CMD32 (*(volatile uint32_t *) 0x0270)
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#define GPU_STAT (*(volatile uint16_t *) 0x0274)
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#define GPU_STAT (*(volatile uint16_t *) 0x0274)
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//----------------------------------------------------------
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//----------------------------------------------------------
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// GRAPHIC CONTROLLER REGISTER FIELD MAPPING
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// GRAPHIC CONTROLLER REGISTER FIELD MAPPING
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//----------------------------------------------------------
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//----------------------------------------------------------
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// GFX_CTRL Register
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// GFX_CTRL Register
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#define GFX_REFR_DONE_IRQ_EN 0x0001
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#define GFX_REFR_DONE_IRQ_EN 0x0001
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#define GFX_REFR_DONE_IRQ_DIS 0x0000
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#define GFX_REFR_DONE_IRQ_DIS 0x0000
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#define GFX_REFR_START_IRQ_EN 0x0002
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#define GFX_REFR_START_IRQ_EN 0x0002
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#define GFX_REFR_START_IRQ_DIS 0x0000
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#define GFX_REFR_START_IRQ_DIS 0x0000
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#define GFX_REFR_CNT_DONE_IRQ_EN 0x0004
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#define GFX_REFR_CNT_DONE_IRQ_DIS 0x0000
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#define GFX_GPU_FIFO_DONE_IRQ_EN 0x0010
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#define GFX_GPU_FIFO_DONE_IRQ_EN 0x0010
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#define GFX_GPU_FIFO_DONE_IRQ_DIS 0x0000
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#define GFX_GPU_FIFO_DONE_IRQ_DIS 0x0000
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#define GFX_GPU_FIFO_OVFL_IRQ_EN 0x0020
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#define GFX_GPU_FIFO_OVFL_IRQ_EN 0x0020
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#define GFX_GPU_FIFO_OVFL_IRQ_DIS 0x0000
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#define GFX_GPU_FIFO_OVFL_IRQ_DIS 0x0000
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#define GFX_GPU_CMD_DONE_IRQ_EN 0x0040
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#define GFX_GPU_CMD_DONE_IRQ_EN 0x0040
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#define GFX_GPU_CMD_DONE_IRQ_DIS 0x0000
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#define GFX_GPU_CMD_DONE_IRQ_DIS 0x0000
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#define GFX_GPU_CMD_ERROR_IRQ_EN 0x0080
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#define GFX_GPU_CMD_ERROR_IRQ_EN 0x0080
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#define GFX_GPU_CMD_ERROR_IRQ_DIS 0x0000
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#define GFX_GPU_CMD_ERROR_IRQ_DIS 0x0000
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#define GFX_16_BPP 0x0400
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#define GFX_16_BPP 0x0400
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#define GFX_8_BPP 0x0300
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#define GFX_8_BPP 0x0300
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#define GFX_4_BPP 0x0200
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#define GFX_4_BPP 0x0200
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#define GFX_2_BPP 0x0100
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#define GFX_2_BPP 0x0100
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#define GFX_1_BPP 0x0000
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#define GFX_1_BPP 0x0000
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#define GFX_GPU_EN 0x1000
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#define GFX_GPU_EN 0x1000
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#define GFX_GPU_DIS 0x0000
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#define GFX_GPU_DIS 0x0000
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// GFX_STATUS Register
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// GFX_STATUS Register
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#define STATUS_REFRESH_BUSY 0x0001
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#define STATUS_REFRESH_BUSY 0x0001
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#define STATUS_GPU_FIFO 0x0010
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#define STATUS_GPU_BUSY 0x0040
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// GFX_IRQ Register
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// GFX_IRQ Register
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#define GFX_IRQ_REFRESH_DONE 0x0001
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#define GFX_IRQ_REFRESH_DONE 0x0001
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#define GFX_IRQ_REFRESH_START 0x0002
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#define GFX_IRQ_REFRESH_START 0x0002
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#define GFX_IRQ_REFRESH_CNT_DONE 0x0004
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#define GFX_IRQ_GPU_FIFO_DONE 0x0010
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#define GFX_IRQ_GPU_FIFO_DONE 0x0010
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#define GFX_IRQ_GPU_FIFO_OVFL 0x0020
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#define GFX_IRQ_GPU_FIFO_OVFL 0x0020
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#define GFX_IRQ_GPU_CMD_DONE 0x0040
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#define GFX_IRQ_GPU_CMD_DONE 0x0040
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#define GFX_IRQ_GPU_CMD_ERROR 0x0080
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#define GFX_IRQ_GPU_CMD_ERROR 0x0080
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// DISPLAY_CFG Register
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// DISPLAY_CFG Register
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#define DISPLAY_CL_SWAP 0x0001
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#define DISPLAY_CL_SWAP 0x0001
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#define DISPLAY_Y_SWAP 0x0002
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#define DISPLAY_Y_SWAP 0x0002
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#define DISPLAY_X_SWAP 0x0004
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#define DISPLAY_X_SWAP 0x0004
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#define DISPLAY_NO_CL_SWAP 0x0000
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#define DISPLAY_NO_CL_SWAP 0x0000
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#define DISPLAY_NO_Y_SWAP 0x0000
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#define DISPLAY_NO_Y_SWAP 0x0000
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#define DISPLAY_NO_X_SWAP 0x0000
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#define DISPLAY_NO_X_SWAP 0x0000
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// LT24_CFG Register
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// LT24_CFG Register
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#define LT24_ON 0x0001
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#define LT24_ON 0x0001
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#define LT24_RESET 0x0002
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#define LT24_RESET 0x0002
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#define LT24_CLK_DIV1 0x0000
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#define LT24_CLK_DIV1 0x0000
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#define LT24_CLK_DIV2 0x0010
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#define LT24_CLK_DIV2 0x0010
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#define LT24_CLK_DIV3 0x0020
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#define LT24_CLK_DIV3 0x0020
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#define LT24_CLK_DIV4 0x0030
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#define LT24_CLK_DIV4 0x0030
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#define LT24_CLK_DIV5 0x0040
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#define LT24_CLK_DIV5 0x0040
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#define LT24_CLK_DIV6 0x0050
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#define LT24_CLK_DIV6 0x0050
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#define LT24_CLK_DIV7 0x0060
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#define LT24_CLK_DIV7 0x0060
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#define LT24_CLK_DIV8 0x0070
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#define LT24_CLK_DIV8 0x0070
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#define LT24_CLK_MASK 0x0070
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#define LT24_CLK_MASK 0x0070
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// LT24_REFRESH Register
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// LT24_REFRESH Register
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#define LT24_REFR_START 0x0001
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#define LT24_REFR_START 0x0001
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#define LT24_REFR_MANUAL 0x0000
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#define LT24_REFR_MANUAL 0x0000
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#define LT24_REFR_21_FPS (((48000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_21_FPS (((48000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_24_FPS (((40000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_24_FPS (((40000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_31_FPS (((32000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_31_FPS (((32000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_42_FPS (((24000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_42_FPS (((24000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_62_FPS (((16000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_62_FPS (((16000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_125_FPS ((( 8000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_125_FPS ((( 8000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_250_FPS ((( 4000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_250_FPS ((( 4000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_500_FPS ((( 2000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_500_FPS ((( 2000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_1000_FPS ((( 1000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_1000_FPS ((( 1000000/DCO_CLK_PERIOD)>>8) & 0xFFF0)
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#define LT24_REFR_MASK 0xFFF0
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#define LT24_REFR_MASK 0xFFF0
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// LT24_REFRESH_SYNC Register
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// LT24_REFRESH_SYNC Register
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#define LT24_REFR_SYNC 0x8000
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#define LT24_REFR_SYNC 0x8000
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#define LT24_REFR_NO_SYNC 0x0000
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#define LT24_REFR_NO_SYNC 0x0000
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// LT24_CMD Register
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// LT24_CMD Register
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#define LT24_CMD_MSK 0x00FF
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#define LT24_CMD_MSK 0x00FF
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#define LT24_CMD_HAS_PARAM 0x0100
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#define LT24_CMD_HAS_PARAM 0x0100
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#define LT24_CMD_NO_PARAM 0x0000
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#define LT24_CMD_NO_PARAM 0x0000
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// LT24_STATUS Register
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// LT24_STATUS Register
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#define LT24_STATUS_FSM_BUSY 0x0001
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#define LT24_STATUS_FSM_BUSY 0x0001
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#define LT24_STATUS_WAIT_PARAM 0x0002
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#define LT24_STATUS_WAIT_PARAM 0x0002
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#define LT24_STATUS_REFRESH_BUSY 0x0004
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#define LT24_STATUS_REFRESH_BUSY 0x0004
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#define LT24_STATUS_REFRESH_WAIT 0x0008
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#define LT24_STATUS_REFRESH_WAIT 0x0008
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#define LT24_STATUS_DFILL_BUSY 0x0010
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#define LT24_STATUS_DFILL_BUSY 0x0010
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// LUT_CFG Register
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#define SW_LUT_DISABLE 0x0000
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#define SW_LUT_ENABLE 0x0001
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#define SW_LUT_RAM_RMW_MODE 0x0002
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#define SW_LUT_RAM_NO_RMW_MODE 0x0000
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#define SW_LUT_BANK0_SELECT 0x0000
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#define SW_LUT_BANK1_SELECT 0x0004
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#define HW_LUT_PALETTE_0_HI 0x0000
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#define HW_LUT_PALETTE_0_LO 0x0010
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#define HW_LUT_PALETTE_1_HI 0x0020
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#define HW_LUT_PALETTE_1_LO 0x0030
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#define HW_LUT_PALETTE_2_HI 0x0040
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#define HW_LUT_PALETTE_2_LO 0x0050
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#define HW_LUT_PALETTE_MSK 0x0070
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#define HW_LUT_BGCOLOR_MSK 0x0F00
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#define HW_LUT_FGCOLOR_MSK 0xF000
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#define HW_LUT_BG_BLACK 0x0000
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#define HW_LUT_BG_BLUE 0x0100
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#define HW_LUT_BG_GREEN 0x0200
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#define HW_LUT_BG_CYAN 0x0300
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#define HW_LUT_BG_RED 0x0400
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#define HW_LUT_BG_MAGENTA 0x0500
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#define HW_LUT_BG_BROWN 0x0600
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#define HW_LUT_BG_LIGHT_GRAY 0x0700
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#define HW_LUT_BG_GRAY 0x0800
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#define HW_LUT_BG_LIGHT_BLUE 0x0900
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#define HW_LUT_BG_LIGHT_GREEN 0x0A00
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#define HW_LUT_BG_LIGHT_CYAN 0x0B00
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#define HW_LUT_BG_LIGHT_RED 0x0C00
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#define HW_LUT_BG_LIGHT_MAGENTA 0x0D00
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#define HW_LUT_BG_YELLOW 0x0E00
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#define HW_LUT_BG_WHITE 0x0F00
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#define HW_LUT_FG_BLACK 0x0000
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#define HW_LUT_FG_BLUE 0x1000
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#define HW_LUT_FG_GREEN 0x2000
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#define HW_LUT_FG_CYAN 0x3000
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#define HW_LUT_FG_RED 0x4000
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#define HW_LUT_FG_MAGENTA 0x5000
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#define HW_LUT_FG_BROWN 0x6000
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#define HW_LUT_FG_LIGHT_GRAY 0x7000
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#define HW_LUT_FG_GRAY 0x8000
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#define HW_LUT_FG_LIGHT_BLUE 0x9000
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#define HW_LUT_FG_LIGHT_GREEN 0xA000
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#define HW_LUT_FG_LIGHT_CYAN 0xB000
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#define HW_LUT_FG_LIGHT_RED 0xC000
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#define HW_LUT_FG_LIGHT_MAGENTA 0xD000
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#define HW_LUT_FG_YELLOW 0xE000
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#define HW_LUT_FG_WHITE 0xF000
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// FRAME_SELECT Register
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// FRAME_SELECT Register
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#define REFRESH_FRAME0_SELECT 0x0000
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#define REFRESH_FRAME0_SELECT 0x0000
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#define REFRESH_FRAME1_SELECT 0x0001
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#define REFRESH_FRAME1_SELECT 0x0001
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#define REFRESH_FRAME2_SELECT 0x0002
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#define REFRESH_FRAME2_SELECT 0x0002
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#define REFRESH_FRAME3_SELECT 0x0003
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#define REFRESH_FRAME3_SELECT 0x0003
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#define REFRESH_FRAME_MASK 0x0003
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#define REFRESH_FRAME_MASK 0x0003
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#define REFRESH_SW_LUT_DISABLE 0x0000
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#define REFRESH_SW_LUT_ENABLE 0x0004
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#define REFRESH_SW_LUT0_SELECT 0x0000
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#define REFRESH_SW_LUT1_SELECT 0x0008
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#define VID_RAM0_FRAME0_SELECT 0x0000
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#define VID_RAM0_FRAME0_SELECT 0x0000
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#define VID_RAM0_FRAME1_SELECT 0x0010
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#define VID_RAM0_FRAME1_SELECT 0x0010
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#define VID_RAM0_FRAME2_SELECT 0x0020
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#define VID_RAM0_FRAME2_SELECT 0x0020
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#define VID_RAM0_FRAME3_SELECT 0x0030
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#define VID_RAM0_FRAME3_SELECT 0x0030
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#define VID_RAM0_FRAME_MASK 0x0030
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#define VID_RAM0_FRAME_MASK 0x0030
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#define VID_RAM1_FRAME0_SELECT 0x0000
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#define VID_RAM1_FRAME0_SELECT 0x0000
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#define VID_RAM1_FRAME1_SELECT 0x0040
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#define VID_RAM1_FRAME1_SELECT 0x0040
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#define VID_RAM1_FRAME2_SELECT 0x0080
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#define VID_RAM1_FRAME2_SELECT 0x0080
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#define VID_RAM1_FRAME3_SELECT 0x00C0
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#define VID_RAM1_FRAME3_SELECT 0x00C0
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#define VID_RAM1_FRAME_MASK 0x00C0
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#define VID_RAM1_FRAME_MASK 0x00C0
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#define LUT_BANK0_SELECT 0x0000
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#define LUT_BANK1_SELECT 0x8000
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// VID_RAMx_CFG Register
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// VID_RAMx_CFG Register
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#define VID_RAM_RMW_MODE 0x0010
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#define VID_RAM_RMW_MODE 0x0010
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#define VID_RAM_MSK_MODE 0x0020
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#define VID_RAM_MSK_MODE 0x0020
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#define VID_RAM_WIN_MODE 0x0040
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#define VID_RAM_WIN_MODE 0x0040
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#define VID_RAM_NO_RMW_MODE 0x0000
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#define VID_RAM_NO_RMW_MODE 0x0000
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#define VID_RAM_NO_MSK_MODE 0x0000
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#define VID_RAM_NO_MSK_MODE 0x0000
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#define VID_RAM_NO_WIN_MODE 0x0000
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#define VID_RAM_NO_WIN_MODE 0x0000
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#define VID_RAM_WIN_CL_SWAP 0x0001
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#define VID_RAM_WIN_CL_SWAP 0x0001
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#define VID_RAM_WIN_Y_SWAP 0x0002
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#define VID_RAM_WIN_Y_SWAP 0x0002
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#define VID_RAM_WIN_X_SWAP 0x0004
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#define VID_RAM_WIN_X_SWAP 0x0004
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#define VID_RAM_WIN_NO_CL_SWAP 0x0000
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#define VID_RAM_WIN_NO_CL_SWAP 0x0000
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#define VID_RAM_WIN_NO_Y_SWAP 0x0000
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#define VID_RAM_WIN_NO_Y_SWAP 0x0000
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#define VID_RAM_WIN_NO_X_SWAP 0x0000
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#define VID_RAM_WIN_NO_X_SWAP 0x0000
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// GPU_STAT Register
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// GPU_STAT Register
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#define GPU_STAT_FIFO_CNT_EMPTY 0x000F
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#define GPU_STAT_FIFO_CNT_EMPTY 0x000F
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#define GPU_STAT_FIFO_CNT 0x00F0
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#define GPU_STAT_FIFO_CNT 0x00F0
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#define GPU_STAT_FIFO_EMPTY 0x0100
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#define GPU_STAT_FIFO_EMPTY 0x0100
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#define GPU_STAT_FIFO_FULL 0x0200
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#define GPU_STAT_FIFO_FULL 0x0200
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#define GPU_STAT_DMA_BUSY 0x1000
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#define GPU_STAT_DMA_BUSY 0x1000
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#define GPU_STAT_BUSY 0x8000
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#define GPU_STAT_BUSY 0x8000
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//----------------------------------------------------------
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//----------------------------------------------------------
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// GPU COMMANDS
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// GPU COMMANDS
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//----------------------------------------------------------
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//----------------------------------------------------------
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// GPU COMMAND
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// GPU COMMAND
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#define GPU_EXEC_FILL 0x0000
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#define GPU_EXEC_FILL 0x0000
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#define GPU_EXEC_COPY 0x4000
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#define GPU_EXEC_COPY 0x4000
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#define GPU_EXEC_COPY_TRANS 0x8000
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#define GPU_EXEC_COPY_TRANS 0x8000
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#define GPU_REC_WIDTH 0xC000
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#define GPU_REC_WIDTH 0xC000
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#define GPU_REC_HEIGHT 0xD000
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#define GPU_REC_HEIGHT 0xD000
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#define GPU_SRC_PX_ADDR 0xF800
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#define GPU_SRC_PX_ADDR 0xF800
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#define GPU_DST_PX_ADDR 0xF801
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#define GPU_DST_PX_ADDR 0xF801
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#define GPU_OF0_ADDR 0xF810
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#define GPU_OF0_ADDR 0xF810
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#define GPU_OF1_ADDR 0xF811
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#define GPU_OF1_ADDR 0xF811
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#define GPU_OF2_ADDR 0xF812
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#define GPU_OF2_ADDR 0xF812
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#define GPU_OF3_ADDR 0xF813
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#define GPU_OF3_ADDR 0xF813
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#define GPU_SET_FILL 0xF420
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#define GPU_SET_FILL 0xF420
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#define GPU_SET_TRANS 0xF421
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#define GPU_SET_TRANS 0xF421
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// ADDRESS SOURCE SELECTION
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// ADDRESS SOURCE SELECTION
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#define GPU_SRC_OF0 0x0000
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#define GPU_SRC_OF0 0x0000
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#define GPU_SRC_OF1 0x1000
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#define GPU_SRC_OF1 0x1000
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#define GPU_SRC_OF2 0x2000
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#define GPU_SRC_OF2 0x2000
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#define GPU_SRC_OF3 0x3000
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#define GPU_SRC_OF3 0x3000
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#define GPU_DST_OF0 0x0000
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#define GPU_DST_OF0 0x0000
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#define GPU_DST_OF1 0x0008
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#define GPU_DST_OF1 0x0008
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#define GPU_DST_OF2 0x0010
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#define GPU_DST_OF2 0x0010
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#define GPU_DST_OF3 0x0018
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#define GPU_DST_OF3 0x0018
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// DMA CONFIGURATION
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// DMA CONFIGURATION
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#define GPU_DST_CL_SWP 0x0001
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#define GPU_DST_CL_SWP 0x0001
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#define GPU_DST_Y_SWP 0x0002
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#define GPU_DST_Y_SWP 0x0002
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#define GPU_DST_X_SWP 0x0004
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#define GPU_DST_X_SWP 0x0004
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#define GPU_SRC_CL_SWP 0x0200
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#define GPU_SRC_CL_SWP 0x0200
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#define GPU_SRC_Y_SWP 0x0400
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#define GPU_SRC_Y_SWP 0x0400
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#define GPU_SRC_X_SWP 0x0800
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#define GPU_SRC_X_SWP 0x0800
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#define GPU_DST_NO_CL_SWP 0x0000
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#define GPU_DST_NO_CL_SWP 0x0000
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#define GPU_DST_NO_Y_SWP 0x0000
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#define GPU_DST_NO_Y_SWP 0x0000
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#define GPU_DST_NO_X_SWP 0x0000
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#define GPU_DST_NO_X_SWP 0x0000
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#define GPU_SRC_NO_CL_SWP 0x0000
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#define GPU_SRC_NO_CL_SWP 0x0000
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#define GPU_SRC_NO_Y_SWP 0x0000
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#define GPU_SRC_NO_Y_SWP 0x0000
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#define GPU_SRC_NO_X_SWP 0x0000
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#define GPU_SRC_NO_X_SWP 0x0000
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#define DST_SWAP_NONE 0x0000
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#define DST_SWAP_NONE 0x0000
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#define DST_SWAP_CL 0x0001
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#define DST_SWAP_CL 0x0001
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#define DST_SWAP_Y 0x0002
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#define DST_SWAP_Y 0x0002
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#define DST_SWAP_Y_CL 0x0003
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#define DST_SWAP_Y_CL 0x0003
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#define DST_SWAP_X 0x0004
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#define DST_SWAP_X 0x0004
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#define DST_SWAP_X_CL 0x0005
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#define DST_SWAP_X_CL 0x0005
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#define DST_SWAP_X_Y 0x0006
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#define DST_SWAP_X_Y 0x0006
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#define DST_SWAP_X_Y_CL 0x0007
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#define DST_SWAP_X_Y_CL 0x0007
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#define DST_SWAP_MSK 0xFFF8
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#define DST_SWAP_MSK 0xFFF8
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#define SRC_SWAP_NONE 0x0000
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#define SRC_SWAP_NONE 0x0000
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#define SRC_SWAP_CL 0x0200
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#define SRC_SWAP_CL 0x0200
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#define SRC_SWAP_Y 0x0400
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#define SRC_SWAP_Y 0x0400
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#define SRC_SWAP_Y_CL 0x0600
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#define SRC_SWAP_Y_CL 0x0600
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#define SRC_SWAP_X 0x0800
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#define SRC_SWAP_X 0x0800
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#define SRC_SWAP_X_CL 0x0A00
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#define SRC_SWAP_X_CL 0x0A00
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#define SRC_SWAP_X_Y 0x0C00
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#define SRC_SWAP_X_Y 0x0C00
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#define SRC_SWAP_X_Y_CL 0x0E00
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#define SRC_SWAP_X_Y_CL 0x0E00
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#define SRC_SWAP_MSK 0xF1FF
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#define SRC_SWAP_MSK 0xF1FF
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// PIXEL OPERATION
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// PIXEL OPERATION
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#define GPU_PXOP_0 0x0000 // S
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#define GPU_PXOP_0 0x0000 // S
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#define GPU_PXOP_1 0x0020 // not S
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#define GPU_PXOP_1 0x0020 // not S
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#define GPU_PXOP_2 0x0040 // not D
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#define GPU_PXOP_2 0x0040 // not D
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#define GPU_PXOP_3 0x0060 // S and D
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#define GPU_PXOP_3 0x0060 // S and D
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#define GPU_PXOP_4 0x0080 // S or D
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#define GPU_PXOP_4 0x0080 // S or D
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#define GPU_PXOP_5 0x00A0 // S xor D
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#define GPU_PXOP_5 0x00A0 // S xor D
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#define GPU_PXOP_6 0x00C0 // not (S and D)
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#define GPU_PXOP_6 0x00C0 // not (S and D)
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#define GPU_PXOP_7 0x00E0 // not (S or D)
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#define GPU_PXOP_7 0x00E0 // not (S or D)
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#define GPU_PXOP_8 0x0100 // not (S xor D)
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#define GPU_PXOP_8 0x0100 // not (S xor D)
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#define GPU_PXOP_9 0x0120 // (not S) and D
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#define GPU_PXOP_9 0x0120 // (not S) and D
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#define GPU_PXOP_A 0x0140 // S and (not D)
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#define GPU_PXOP_A 0x0140 // S and (not D)
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#define GPU_PXOP_B 0x0160 // (not S) or D
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#define GPU_PXOP_B 0x0160 // (not S) or D
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#define GPU_PXOP_C 0x0180 // S or (not D)
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#define GPU_PXOP_C 0x0180 // S or (not D)
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#define GPU_PXOP_D 0x01A0 // Fill 0 if S not transparent (only COPY_TRANSPARENT command)
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#define GPU_PXOP_D 0x01A0 // Fill 0 if S not transparent (only COPY_TRANSPARENT command)
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#define GPU_PXOP_E 0x01C0 // Fill 1 if S not transparent (only COPY_TRANSPARENT command)
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#define GPU_PXOP_E 0x01C0 // Fill 1 if S not transparent (only COPY_TRANSPARENT command)
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#define GPU_PXOP_F 0x01E0 // Fill 'fill_color' if S not transparent (only COPY_TRANSPARENT command)
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#define GPU_PXOP_F 0x01E0 // Fill 'fill_color' if S not transparent (only COPY_TRANSPARENT command)
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#endif
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#endif
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