//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2001 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: tb_openMSP430_fpga.v
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// *File Name: tb_openMSP430_fpga.v
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//
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//
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// *Module Description:
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// *Module Description:
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// openMSP430 FPGA testbench
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// openMSP430 FPGA testbench
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 111 $
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// $Rev: 111 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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module tb_openMSP430_fpga;
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module tb_openMSP430_fpga;
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|
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//
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//
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// Wire & Register definition
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// Wire & Register definition
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//------------------------------
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//------------------------------
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|
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// Clock & Reset
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// Clock & Reset
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reg CLK_40MHz;
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reg CLK_40MHz;
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reg CLK_66MHz;
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reg CLK_66MHz;
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reg CLK_100MHz;
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reg CLK_100MHz;
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reg USER_RESET;
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reg USER_RESET;
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|
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// Slide Switches
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// Slide Switches
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reg SW4;
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reg SW4;
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reg SW3;
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reg SW3;
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reg SW2;
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reg SW2;
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reg SW1;
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reg SW1;
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// LEDs
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// LEDs
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wire LED4;
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wire LED4;
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wire LED3;
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wire LED3;
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wire LED2;
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wire LED2;
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wire LED1;
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wire LED1;
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// UART
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// UART
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reg UART_RXD;
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reg UART_RXD;
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wire UART_TXD;
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wire UART_TXD;
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// UART
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// UART
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wire PMOD1_P1;
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wire PMOD1_P1;
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reg PMOD1_P4;
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reg PMOD1_P4;
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|
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// Core debug signals
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// Core debug signals
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wire [8*32-1:0] i_state;
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wire [8*32-1:0] omsp0_i_state;
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wire [8*32-1:0] e_state;
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wire [8*32-1:0] omsp0_e_state;
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wire [31:0] inst_cycle;
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wire [31:0] omsp0_inst_cycle;
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wire [8*32-1:0] inst_full;
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wire [8*32-1:0] omsp0_inst_full;
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wire [31:0] inst_number;
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wire [31:0] omsp0_inst_number;
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wire [15:0] inst_pc;
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wire [15:0] omsp0_inst_pc;
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wire [8*32-1:0] inst_short;
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wire [8*32-1:0] omsp0_inst_short;
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wire [8*32-1:0] omsp1_i_state;
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wire [8*32-1:0] omsp1_e_state;
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wire [31:0] omsp1_inst_cycle;
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wire [8*32-1:0] omsp1_inst_full;
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wire [31:0] omsp1_inst_number;
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wire [15:0] omsp1_inst_pc;
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wire [8*32-1:0] omsp1_inst_short;
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// Testbench variables
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// Testbench variables
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integer i;
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integer i;
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integer error;
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integer error;
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reg stimulus_done;
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reg stimulus_done;
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//
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//
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// Include files
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// Include files
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//------------------------------
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//------------------------------
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// CPU & Memory registers
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// CPU & Memory registers
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`include "registers.v"
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`include "registers_omsp0.v"
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`include "registers_omsp1.v"
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// Verilog stimulus
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// Verilog stimulus
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`include "stimulus.v"
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`include "stimulus.v"
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|
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//
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//
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// Initialize Program Memory
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// Initialize Program Memory
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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// Read memory file
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// Read memory file
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#10 $readmemh("./pmem.mem", pmem);
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#10 $readmemh("./pmem.mem", pmem);
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// Update Xilinx memory banks
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// Update Xilinx memory banks
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for (i=0; i<2048; i=i+1)
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for (i=0; i<8192; i=i+1)
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begin
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begin
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dut.ram_16x2k_pmem.ram_inst.mem[i] = pmem[i];
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dut.ram_16x8k_dp_pmem_shared.ram_dp_inst.mem[i] = pmem[i];
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end
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end
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end
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end
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//
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//
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// Generate Clock & Reset
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// Generate Clock & Reset
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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CLK_40MHz = 1'b0;
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CLK_40MHz = 1'b0;
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forever #12.5 CLK_40MHz <= ~CLK_40MHz; // 40 MHz
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forever #12.5 CLK_40MHz <= ~CLK_40MHz; // 40 MHz
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end
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end
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initial
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initial
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begin
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begin
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CLK_66MHz = 1'b0;
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CLK_66MHz = 1'b0;
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forever #7.57 CLK_66MHz <= ~CLK_66MHz; // 66 MHz
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forever #7.57 CLK_66MHz <= ~CLK_66MHz; // 66 MHz
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end
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end
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initial
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initial
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begin
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begin
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CLK_100MHz = 1'b0;
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CLK_100MHz = 1'b0;
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forever #5 CLK_100MHz <= ~CLK_100MHz; // 100 MHz
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forever #5 CLK_100MHz <= ~CLK_100MHz; // 100 MHz
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end
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end
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initial
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initial
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begin
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begin
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USER_RESET = 1'b0;
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USER_RESET = 1'b0;
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#100 USER_RESET = 1'b1;
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#100 USER_RESET = 1'b1;
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#600 USER_RESET = 1'b0;
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#600 USER_RESET = 1'b0;
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end
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end
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|
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//
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//
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// Global initialization
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// Global initialization
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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error = 0;
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error = 0;
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stimulus_done = 1;
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stimulus_done = 1;
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SW4 = 1'b0; // Slide Switches
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SW4 = 1'b0; // Slide Switches
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SW3 = 1'b0;
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SW3 = 1'b0;
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SW2 = 1'b0;
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SW2 = 1'b0;
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SW1 = 1'b0;
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SW1 = 1'b0;
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UART_RXD = 1'b1; // UART
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UART_RXD = 1'b1; // UART
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PMOD1_P4 = 1'b1;
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PMOD1_P4 = 1'b1;
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end
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end
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//
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//
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// openMSP430 FPGA Instance
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// openMSP430 FPGA Instance
|
//----------------------------------
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//----------------------------------
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|
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openMSP430_fpga dut (
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openMSP430_fpga dut (
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|
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//----------------------------------------------
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//----------------------------------------------
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// User Reset Push Button
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// User Reset Push Button
|
//----------------------------------------------
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//----------------------------------------------
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.USER_RESET (USER_RESET),
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.USER_RESET (USER_RESET),
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|
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//----------------------------------------------
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//----------------------------------------------
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// Micron N25Q128 SPI Flash
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// Micron N25Q128 SPI Flash
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// This is a Multi-I/O Flash. Several pins
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// This is a Multi-I/O Flash. Several pins
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// have dual purposes depending on the mode.
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// have dual purposes depending on the mode.
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//----------------------------------------------
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//----------------------------------------------
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.SPI_SCK (),
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.SPI_SCK (),
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.SPI_CS_n (),
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.SPI_CS_n (),
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.SPI_MOSI_MISO0 (),
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.SPI_MOSI_MISO0 (),
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.SPI_MISO_MISO1 (),
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.SPI_MISO_MISO1 (),
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.SPI_Wn_MISO2 (),
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.SPI_Wn_MISO2 (),
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.SPI_HOLDn_MISO3 (),
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.SPI_HOLDn_MISO3 (),
|
|
|
//----------------------------------------------
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//----------------------------------------------
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// TI CDCE913 Triple-Output PLL Clock Chip
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// TI CDCE913 Triple-Output PLL Clock Chip
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// Y1: 40 MHz, USER_CLOCK can be used as
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// Y1: 40 MHz, USER_CLOCK can be used as
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// external configuration clock
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// external configuration clock
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// Y2: 66.667 MHz
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// Y2: 66.667 MHz
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// Y3: 100 MHz
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// Y3: 100 MHz
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//----------------------------------------------
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//----------------------------------------------
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.USER_CLOCK (CLK_40MHz),
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.USER_CLOCK (CLK_40MHz),
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.CLOCK_Y2 (CLK_66MHz),
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.CLOCK_Y2 (CLK_66MHz),
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.CLOCK_Y3 (CLK_100MHz),
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.CLOCK_Y3 (CLK_100MHz),
|
|
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//----------------------------------------------
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//----------------------------------------------
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// The following oscillator is not populated
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// The following oscillator is not populated
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// in production but the footprint is compatible
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// in production but the footprint is compatible
|
// with the Maxim DS1088LU
|
// with the Maxim DS1088LU
|
//----------------------------------------------
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//----------------------------------------------
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.BACKUP_CLK (1'b0),
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.BACKUP_CLK (1'b0),
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|
|
//----------------------------------------------
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//----------------------------------------------
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// User DIP Switch x4
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// User DIP Switch x4
|
//----------------------------------------------
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//----------------------------------------------
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.GPIO_DIP1 (SW1),
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.GPIO_DIP1 (SW1),
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.GPIO_DIP2 (SW2),
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.GPIO_DIP2 (SW2),
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.GPIO_DIP3 (SW3),
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.GPIO_DIP3 (SW3),
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.GPIO_DIP4 (SW4),
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.GPIO_DIP4 (SW4),
|
|
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//----------------------------------------------
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//----------------------------------------------
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// User LEDs
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// User LEDs
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//----------------------------------------------
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//----------------------------------------------
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.GPIO_LED1 (LED1),
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.GPIO_LED1 (LED1),
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.GPIO_LED2 (LED2),
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.GPIO_LED2 (LED2),
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.GPIO_LED3 (LED3),
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.GPIO_LED3 (LED3),
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.GPIO_LED4 (LED4),
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.GPIO_LED4 (LED4),
|
|
|
//----------------------------------------------
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//----------------------------------------------
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// Silicon Labs CP2102 USB-to-UART Bridge Chip
|
// Silicon Labs CP2102 USB-to-UART Bridge Chip
|
//----------------------------------------------
|
//----------------------------------------------
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.USB_RS232_RXD (UART_RXD),
|
.USB_RS232_RXD (UART_RXD),
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.USB_RS232_TXD (UART_TXD),
|
.USB_RS232_TXD (UART_TXD),
|
|
|
//----------------------------------------------
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//----------------------------------------------
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// Texas Instruments CDCE913 programming port
|
// Texas Instruments CDCE913 programming port
|
//----------------------------------------------
|
//----------------------------------------------
|
.SCL (),
|
.SCL (),
|
.SDA (),
|
.SDA (),
|
|
|
//----------------------------------------------
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//----------------------------------------------
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// Micron MT46H32M16LFBF-5 LPDDR
|
// Micron MT46H32M16LFBF-5 LPDDR
|
//----------------------------------------------
|
//----------------------------------------------
|
|
|
// Addresses
|
// Addresses
|
.LPDDR_A0 (),
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.LPDDR_A0 (),
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.LPDDR_A1 (),
|
.LPDDR_A1 (),
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.LPDDR_A2 (),
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.LPDDR_A2 (),
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.LPDDR_A3 (),
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.LPDDR_A3 (),
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.LPDDR_A4 (),
|
.LPDDR_A4 (),
|
.LPDDR_A5 (),
|
.LPDDR_A5 (),
|
.LPDDR_A6 (),
|
.LPDDR_A6 (),
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.LPDDR_A7 (),
|
.LPDDR_A7 (),
|
.LPDDR_A8 (),
|
.LPDDR_A8 (),
|
.LPDDR_A9 (),
|
.LPDDR_A9 (),
|
.LPDDR_A10 (),
|
.LPDDR_A10 (),
|
.LPDDR_A11 (),
|
.LPDDR_A11 (),
|
.LPDDR_A12 (),
|
.LPDDR_A12 (),
|
.LPDDR_BA0 (),
|
.LPDDR_BA0 (),
|
.LPDDR_BA1 (),
|
.LPDDR_BA1 (),
|
|
|
// Data
|
// Data
|
.LPDDR_DQ0 (),
|
.LPDDR_DQ0 (),
|
.LPDDR_DQ1 (),
|
.LPDDR_DQ1 (),
|
.LPDDR_DQ2 (),
|
.LPDDR_DQ2 (),
|
.LPDDR_DQ3 (),
|
.LPDDR_DQ3 (),
|
.LPDDR_DQ4 (),
|
.LPDDR_DQ4 (),
|
.LPDDR_DQ5 (),
|
.LPDDR_DQ5 (),
|
.LPDDR_DQ6 (),
|
.LPDDR_DQ6 (),
|
.LPDDR_DQ7 (),
|
.LPDDR_DQ7 (),
|
.LPDDR_DQ8 (),
|
.LPDDR_DQ8 (),
|
.LPDDR_DQ9 (),
|
.LPDDR_DQ9 (),
|
.LPDDR_DQ10 (),
|
.LPDDR_DQ10 (),
|
.LPDDR_DQ11 (),
|
.LPDDR_DQ11 (),
|
.LPDDR_DQ12 (),
|
.LPDDR_DQ12 (),
|
.LPDDR_DQ13 (),
|
.LPDDR_DQ13 (),
|
.LPDDR_DQ14 (),
|
.LPDDR_DQ14 (),
|
.LPDDR_DQ15 (),
|
.LPDDR_DQ15 (),
|
.LPDDR_LDM (),
|
.LPDDR_LDM (),
|
.LPDDR_UDM (),
|
.LPDDR_UDM (),
|
.LPDDR_LDQS (),
|
.LPDDR_LDQS (),
|
.LPDDR_UDQS (),
|
.LPDDR_UDQS (),
|
|
|
// Clock
|
// Clock
|
.LPDDR_CK_N (),
|
.LPDDR_CK_N (),
|
.LPDDR_CK_P (),
|
.LPDDR_CK_P (),
|
.LPDDR_CKE (),
|
.LPDDR_CKE (),
|
|
|
// Control
|
// Control
|
.LPDDR_CAS_n (),
|
.LPDDR_CAS_n (),
|
.LPDDR_RAS_n (),
|
.LPDDR_RAS_n (),
|
.LPDDR_WE_n (),
|
.LPDDR_WE_n (),
|
.LPDDR_RZQ (),
|
.LPDDR_RZQ (),
|
|
|
//----------------------------------------------
|
//----------------------------------------------
|
// National Semiconductor DP83848J 10/100 Ethernet PHY
|
// National Semiconductor DP83848J 10/100 Ethernet PHY
|
// Pull-ups on RXD are necessary to set the PHY AD to 11110b.
|
// Pull-ups on RXD are necessary to set the PHY AD to 11110b.
|
// Must keep the PHY from defaulting to PHY AD = 00000b
|
// Must keep the PHY from defaulting to PHY AD = 00000b
|
// because this is Isolate Mode
|
// because this is Isolate Mode
|
//----------------------------------------------
|
//----------------------------------------------
|
.ETH_COL (1'b0),
|
.ETH_COL (1'b0),
|
.ETH_CRS (1'b0),
|
.ETH_CRS (1'b0),
|
.ETH_MDC (),
|
.ETH_MDC (),
|
.ETH_MDIO (),
|
.ETH_MDIO (),
|
.ETH_RESET_n (),
|
.ETH_RESET_n (),
|
.ETH_RX_CLK (1'b0),
|
.ETH_RX_CLK (1'b0),
|
.ETH_RX_D0 (1'b0),
|
.ETH_RX_D0 (1'b0),
|
.ETH_RX_D1 (1'b0),
|
.ETH_RX_D1 (1'b0),
|
.ETH_RX_D2 (1'b0),
|
.ETH_RX_D2 (1'b0),
|
.ETH_RX_D3 (1'b0),
|
.ETH_RX_D3 (1'b0),
|
.ETH_RX_DV (1'b0),
|
.ETH_RX_DV (1'b0),
|
.ETH_RX_ER (1'b0),
|
.ETH_RX_ER (1'b0),
|
.ETH_TX_CLK (1'b0),
|
.ETH_TX_CLK (1'b0),
|
.ETH_TX_D0 (),
|
.ETH_TX_D0 (),
|
.ETH_TX_D1 (),
|
.ETH_TX_D1 (),
|
.ETH_TX_D2 (),
|
.ETH_TX_D2 (),
|
.ETH_TX_D3 (),
|
.ETH_TX_D3 (),
|
.ETH_TX_EN (),
|
.ETH_TX_EN (),
|
|
|
//----------------------------------------------
|
//----------------------------------------------
|
// Peripheral Modules (PMODs) and GPIO
|
// Peripheral Modules (PMODs) and GPIO
|
// https://www.digilentinc.com/PMODs
|
// https://www.digilentinc.com/PMODs
|
//----------------------------------------------
|
//----------------------------------------------
|
|
|
// Connector J5
|
// Connector J5
|
.PMOD1_P1 (PMOD1_P1), // Serial Debug Interface TX
|
.PMOD1_P1 (PMOD1_P1), // Serial Debug Interface TX
|
.PMOD1_P2 (),
|
.PMOD1_P2 (),
|
.PMOD1_P3 (),
|
.PMOD1_P3 (),
|
.PMOD1_P4 (PMOD1_P4), // Serial Debug Interface RX
|
.PMOD1_P4 (PMOD1_P4), // Serial Debug Interface RX
|
.PMOD1_P7 (),
|
.PMOD1_P7 (),
|
.PMOD1_P8 (),
|
.PMOD1_P8 (),
|
.PMOD1_P9 (),
|
.PMOD1_P9 (),
|
.PMOD1_P10 (),
|
.PMOD1_P10 (),
|
|
|
// Connector J4
|
// Connector J4
|
.PMOD2_P1 (),
|
.PMOD2_P1 (),
|
.PMOD2_P2 (),
|
.PMOD2_P2 (),
|
.PMOD2_P3 (),
|
.PMOD2_P3 (),
|
.PMOD2_P4 (),
|
.PMOD2_P4 (),
|
.PMOD2_P7 (),
|
.PMOD2_P7 (),
|
.PMOD2_P8 (),
|
.PMOD2_P8 (),
|
.PMOD2_P9 (),
|
.PMOD2_P9 (),
|
.PMOD2_P10 ()
|
.PMOD2_P10 ()
|
);
|
);
|
|
|
|
|
// Debug utility signals
|
// Debug utility signals
|
//----------------------------------------
|
//----------------------------------------
|
msp_debug msp_debug_0 (
|
msp_debug msp_debug_omsp0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.e_state (e_state), // Execution state
|
.e_state (omsp0_e_state), // Execution state
|
.i_state (i_state), // Instruction fetch state
|
.i_state (omsp0_i_state), // Instruction fetch state
|
.inst_cycle (inst_cycle), // Cycle number within current instruction
|
.inst_cycle (omsp0_inst_cycle), // Cycle number within current instruction
|
.inst_full (inst_full), // Currently executed instruction (full version)
|
.inst_full (omsp0_inst_full), // Currently executed instruction (full version)
|
.inst_number (inst_number), // Instruction number since last system reset
|
.inst_number (omsp0_inst_number), // Instruction number since last system reset
|
.inst_pc (inst_pc), // Instruction Program counter
|
.inst_pc (omsp0_inst_pc), // Instruction Program counter
|
.inst_short (inst_short), // Currently executed instruction (short version)
|
.inst_short (omsp0_inst_short), // Currently executed instruction (short version)
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.core_select (0) // Core selection
|
.puc_rst (puc_rst) // Main system reset
|
);
|
|
|
|
msp_debug msp_debug_omsp1 (
|
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// OUTPUTs
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.e_state (omsp1_e_state), // Execution state
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.i_state (omsp1_i_state), // Instruction fetch state
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.inst_cycle (omsp1_inst_cycle), // Cycle number within current instruction
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.inst_full (omsp1_inst_full), // Currently executed instruction (full version)
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.inst_number (omsp1_inst_number), // Instruction number since last system reset
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.inst_pc (omsp1_inst_pc), // Instruction Program counter
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.inst_short (omsp1_inst_short), // Currently executed instruction (short version)
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// INPUTs
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.core_select (1) // Core selection
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);
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);
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//
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//
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// Generate Waveform
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// Generate Waveform
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//----------------------------------------
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//----------------------------------------
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initial
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initial
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begin
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begin
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`ifdef VPD_FILE
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`ifdef VPD_FILE
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$vcdplusfile("tb_openMSP430_fpga.vpd");
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$vcdplusfile("tb_openMSP430_fpga.vpd");
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$vcdpluson();
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$vcdpluson();
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`else
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`else
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`ifdef TRN_FILE
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`ifdef TRN_FILE
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$recordfile ("tb_openMSP430_fpga.trn");
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$recordfile ("tb_openMSP430_fpga.trn");
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$recordvars;
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$recordvars;
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`else
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`else
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$dumpfile("tb_openMSP430_fpga.vcd");
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$dumpfile("tb_openMSP430_fpga.vcd");
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$dumpvars(0, tb_openMSP430_fpga);
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$dumpvars(0, tb_openMSP430_fpga);
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`endif
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`endif
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`endif
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`endif
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end
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end
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//
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//
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// End of simulation
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// End of simulation
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//----------------------------------------
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//----------------------------------------
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initial // Timeout
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initial // Timeout
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begin
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begin
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#500000;
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#500000;
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| SIMULATION FAILED |");
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$display("| SIMULATION FAILED |");
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$display("| (simulation Timeout) |");
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$display("| (simulation Timeout) |");
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$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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end
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end
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initial // Normal end of test
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initial // Normal end of test
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begin
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begin
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@(inst_pc===16'hffff)
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@(omsp0_inst_pc===16'hffff)
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$display(" ===============================================");
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$display(" ===============================================");
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if (error!=0)
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if (error!=0)
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begin
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begin
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$display("| SIMULATION FAILED |");
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$display("| SIMULATION FAILED |");
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$display("| (some verilog stimulus checks failed) |");
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$display("| (some verilog stimulus checks failed) |");
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end
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end
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else if (~stimulus_done)
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else if (~stimulus_done)
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begin
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begin
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$display("| SIMULATION FAILED |");
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$display("| SIMULATION FAILED |");
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$display("| (the verilog stimulus didn't complete) |");
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$display("| (the verilog stimulus didn't complete) |");
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end
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end
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else
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else
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begin
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begin
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$display("| SIMULATION PASSED |");
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$display("| SIMULATION PASSED |");
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end
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end
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$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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end
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end
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//
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//
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// Tasks Definition
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// Tasks Definition
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//------------------------------
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//------------------------------
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task tb_error;
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task tb_error;
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input [65*8:0] error_string;
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input [65*8:0] error_string;
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begin
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begin
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$display("ERROR: %s %t", error_string, $time);
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$display("ERROR: %s %t", error_string, $time);
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error = error+1;
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error = error+1;
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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