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verilog work ../../../bench/verilog/tb_openMSP430_fpga.v
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verilog work ../../../bench/verilog/tb_openMSP430_fpga.v
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verilog work ../../../bench/verilog/msp_debug.v
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verilog work ../../../bench/verilog/msp_debug.v
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verilog work ../../../bench/verilog/glbl.v
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verilog work ../../../bench/verilog/glbl.v
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verilog work ../../../bench/verilog/ram_16x512.v
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verilog work ../../../bench/verilog/ram_16x512.v
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verilog work ../../../bench/verilog/ram_16x2k.v
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verilog work ../../../bench/verilog/ram_16x2k.v
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verilog work ../../../bench/verilog/ram.v
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verilog work ../../../bench/verilog/ram.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUFG.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IBUFG.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/BUFG.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/BUFG.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/OBUF.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/OBUF.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IOBUF.v
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verilog work /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/IOBUF.v
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verilog work ../../../rtl/verilog/openMSP430_fpga.v
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verilog work ../../../rtl/verilog/openMSP430_fpga.v
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verilog work ../../../rtl/verilog/omsp_system_0.v
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verilog work ../../../rtl/verilog/omsp_system_0.v
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verilog work ../../../rtl/verilog/io_mux.v
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verilog work ../../../rtl/verilog/io_mux.v
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verilog work ../../../rtl/verilog/omsp_uart.v
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verilog work ../../../rtl/verilog/omsp_uart.v
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verilog work ../../../rtl/verilog/openmsp430/openMSP430.v
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verilog work ../../../rtl/verilog/openmsp430/openMSP430.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_frontend.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_frontend.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_execution_unit.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_execution_unit.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_register_file.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_register_file.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_alu.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_alu.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_sfr.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_sfr.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_mem_backbone.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_mem_backbone.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_clock_module.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_clock_module.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_dbg.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_dbg.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_watchdog.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_watchdog.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_multiplier.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_multiplier.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_sync_reset.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_sync_reset.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_sync_cell.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_sync_cell.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_scan_mux.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_scan_mux.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_and_gate.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_and_gate.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_wakeup_cell.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_wakeup_cell.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_clock_gate.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_clock_gate.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_clock_mux.v
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verilog work ../../../rtl/verilog/openmsp430/omsp_clock_mux.v
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verilog work ../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
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verilog work ../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
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verilog work ../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
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verilog work ../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
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