//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2001 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: tb_openMSP430_fpga.v
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// *File Name: tb_openMSP430_fpga.v
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//
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//
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// *Module Description:
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// *Module Description:
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// openMSP430 FPGA testbench
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// openMSP430 FPGA testbench
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 94 $
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// $Rev: 98 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-02-24 21:33:35 +0100 (Thu, 24 Feb 2011) $
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// $LastChangedDate: 2011-02-28 21:20:51 +0100 (Mon, 28 Feb 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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|
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module tb_openMSP430_fpga;
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module tb_openMSP430_fpga;
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|
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//
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//
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// Wire & Register definition
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// Wire & Register definition
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//------------------------------
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//------------------------------
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// Clock & Reset
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// Clock & Reset
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reg CLK_50MHz;
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reg CLK_50MHz;
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reg RESET;
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reg RESET;
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|
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// Slide Switches
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// Slide Switches
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reg SW7;
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reg SW7;
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reg SW6;
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reg SW6;
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reg SW5;
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reg SW5;
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reg SW4;
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reg SW4;
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reg SW3;
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reg SW3;
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reg SW2;
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reg SW2;
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reg SW1;
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reg SW1;
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reg SW0;
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reg SW0;
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// Push Button Switches
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// Push Button Switches
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reg BTN2;
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reg BTN2;
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reg BTN1;
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reg BTN1;
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reg BTN0;
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reg BTN0;
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// LEDs
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// LEDs
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wire LED7;
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wire LED7;
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wire LED6;
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wire LED6;
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wire LED5;
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wire LED5;
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wire LED4;
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wire LED4;
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wire LED3;
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wire LED3;
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wire LED2;
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wire LED2;
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wire LED1;
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wire LED1;
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wire LED0;
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wire LED0;
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// Four-Sigit, Seven-Segment LED Display
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// Four-Sigit, Seven-Segment LED Display
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wire SEG_A;
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wire SEG_A;
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wire SEG_B;
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wire SEG_B;
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wire SEG_C;
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wire SEG_C;
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wire SEG_D;
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wire SEG_D;
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wire SEG_E;
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wire SEG_E;
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wire SEG_F;
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wire SEG_F;
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wire SEG_G;
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wire SEG_G;
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wire SEG_DP;
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wire SEG_DP;
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wire SEG_AN0;
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wire SEG_AN0;
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wire SEG_AN1;
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wire SEG_AN1;
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wire SEG_AN2;
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wire SEG_AN2;
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wire SEG_AN3;
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wire SEG_AN3;
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// UART
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// UART
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reg UART_RXD;
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reg UART_RXD;
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wire UART_TXD;
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wire UART_TXD;
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// Core debug signals
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// Core debug signals
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wire [8*32-1:0] i_state;
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wire [8*32-1:0] i_state;
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wire [8*32-1:0] e_state;
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wire [8*32-1:0] e_state;
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wire [31:0] inst_cycle;
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wire [31:0] inst_cycle;
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wire [8*32-1:0] inst_full;
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wire [8*32-1:0] inst_full;
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wire [31:0] inst_number;
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wire [31:0] inst_number;
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wire [15:0] inst_pc;
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wire [15:0] inst_pc;
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wire [8*32-1:0] inst_short;
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wire [8*32-1:0] inst_short;
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// Testbench variables
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// Testbench variables
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integer i;
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integer i;
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integer error;
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integer error;
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reg stimulus_done;
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reg stimulus_done;
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//
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//
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// Include files
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// Include files
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//------------------------------
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//------------------------------
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// CPU & Memory registers
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// CPU & Memory registers
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`include "registers.v"
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`include "registers.v"
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// Verilog stimulus
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// Verilog stimulus
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`include "stimulus.v"
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`include "stimulus.v"
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//
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//
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// Initialize Program Memory
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// Initialize Program Memory
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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// Read memory file
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// Read memory file
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#10 $readmemh("./pmem.mem", pmem);
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#10 $readmemh("./pmem.mem", pmem);
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// Update Xilinx memory banks
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// Update Xilinx memory banks
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for (i=0; i<2048; i=i+1)
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for (i=0; i<2048; i=i+1)
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begin
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begin
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dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
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dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
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dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
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dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
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end
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end
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end
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end
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//
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//
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// Generate Clock & Reset
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// Generate Clock & Reset
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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CLK_50MHz = 1'b0;
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CLK_50MHz = 1'b0;
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forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz
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forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz
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end
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end
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initial
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initial
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begin
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begin
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RESET = 1'b0;
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RESET = 1'b0;
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#100 RESET = 1'b1;
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#100 RESET = 1'b1;
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#600 RESET = 1'b0;
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#600 RESET = 1'b0;
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end
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end
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//
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//
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// Global initialization
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// Global initialization
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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error = 0;
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error = 0;
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stimulus_done = 1;
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stimulus_done = 1;
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SW7 = 1'b0; // Slide Switches
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SW7 = 1'b0; // Slide Switches
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SW6 = 1'b0;
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SW6 = 1'b0;
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SW5 = 1'b0;
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SW5 = 1'b0;
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SW4 = 1'b0;
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SW4 = 1'b0;
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SW3 = 1'b0;
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SW3 = 1'b0;
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SW2 = 1'b0;
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SW2 = 1'b0;
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SW1 = 1'b0;
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SW1 = 1'b0;
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SW0 = 1'b0;
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SW0 = 1'b0;
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BTN2 = 1'b0; // Push Button Switches
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BTN2 = 1'b0; // Push Button Switches
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BTN1 = 1'b0;
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BTN1 = 1'b0;
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BTN0 = 1'b0;
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BTN0 = 1'b0;
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UART_RXD = 1'b0; // UART
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UART_RXD = 1'b0; // UART
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end
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end
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//
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//
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// openMSP430 FPGA Instance
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// openMSP430 FPGA Instance
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//----------------------------------
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//----------------------------------
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|
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openMSP430_fpga dut (
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openMSP430_fpga dut (
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// Clock Sources
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// Clock Sources
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.CLK_50MHz (CLK_50MHz),
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.CLK_50MHz (CLK_50MHz),
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.CLK_SOCKET (1'b0),
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.CLK_SOCKET (1'b0),
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// Slide Switches
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// Slide Switches
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.SW7 (SW7),
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.SW7 (SW7),
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.SW6 (SW6),
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.SW6 (SW6),
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.SW5 (SW5),
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.SW5 (SW5),
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.SW4 (SW4),
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.SW4 (SW4),
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.SW3 (SW3),
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.SW3 (SW3),
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.SW2 (SW2),
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.SW2 (SW2),
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.SW1 (SW1),
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.SW1 (SW1),
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.SW0 (SW0),
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.SW0 (SW0),
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// Push Button Switches
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// Push Button Switches
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.BTN3 (RESET),
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.BTN3 (RESET),
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.BTN2 (BTN2),
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.BTN2 (BTN2),
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.BTN1 (BTN1),
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.BTN1 (BTN1),
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.BTN0 (BTN0),
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.BTN0 (BTN0),
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// LEDs
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// LEDs
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.LED7 (LED7),
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.LED7 (LED7),
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.LED6 (LED6),
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.LED6 (LED6),
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.LED5 (LED5),
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.LED5 (LED5),
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.LED4 (LED4),
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.LED4 (LED4),
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.LED3 (LED3),
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.LED3 (LED3),
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.LED2 (LED2),
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.LED2 (LED2),
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.LED1 (LED1),
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.LED1 (LED1),
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.LED0 (LED0),
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.LED0 (LED0),
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// Four-Sigit, Seven-Segment LED Display
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// Four-Sigit, Seven-Segment LED Display
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.SEG_A (SEG_A),
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.SEG_A (SEG_A),
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.SEG_B (SEG_B),
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.SEG_B (SEG_B),
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.SEG_C (SEG_C),
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.SEG_C (SEG_C),
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.SEG_D (SEG_D),
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.SEG_D (SEG_D),
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.SEG_E (SEG_E),
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.SEG_E (SEG_E),
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.SEG_F (SEG_F),
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.SEG_F (SEG_F),
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.SEG_G (SEG_G),
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.SEG_G (SEG_G),
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.SEG_DP (SEG_DP),
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.SEG_DP (SEG_DP),
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.SEG_AN0 (SEG_AN0),
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.SEG_AN0 (SEG_AN0),
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.SEG_AN1 (SEG_AN1),
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.SEG_AN1 (SEG_AN1),
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.SEG_AN2 (SEG_AN2),
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.SEG_AN2 (SEG_AN2),
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.SEG_AN3 (SEG_AN3),
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.SEG_AN3 (SEG_AN3),
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|
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// RS-232 Port
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// RS-232 Port
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.UART_RXD (UART_RXD),
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.UART_RXD (UART_RXD),
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.UART_TXD (UART_TXD),
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.UART_TXD (UART_TXD),
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.UART_RXD_A (1'b0),
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.UART_RXD_A (1'b0),
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.UART_TXD_A (UART_TXD_A),
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.UART_TXD_A (UART_TXD_A),
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|
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// PS/2 Mouse/Keyboard Port
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// PS/2 Mouse/Keyboard Port
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.PS2_D (PS2_D),
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.PS2_D (PS2_D),
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.PS2_C (PS2_C),
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.PS2_C (PS2_C),
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|
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// Fast, Asynchronous SRAM
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// Fast, Asynchronous SRAM
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.SRAM_A17 (SRAM_A17), // Address Bus Connections
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.SRAM_A17 (SRAM_A17), // Address Bus Connections
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.SRAM_A16 (SRAM_A16),
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.SRAM_A16 (SRAM_A16),
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.SRAM_A15 (SRAM_A15),
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.SRAM_A15 (SRAM_A15),
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.SRAM_A14 (SRAM_A14),
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.SRAM_A14 (SRAM_A14),
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.SRAM_A13 (SRAM_A13),
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.SRAM_A13 (SRAM_A13),
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.SRAM_A12 (SRAM_A12),
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.SRAM_A12 (SRAM_A12),
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.SRAM_A11 (SRAM_A11),
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.SRAM_A11 (SRAM_A11),
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.SRAM_A10 (SRAM_A10),
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.SRAM_A10 (SRAM_A10),
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.SRAM_A9 (SRAM_A9),
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.SRAM_A9 (SRAM_A9),
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.SRAM_A8 (SRAM_A8),
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.SRAM_A8 (SRAM_A8),
|
.SRAM_A7 (SRAM_A7),
|
.SRAM_A7 (SRAM_A7),
|
.SRAM_A6 (SRAM_A6),
|
.SRAM_A6 (SRAM_A6),
|
.SRAM_A5 (SRAM_A5),
|
.SRAM_A5 (SRAM_A5),
|
.SRAM_A4 (SRAM_A4),
|
.SRAM_A4 (SRAM_A4),
|
.SRAM_A3 (SRAM_A3),
|
.SRAM_A3 (SRAM_A3),
|
.SRAM_A2 (SRAM_A2),
|
.SRAM_A2 (SRAM_A2),
|
.SRAM_A1 (SRAM_A1),
|
.SRAM_A1 (SRAM_A1),
|
.SRAM_A0 (SRAM_A0),
|
.SRAM_A0 (SRAM_A0),
|
.SRAM_OE (SRAM_OE), // Write enable and output enable control signals
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.SRAM_OE (SRAM_OE), // Write enable and output enable control signals
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.SRAM_WE (SRAM_WE),
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.SRAM_WE (SRAM_WE),
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.SRAM0_IO15 (SRAM0_IO15), // SRAM Data signals, chip enables, and byte enables
|
.SRAM0_IO15 (SRAM0_IO15), // SRAM Data signals, chip enables, and byte enables
|
.SRAM0_IO14 (SRAM0_IO14),
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.SRAM0_IO14 (SRAM0_IO14),
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.SRAM0_IO13 (SRAM0_IO13),
|
.SRAM0_IO13 (SRAM0_IO13),
|
.SRAM0_IO12 (SRAM0_IO12),
|
.SRAM0_IO12 (SRAM0_IO12),
|
.SRAM0_IO11 (SRAM0_IO11),
|
.SRAM0_IO11 (SRAM0_IO11),
|
.SRAM0_IO10 (SRAM0_IO10),
|
.SRAM0_IO10 (SRAM0_IO10),
|
.SRAM0_IO9 (SRAM0_IO9),
|
.SRAM0_IO9 (SRAM0_IO9),
|
.SRAM0_IO8 (SRAM0_IO8),
|
.SRAM0_IO8 (SRAM0_IO8),
|
.SRAM0_IO7 (SRAM0_IO7),
|
.SRAM0_IO7 (SRAM0_IO7),
|
.SRAM0_IO6 (SRAM0_IO6),
|
.SRAM0_IO6 (SRAM0_IO6),
|
.SRAM0_IO5 (SRAM0_IO5),
|
.SRAM0_IO5 (SRAM0_IO5),
|
.SRAM0_IO4 (SRAM0_IO4),
|
.SRAM0_IO4 (SRAM0_IO4),
|
.SRAM0_IO3 (SRAM0_IO3),
|
.SRAM0_IO3 (SRAM0_IO3),
|
.SRAM0_IO2 (SRAM0_IO2),
|
.SRAM0_IO2 (SRAM0_IO2),
|
.SRAM0_IO1 (SRAM0_IO1),
|
.SRAM0_IO1 (SRAM0_IO1),
|
.SRAM0_IO0 (SRAM0_IO0),
|
.SRAM0_IO0 (SRAM0_IO0),
|
.SRAM0_CE1 (SRAM0_CE1),
|
.SRAM0_CE1 (SRAM0_CE1),
|
.SRAM0_UB1 (SRAM0_UB1),
|
.SRAM0_UB1 (SRAM0_UB1),
|
.SRAM0_LB1 (SRAM0_LB1),
|
.SRAM0_LB1 (SRAM0_LB1),
|
.SRAM1_IO15 (SRAM1_IO15),
|
.SRAM1_IO15 (SRAM1_IO15),
|
.SRAM1_IO14 (SRAM1_IO14),
|
.SRAM1_IO14 (SRAM1_IO14),
|
.SRAM1_IO13 (SRAM1_IO13),
|
.SRAM1_IO13 (SRAM1_IO13),
|
.SRAM1_IO12 (SRAM1_IO12),
|
.SRAM1_IO12 (SRAM1_IO12),
|
.SRAM1_IO11 (SRAM1_IO11),
|
.SRAM1_IO11 (SRAM1_IO11),
|
.SRAM1_IO10 (SRAM1_IO10),
|
.SRAM1_IO10 (SRAM1_IO10),
|
.SRAM1_IO9 (SRAM1_IO9),
|
.SRAM1_IO9 (SRAM1_IO9),
|
.SRAM1_IO8 (SRAM1_IO8),
|
.SRAM1_IO8 (SRAM1_IO8),
|
.SRAM1_IO7 (SRAM1_IO7),
|
.SRAM1_IO7 (SRAM1_IO7),
|
.SRAM1_IO6 (SRAM1_IO6),
|
.SRAM1_IO6 (SRAM1_IO6),
|
.SRAM1_IO5 (SRAM1_IO5),
|
.SRAM1_IO5 (SRAM1_IO5),
|
.SRAM1_IO4 (SRAM1_IO4),
|
.SRAM1_IO4 (SRAM1_IO4),
|
.SRAM1_IO3 (SRAM1_IO3),
|
.SRAM1_IO3 (SRAM1_IO3),
|
.SRAM1_IO2 (SRAM1_IO2),
|
.SRAM1_IO2 (SRAM1_IO2),
|
.SRAM1_IO1 (SRAM1_IO1),
|
.SRAM1_IO1 (SRAM1_IO1),
|
.SRAM1_IO0 (SRAM1_IO0),
|
.SRAM1_IO0 (SRAM1_IO0),
|
.SRAM1_CE2 (SRAM1_CE2),
|
.SRAM1_CE2 (SRAM1_CE2),
|
.SRAM1_UB2 (SRAM1_UB2),
|
.SRAM1_UB2 (SRAM1_UB2),
|
.SRAM1_LB2 (SRAM1_LB2),
|
.SRAM1_LB2 (SRAM1_LB2),
|
|
|
// VGA Port
|
// VGA Port
|
.VGA_R (VGA_R),
|
.VGA_R (VGA_R),
|
.VGA_G (VGA_G),
|
.VGA_G (VGA_G),
|
.VGA_B (VGA_B),
|
.VGA_B (VGA_B),
|
.VGA_HS (VGA_HS),
|
.VGA_HS (VGA_HS),
|
.VGA_VS (VGA_VS)
|
.VGA_VS (VGA_VS)
|
);
|
);
|
|
|
|
|
//
|
//
|
// Debug utility signals
|
// Debug utility signals
|
//----------------------------------------
|
//----------------------------------------
|
msp_debug msp_debug_0 (
|
msp_debug msp_debug_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.e_state (e_state), // Execution state
|
.e_state (e_state), // Execution state
|
.i_state (i_state), // Instruction fetch state
|
.i_state (i_state), // Instruction fetch state
|
.inst_cycle (inst_cycle), // Cycle number within current instruction
|
.inst_cycle (inst_cycle), // Cycle number within current instruction
|
.inst_full (inst_full), // Currently executed instruction (full version)
|
.inst_full (inst_full), // Currently executed instruction (full version)
|
.inst_number (inst_number), // Instruction number since last system reset
|
.inst_number (inst_number), // Instruction number since last system reset
|
.inst_pc (inst_pc), // Instruction Program counter
|
.inst_pc (inst_pc), // Instruction Program counter
|
.inst_short (inst_short), // Currently executed instruction (short version)
|
.inst_short (inst_short), // Currently executed instruction (short version)
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.puc (puc) // Main system reset
|
.puc (puc) // Main system reset
|
);
|
);
|
|
|
//
|
//
|
// Generate Waveform
|
// Generate Waveform
|
//----------------------------------------
|
//----------------------------------------
|
initial
|
initial
|
begin
|
begin
|
`ifdef VPD_FILE
|
`ifdef VPD_FILE
|
$vcdplusfile("tb_openMSP430_fpga.vpd");
|
$vcdplusfile("tb_openMSP430_fpga.vpd");
|
$vcdpluson();
|
$vcdpluson();
|
`else
|
`else
|
|
`ifdef TRN_FILE
|
|
$recordfile ("tb_openMSP430_fpga.trn");
|
|
$recordvars;
|
|
`else
|
$dumpfile("tb_openMSP430_fpga.vcd");
|
$dumpfile("tb_openMSP430_fpga.vcd");
|
$dumpvars(0, tb_openMSP430_fpga);
|
$dumpvars(0, tb_openMSP430_fpga);
|
`endif
|
`endif
|
|
`endif
|
end
|
end
|
|
|
//
|
//
|
// End of simulation
|
// End of simulation
|
//----------------------------------------
|
//----------------------------------------
|
|
|
initial // Timeout
|
initial // Timeout
|
begin
|
begin
|
#500000;
|
#500000;
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$display("| SIMULATION FAILED |");
|
$display("| SIMULATION FAILED |");
|
$display("| (simulation Timeout) |");
|
$display("| (simulation Timeout) |");
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$finish;
|
$finish;
|
end
|
end
|
|
|
initial // Normal end of test
|
initial // Normal end of test
|
begin
|
begin
|
@(inst_pc===16'hffff)
|
@(inst_pc===16'hffff)
|
$display(" ===============================================");
|
$display(" ===============================================");
|
if (error!=0)
|
if (error!=0)
|
begin
|
begin
|
$display("| SIMULATION FAILED |");
|
$display("| SIMULATION FAILED |");
|
$display("| (some verilog stimulus checks failed) |");
|
$display("| (some verilog stimulus checks failed) |");
|
end
|
end
|
else if (~stimulus_done)
|
else if (~stimulus_done)
|
begin
|
begin
|
$display("| SIMULATION FAILED |");
|
$display("| SIMULATION FAILED |");
|
$display("| (the verilog stimulus didn't complete) |");
|
$display("| (the verilog stimulus didn't complete) |");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("| SIMULATION PASSED |");
|
$display("| SIMULATION PASSED |");
|
end
|
end
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$finish;
|
$finish;
|
end
|
end
|
|
|
|
|
//
|
//
|
// Tasks Definition
|
// Tasks Definition
|
//------------------------------
|
//------------------------------
|
|
|
task tb_error;
|
task tb_error;
|
input [65*8:0] error_string;
|
input [65*8:0] error_string;
|
begin
|
begin
|
$display("ERROR: %s %t", error_string, $time);
|
$display("ERROR: %s %t", error_string, $time);
|
error = error+1;
|
error = error+1;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
endmodule
|
endmodule
|
|
|
