URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [coregen.cgp] - Diff between revs 2 and 28

Rev 2	Rev 28
`# Date: Mon Apr 6 14:50:01 2009`	`# Date: Mon Apr 6 14:50:01 2009`
`SET addpads = False`	`SET addpads = False`
`SET asysymbol = True`	`SET asysymbol = True`
`SET busformat = BusFormatAngleBracketNotRipped`	`SET busformat = BusFormatAngleBracketNotRipped`
`SET createndf = False`	`SET createndf = False`
`SET designentry = Verilog`	`SET designentry = Verilog`
`SET device = xc3s200`	`SET device = xc3s200`
`SET devicefamily = spartan3`	`SET devicefamily = spartan3`
`SET flowvendor = Foundation_iSE`	`SET flowvendor = Foundation_iSE`
`SET formalverification = False`	`SET formalverification = False`
`SET foundationsym = False`	`SET foundationsym = False`
`SET implementationfiletype = Ngc`	`SET implementationfiletype = Ngc`
`SET package = ft256`	`SET package = ft256`
`SET removerpms = False`	`SET removerpms = False`
`SET simulationfiles = Behavioral`	`SET simulationfiles = Behavioral`
`SET speedgrade = -4`	`SET speedgrade = -4`
`SET verilogsim = True`	`SET verilogsim = True`
`SET vhdlsim = False`	`SET vhdlsim = False`
`SET workingdirectory = /home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/tmp`	`SET workingdirectory = /home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/tmp`