##############################################################
|
##############################################################
|
#
|
#
|
# Xilinx Core Generator version K.31
|
# Xilinx Core Generator version K.31
|
# Date: Mon Apr 6 14:52:29 2009
|
# Date: Mon Apr 6 14:52:29 2009
|
#
|
#
|
##############################################################
|
##############################################################
|
#
|
#
|
# This file contains the customisation parameters for a
|
# This file contains the customisation parameters for a
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
# that you do not manually alter this file as it may cause
|
# that you do not manually alter this file as it may cause
|
# unexpected and unsupported behavior.
|
# unexpected and unsupported behavior.
|
#
|
#
|
##############################################################
|
##############################################################
|
#
|
#
|
# BEGIN Project Options
|
# BEGIN Project Options
|
SET addpads = False
|
SET addpads = False
|
SET asysymbol = True
|
SET asysymbol = True
|
SET busformat = BusFormatAngleBracketNotRipped
|
SET busformat = BusFormatAngleBracketNotRipped
|
SET createndf = False
|
SET createndf = False
|
SET designentry = Verilog
|
SET designentry = Verilog
|
SET device = xc3s200
|
SET device = xc3s200
|
SET devicefamily = spartan3
|
SET devicefamily = spartan3
|
SET flowvendor = Foundation_iSE
|
SET flowvendor = Foundation_iSE
|
SET formalverification = False
|
SET formalverification = False
|
SET foundationsym = False
|
SET foundationsym = False
|
SET implementationfiletype = Ngc
|
SET implementationfiletype = Ngc
|
SET package = ft256
|
SET package = ft256
|
SET removerpms = False
|
SET removerpms = False
|
SET simulationfiles = Behavioral
|
SET simulationfiles = Behavioral
|
SET speedgrade = -4
|
SET speedgrade = -4
|
SET verilogsim = True
|
SET verilogsim = True
|
SET vhdlsim = False
|
SET vhdlsim = False
|
# END Project Options
|
# END Project Options
|
# BEGIN Select
|
# BEGIN Select
|
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
|
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
|
# END Select
|
# END Select
|
# BEGIN Parameters
|
# BEGIN Parameters
|
CSET active_clock_edge=Rising_Edge_Triggered
|
CSET active_clock_edge=Rising_Edge_Triggered
|
CSET additional_output_pipe_stages=0
|
CSET additional_output_pipe_stages=0
|
CSET component_name=ram_8x512_hi
|
CSET component_name=ram_8x512_hi
|
CSET depth=512
|
CSET depth=512
|
CSET disable_warning_messages=true
|
CSET disable_warning_messages=true
|
CSET enable_pin=true
|
CSET enable_pin=true
|
CSET enable_pin_polarity=Active_Low
|
CSET enable_pin_polarity=Active_Low
|
CSET global_init_value=0
|
CSET global_init_value=0
|
CSET handshaking_pins=false
|
CSET handshaking_pins=false
|
CSET has_limit_data_pitch=false
|
CSET has_limit_data_pitch=false
|
CSET init_pin=false
|
CSET init_pin=false
|
CSET init_value=0
|
CSET init_value=0
|
CSET initialization_pin_polarity=Active_High
|
CSET initialization_pin_polarity=Active_High
|
CSET limit_data_pitch=18
|
CSET limit_data_pitch=18
|
CSET load_init_file=false
|
CSET load_init_file=false
|
CSET port_configuration=Read_And_Write
|
CSET port_configuration=Read_And_Write
|
CSET primitive_selection=Optimize_For_Area
|
CSET primitive_selection=Optimize_For_Area
|
CSET register_inputs=false
|
CSET register_inputs=false
|
CSET select_primitive=16kx1
|
CSET select_primitive=16kx1
|
CSET width=8
|
CSET width=8
|
CSET write_enable_polarity=Active_Low
|
CSET write_enable_polarity=Active_Low
|
CSET write_mode=Read_After_Write
|
CSET write_mode=Read_After_Write
|
# END Parameters
|
# END Parameters
|
GENERATE
|
GENERATE
|
# CRC: 14e27e11
|
# CRC: 14e27e11
|
|
|
|
|