The following files were generated for 'ram_8x512_hi' in directory
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The following files were generated for 'ram_8x512_hi' in directory
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/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/:
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/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/:
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ram_8x512_hi.asy:
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ram_8x512_hi.asy:
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Graphical symbol information file. Used by the ISE tools and some
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Graphical symbol information file. Used by the ISE tools and some
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third party tools to create a symbol representing the core.
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third party tools to create a symbol representing the core.
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ram_8x512_hi.ngc:
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ram_8x512_hi.ngc:
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Binary Xilinx implementation netlist file containing the information
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Binary Xilinx implementation netlist file containing the information
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required to implement the module in a Xilinx (R) FPGA.
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required to implement the module in a Xilinx (R) FPGA.
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ram_8x512_hi.sym:
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ram_8x512_hi.sym:
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Please see the core data sheet.
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Please see the core data sheet.
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ram_8x512_hi.v:
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ram_8x512_hi.v:
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Verilog wrapper file provided to support functional simulation.
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Verilog wrapper file provided to support functional simulation.
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This file contains simulation model customization data that is
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This file contains simulation model customization data that is
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passed to a parameterized simulation model for the core.
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passed to a parameterized simulation model for the core.
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ram_8x512_hi.veo:
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ram_8x512_hi.veo:
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VEO template file containing code that can be used as a model for
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VEO template file containing code that can be used as a model for
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instantiating a CORE Generator module in a Verilog design.
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instantiating a CORE Generator module in a Verilog design.
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ram_8x512_hi.xco:
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ram_8x512_hi.xco:
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CORE Generator input file containing the parameters used to
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CORE Generator input file containing the parameters used to
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regenerate a core.
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regenerate a core.
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ram_8x512_hi_flist.txt:
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ram_8x512_hi_flist.txt:
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Text file listing all of the output files produced when a customized
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Text file listing all of the output files produced when a customized
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core was generated in the CORE Generator.
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core was generated in the CORE Generator.
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ram_8x512_hi_readme.txt:
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ram_8x512_hi_readme.txt:
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Text file indicating the files generated and how they are used.
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Text file indicating the files generated and how they are used.
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ram_8x512_hi_xmdf.tcl:
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ram_8x512_hi_xmdf.tcl:
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ISE Project Navigator interface file. ISE uses this file to determine
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ISE Project Navigator interface file. ISE uses this file to determine
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how the files output by CORE Generator for the core can be integrated
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how the files output by CORE Generator for the core can be integrated
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into your ISE project.
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into your ISE project.
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Please see the Xilinx CORE Generator online help for further details on
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Please see the Xilinx CORE Generator online help for further details on
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generated files and how to use them.
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generated files and how to use them.
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