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#
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#
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# Xilinx Core Generator version K.31
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# Xilinx Core Generator version K.31
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# Date: Wed May 27 15:21:33 2009
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# Date: Wed May 27 15:21:33 2009
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#
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#
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##############################################################
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##############################################################
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#
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#
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# This file contains the customisation parameters for a
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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# unexpected and unsupported behavior.
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#
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#
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##############################################################
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##############################################################
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#
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#
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# BEGIN Project Options
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# BEGIN Project Options
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SET addpads = False
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SET addpads = False
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SET asysymbol = True
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET createndf = False
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SET designentry = Verilog
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SET designentry = Verilog
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SET device = xc3s200
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SET device = xc3s200
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SET devicefamily = spartan3
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SET devicefamily = spartan3
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SET flowvendor = Foundation_iSE
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SET flowvendor = Foundation_iSE
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SET formalverification = False
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SET formalverification = False
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SET foundationsym = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET implementationfiletype = Ngc
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SET package = ft256
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SET package = ft256
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SET removerpms = False
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET simulationfiles = Behavioral
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SET speedgrade = -4
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SET speedgrade = -4
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SET verilogsim = True
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SET verilogsim = True
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SET vhdlsim = False
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SET vhdlsim = False
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# END Project Options
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# END Project Options
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# BEGIN Select
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# BEGIN Select
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SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
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SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
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# END Select
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# END Select
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# BEGIN Parameters
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# BEGIN Parameters
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CSET active_clock_edge=Rising_Edge_Triggered
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CSET active_clock_edge=Rising_Edge_Triggered
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CSET additional_output_pipe_stages=0
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CSET additional_output_pipe_stages=0
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CSET component_name=rom_8x2k_lo
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CSET component_name=rom_8x2k_lo
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CSET depth=2048
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CSET depth=2048
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CSET disable_warning_messages=true
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CSET disable_warning_messages=true
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CSET enable_pin=true
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CSET enable_pin=true
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CSET enable_pin_polarity=Active_Low
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CSET enable_pin_polarity=Active_Low
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CSET global_init_value=0
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CSET global_init_value=0
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CSET handshaking_pins=false
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CSET handshaking_pins=false
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CSET has_limit_data_pitch=false
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CSET has_limit_data_pitch=false
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CSET init_pin=false
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CSET init_pin=false
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CSET init_value=0
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CSET init_value=0
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CSET initialization_pin_polarity=Active_High
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CSET initialization_pin_polarity=Active_High
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CSET limit_data_pitch=18
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CSET limit_data_pitch=18
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CSET load_init_file=false
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CSET load_init_file=false
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CSET port_configuration=Read_And_Write
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CSET port_configuration=Read_And_Write
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CSET primitive_selection=Optimize_For_Area
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CSET primitive_selection=Optimize_For_Area
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CSET register_inputs=false
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CSET register_inputs=false
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CSET select_primitive=16kx1
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CSET select_primitive=16kx1
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CSET width=8
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CSET width=8
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CSET write_enable_polarity=Active_Low
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CSET write_enable_polarity=Active_Low
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CSET write_mode=Read_After_Write
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CSET write_mode=Read_After_Write
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# END Parameters
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# END Parameters
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GENERATE
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GENERATE
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# CRC: 648b0470
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# CRC: 648b0470
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