The following files were generated for 'rom_8x2k_lo' in directory
|
The following files were generated for 'rom_8x2k_lo' in directory
|
/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/:
|
/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/:
|
|
|
rom_8x2k_lo.asy:
|
rom_8x2k_lo.asy:
|
Graphical symbol information file. Used by the ISE tools and some
|
Graphical symbol information file. Used by the ISE tools and some
|
third party tools to create a symbol representing the core.
|
third party tools to create a symbol representing the core.
|
|
|
rom_8x2k_lo.ngc:
|
rom_8x2k_lo.ngc:
|
Binary Xilinx implementation netlist file containing the information
|
Binary Xilinx implementation netlist file containing the information
|
required to implement the module in a Xilinx (R) FPGA.
|
required to implement the module in a Xilinx (R) FPGA.
|
|
|
rom_8x2k_lo.sym:
|
rom_8x2k_lo.sym:
|
Please see the core data sheet.
|
Please see the core data sheet.
|
|
|
rom_8x2k_lo.v:
|
rom_8x2k_lo.v:
|
Verilog wrapper file provided to support functional simulation.
|
Verilog wrapper file provided to support functional simulation.
|
This file contains simulation model customization data that is
|
This file contains simulation model customization data that is
|
passed to a parameterized simulation model for the core.
|
passed to a parameterized simulation model for the core.
|
|
|
rom_8x2k_lo.veo:
|
rom_8x2k_lo.veo:
|
VEO template file containing code that can be used as a model for
|
VEO template file containing code that can be used as a model for
|
instantiating a CORE Generator module in a Verilog design.
|
instantiating a CORE Generator module in a Verilog design.
|
|
|
rom_8x2k_lo.xco:
|
rom_8x2k_lo.xco:
|
CORE Generator input file containing the parameters used to
|
CORE Generator input file containing the parameters used to
|
regenerate a core.
|
regenerate a core.
|
|
|
rom_8x2k_lo_flist.txt:
|
rom_8x2k_lo_flist.txt:
|
Text file listing all of the output files produced when a customized
|
Text file listing all of the output files produced when a customized
|
core was generated in the CORE Generator.
|
core was generated in the CORE Generator.
|
|
|
rom_8x2k_lo_readme.txt:
|
rom_8x2k_lo_readme.txt:
|
Text file indicating the files generated and how they are used.
|
Text file indicating the files generated and how they are used.
|
|
|
rom_8x2k_lo_xmdf.tcl:
|
rom_8x2k_lo_xmdf.tcl:
|
ISE Project Navigator interface file. ISE uses this file to determine
|
ISE Project Navigator interface file. ISE uses this file to determine
|
how the files output by CORE Generator for the core can be integrated
|
how the files output by CORE Generator for the core can be integrated
|
into your ISE project.
|
into your ISE project.
|
|
|
|
|
Please see the Xilinx CORE Generator online help for further details on
|
Please see the Xilinx CORE Generator online help for further details on
|
generated files and how to use them.
|
generated files and how to use them.
|
|
|
|
|
