//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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// Copyright (C) 2009 , Olivier Girard
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// modification, are permitted provided that the following conditions
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// are met:
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// are met:
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// * Redistributions of source code must retain the above copyright
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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// without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: omsp_uart.v
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// *File Name: omsp_uart.v
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//
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//
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// *Module Description:
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// *Module Description:
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// Simple full duplex UART (8N1 protocol).
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// Simple full duplex UART (8N1 protocol).
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 111 $
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// $Rev: 111 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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module omsp_uart (
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module omsp_uart (
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// OUTPUTs
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// OUTPUTs
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irq_uart_rx, // UART receive interrupt
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irq_uart_rx, // UART receive interrupt
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irq_uart_tx, // UART transmit interrupt
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irq_uart_tx, // UART transmit interrupt
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per_dout, // Peripheral data output
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per_dout, // Peripheral data output
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uart_txd, // UART Data Transmit (TXD)
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uart_txd, // UART Data Transmit (TXD)
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// INPUTs
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// INPUTs
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mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc_rst, // Main system reset
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puc_rst, // Main system reset
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smclk_en, // SMCLK enable (from CPU)
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smclk_en, // SMCLK enable (from CPU)
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uart_rxd // UART Data Receive (RXD)
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uart_rxd // UART Data Receive (RXD)
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output irq_uart_rx; // UART receive interrupt
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output irq_uart_rx; // UART receive interrupt
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output irq_uart_tx; // UART transmit interrupt
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output irq_uart_tx; // UART transmit interrupt
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output [15:0] per_dout; // Peripheral data output
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output [15:0] per_dout; // Peripheral data output
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output uart_txd; // UART Data Transmit (TXD)
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output uart_txd; // UART Data Transmit (TXD)
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// INPUTs
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// INPUTs
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//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [13:0] per_addr; // Peripheral address
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input smclk_en; // SMCLK enable (from CPU)
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input smclk_en; // SMCLK enable (from CPU)
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input uart_rxd; // UART Data Receive (RXD)
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input uart_rxd; // UART Data Receive (RXD)
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER DECLARATION
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// 1) PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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// Register base address (must be aligned to decoder bit width)
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// Register base address (must be aligned to decoder bit width)
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parameter [14:0] BASE_ADDR = 15'h0080;
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parameter [14:0] BASE_ADDR = 15'h0080;
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// Decoder bit width (defines how many bits are considered for address decoding)
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DEC_WD = 3;
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parameter DEC_WD = 3;
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// Register addresses offset
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// Register addresses offset
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parameter [DEC_WD-1:0] CTRL = 'h0,
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parameter [DEC_WD-1:0] CTRL = 'h0,
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STATUS = 'h1,
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STATUS = 'h1,
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BAUD_LO = 'h2,
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BAUD_LO = 'h2,
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BAUD_HI = 'h3,
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BAUD_HI = 'h3,
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DATA_TX = 'h4,
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DATA_TX = 'h4,
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DATA_RX = 'h5;
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DATA_RX = 'h5;
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// Register one-hot decoder utilities
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter DEC_SZ = (1 << DEC_WD);
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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// Register one-hot decoder
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parameter [DEC_SZ-1:0] CTRL_D = (BASE_REG << CTRL),
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parameter [DEC_SZ-1:0] CTRL_D = (BASE_REG << CTRL),
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STATUS_D = (BASE_REG << STATUS),
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STATUS_D = (BASE_REG << STATUS),
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BAUD_LO_D = (BASE_REG << BAUD_LO),
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BAUD_LO_D = (BASE_REG << BAUD_LO),
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BAUD_HI_D = (BASE_REG << BAUD_HI),
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BAUD_HI_D = (BASE_REG << BAUD_HI),
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DATA_TX_D = (BASE_REG << DATA_TX),
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DATA_TX_D = (BASE_REG << DATA_TX),
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DATA_RX_D = (BASE_REG << DATA_RX);
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DATA_RX_D = (BASE_REG << DATA_RX);
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// Local register selection
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// Local register selection
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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// Register local address
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wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
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wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
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// Register address decode
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// Register address decode
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wire [DEC_SZ-1:0] reg_dec = (CTRL_D & {DEC_SZ{(reg_addr==(CTRL >>1))}}) |
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wire [DEC_SZ-1:0] reg_dec = (CTRL_D & {DEC_SZ{(reg_addr==(CTRL >>1))}}) |
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(STATUS_D & {DEC_SZ{(reg_addr==(STATUS >>1))}}) |
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(STATUS_D & {DEC_SZ{(reg_addr==(STATUS >>1))}}) |
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(BAUD_LO_D & {DEC_SZ{(reg_addr==(BAUD_LO >>1))}}) |
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(BAUD_LO_D & {DEC_SZ{(reg_addr==(BAUD_LO >>1))}}) |
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(BAUD_HI_D & {DEC_SZ{(reg_addr==(BAUD_HI >>1))}}) |
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(BAUD_HI_D & {DEC_SZ{(reg_addr==(BAUD_HI >>1))}}) |
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(DATA_TX_D & {DEC_SZ{(reg_addr==(DATA_TX >>1))}}) |
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(DATA_TX_D & {DEC_SZ{(reg_addr==(DATA_TX >>1))}}) |
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(DATA_RX_D & {DEC_SZ{(reg_addr==(DATA_RX >>1))}});
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(DATA_RX_D & {DEC_SZ{(reg_addr==(DATA_RX >>1))}});
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// Read/Write probes
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// Read/Write probes
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wire reg_lo_write = per_we[0] & reg_sel;
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wire reg_lo_write = per_we[0] & reg_sel;
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wire reg_hi_write = per_we[1] & reg_sel;
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wire reg_hi_write = per_we[1] & reg_sel;
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wire reg_read = ~|per_we & reg_sel;
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wire reg_read = ~|per_we & reg_sel;
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// Read/Write vectors
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// Read/Write vectors
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wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
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wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
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wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
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wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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//============================================================================
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//============================================================================
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// 3) REGISTERS
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// 3) REGISTERS
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//============================================================================
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//============================================================================
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// CTRL Register
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// CTRL Register
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//-----------------
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//-----------------
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reg [7:0] ctrl;
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reg [7:0] ctrl;
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wire ctrl_wr = CTRL[0] ? reg_hi_wr[CTRL] : reg_lo_wr[CTRL];
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wire ctrl_wr = CTRL[0] ? reg_hi_wr[CTRL] : reg_lo_wr[CTRL];
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wire [7:0] ctrl_nxt = CTRL[0] ? per_din[15:8] : per_din[7:0];
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wire [7:0] ctrl_nxt = CTRL[0] ? per_din[15:8] : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) ctrl <= 8'h00;
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if (puc_rst) ctrl <= 8'h00;
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else if (ctrl_wr) ctrl <= ctrl_nxt & 8'h73;
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else if (ctrl_wr) ctrl <= ctrl_nxt & 8'h73;
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wire ctrl_ien_tx_empty = ctrl[7];
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wire ctrl_ien_tx_empty = ctrl[7];
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wire ctrl_ien_tx = ctrl[6];
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wire ctrl_ien_tx = ctrl[6];
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wire ctrl_ien_rx_ovflw = ctrl[5];
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wire ctrl_ien_rx_ovflw = ctrl[5];
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wire ctrl_ien_rx = ctrl[4];
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wire ctrl_ien_rx = ctrl[4];
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wire ctrl_smclk_sel = ctrl[1];
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wire ctrl_smclk_sel = ctrl[1];
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wire ctrl_en = ctrl[0];
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wire ctrl_en = ctrl[0];
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// STATUS Register
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// STATUS Register
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//-----------------
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//-----------------
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wire [7:0] status;
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wire [7:0] status;
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reg status_tx_empty_pnd;
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reg status_tx_empty_pnd;
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reg status_tx_pnd;
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reg status_tx_pnd;
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reg status_rx_ovflw_pnd;
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reg status_rx_ovflw_pnd;
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reg status_rx_pnd;
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reg status_rx_pnd;
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wire status_tx_full;
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wire status_tx_full;
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wire status_tx_busy;
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wire status_tx_busy;
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wire status_rx_busy;
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wire status_rx_busy;
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wire status_wr = STATUS[0] ? reg_hi_wr[STATUS] : reg_lo_wr[STATUS];
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wire status_wr = STATUS[0] ? reg_hi_wr[STATUS] : reg_lo_wr[STATUS];
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wire [7:0] status_nxt = STATUS[0] ? per_din[15:8] : per_din[7:0];
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wire [7:0] status_nxt = STATUS[0] ? per_din[15:8] : per_din[7:0];
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wire status_tx_empty_pnd_clr = status_wr & status_nxt[7];
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wire status_tx_empty_pnd_clr = status_wr & status_nxt[7];
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wire status_tx_pnd_clr = status_wr & status_nxt[6];
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wire status_tx_pnd_clr = status_wr & status_nxt[6];
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wire status_rx_ovflw_pnd_clr = status_wr & status_nxt[5];
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wire status_rx_ovflw_pnd_clr = status_wr & status_nxt[5];
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wire status_rx_pnd_clr = status_wr & status_nxt[4];
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wire status_rx_pnd_clr = status_wr & status_nxt[4];
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wire status_tx_empty_pnd_set;
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wire status_tx_empty_pnd_set;
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wire status_tx_pnd_set;
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wire status_tx_pnd_set;
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wire status_rx_ovflw_pnd_set;
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wire status_rx_ovflw_pnd_set;
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wire status_rx_pnd_set;
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wire status_rx_pnd_set;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) status_tx_empty_pnd <= 1'b0;
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if (puc_rst) status_tx_empty_pnd <= 1'b0;
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else if (status_tx_empty_pnd_set) status_tx_empty_pnd <= 1'b1;
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else if (status_tx_empty_pnd_set) status_tx_empty_pnd <= 1'b1;
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else if (status_tx_empty_pnd_clr) status_tx_empty_pnd <= 1'b0;
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else if (status_tx_empty_pnd_clr) status_tx_empty_pnd <= 1'b0;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) status_tx_pnd <= 1'b0;
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if (puc_rst) status_tx_pnd <= 1'b0;
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else if (status_tx_pnd_set) status_tx_pnd <= 1'b1;
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else if (status_tx_pnd_set) status_tx_pnd <= 1'b1;
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else if (status_tx_pnd_clr) status_tx_pnd <= 1'b0;
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else if (status_tx_pnd_clr) status_tx_pnd <= 1'b0;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) status_rx_ovflw_pnd <= 1'b0;
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if (puc_rst) status_rx_ovflw_pnd <= 1'b0;
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else if (status_rx_ovflw_pnd_set) status_rx_ovflw_pnd <= 1'b1;
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else if (status_rx_ovflw_pnd_set) status_rx_ovflw_pnd <= 1'b1;
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else if (status_rx_ovflw_pnd_clr) status_rx_ovflw_pnd <= 1'b0;
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else if (status_rx_ovflw_pnd_clr) status_rx_ovflw_pnd <= 1'b0;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) status_rx_pnd <= 1'b0;
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if (puc_rst) status_rx_pnd <= 1'b0;
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else if (status_rx_pnd_set) status_rx_pnd <= 1'b1;
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else if (status_rx_pnd_set) status_rx_pnd <= 1'b1;
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else if (status_rx_pnd_clr) status_rx_pnd <= 1'b0;
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else if (status_rx_pnd_clr) status_rx_pnd <= 1'b0;
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assign status = {status_tx_empty_pnd, status_tx_pnd, status_rx_ovflw_pnd, status_rx_pnd,
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assign status = {status_tx_empty_pnd, status_tx_pnd, status_rx_ovflw_pnd, status_rx_pnd,
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status_tx_full, status_tx_busy, 1'b0, status_rx_busy};
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status_tx_full, status_tx_busy, 1'b0, status_rx_busy};
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// BAUD_LO Register
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// BAUD_LO Register
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//-----------------
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//-----------------
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reg [7:0] baud_lo;
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reg [7:0] baud_lo;
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wire baud_lo_wr = BAUD_LO[0] ? reg_hi_wr[BAUD_LO] : reg_lo_wr[BAUD_LO];
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wire baud_lo_wr = BAUD_LO[0] ? reg_hi_wr[BAUD_LO] : reg_lo_wr[BAUD_LO];
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wire [7:0] baud_lo_nxt = BAUD_LO[0] ? per_din[15:8] : per_din[7:0];
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wire [7:0] baud_lo_nxt = BAUD_LO[0] ? per_din[15:8] : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) baud_lo <= 8'h00;
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if (puc_rst) baud_lo <= 8'h00;
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else if (baud_lo_wr) baud_lo <= baud_lo_nxt;
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else if (baud_lo_wr) baud_lo <= baud_lo_nxt;
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// BAUD_HI Register
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// BAUD_HI Register
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//-----------------
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//-----------------
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reg [7:0] baud_hi;
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reg [7:0] baud_hi;
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wire baud_hi_wr = BAUD_HI[0] ? reg_hi_wr[BAUD_HI] : reg_lo_wr[BAUD_HI];
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wire baud_hi_wr = BAUD_HI[0] ? reg_hi_wr[BAUD_HI] : reg_lo_wr[BAUD_HI];
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wire [7:0] baud_hi_nxt = BAUD_HI[0] ? per_din[15:8] : per_din[7:0];
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wire [7:0] baud_hi_nxt = BAUD_HI[0] ? per_din[15:8] : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) baud_hi <= 8'h00;
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if (puc_rst) baud_hi <= 8'h00;
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else if (baud_lo_wr) baud_hi <= baud_hi_nxt;
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else if (baud_hi_wr) baud_hi <= baud_hi_nxt;
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wire [15:0] baudrate = {baud_hi, baud_lo};
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wire [15:0] baudrate = {baud_hi, baud_lo};
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// DATA_TX Register
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// DATA_TX Register
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//-----------------
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//-----------------
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reg [7:0] data_tx;
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reg [7:0] data_tx;
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wire data_tx_wr = DATA_TX[0] ? reg_hi_wr[DATA_TX] : reg_lo_wr[DATA_TX];
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wire data_tx_wr = DATA_TX[0] ? reg_hi_wr[DATA_TX] : reg_lo_wr[DATA_TX];
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wire [7:0] data_tx_nxt = DATA_TX[0] ? per_din[15:8] : per_din[7:0];
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wire [7:0] data_tx_nxt = DATA_TX[0] ? per_din[15:8] : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) data_tx <= 8'h00;
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if (puc_rst) data_tx <= 8'h00;
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else if (data_tx_wr) data_tx <= data_tx_nxt;
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else if (data_tx_wr) data_tx <= data_tx_nxt;
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// DATA_RX Register
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// DATA_RX Register
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//-----------------
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//-----------------
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reg [7:0] data_rx;
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reg [7:0] data_rx;
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reg [7:0] rxfer_buf;
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reg [7:0] rxfer_buf;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) data_rx <= 8'h00;
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if (puc_rst) data_rx <= 8'h00;
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else if (status_rx_pnd_set) data_rx <= rxfer_buf;
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else if (status_rx_pnd_set) data_rx <= rxfer_buf;
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//============================================================================
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//============================================================================
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// 4) DATA OUTPUT GENERATION
|
// 4) DATA OUTPUT GENERATION
|
//============================================================================
|
//============================================================================
|
|
|
// Data output mux
|
// Data output mux
|
wire [15:0] ctrl_rd = {8'h00, (ctrl & {8{reg_rd[CTRL]}})} << (8 & {4{CTRL[0]}});
|
wire [15:0] ctrl_rd = {8'h00, (ctrl & {8{reg_rd[CTRL]}})} << (8 & {4{CTRL[0]}});
|
wire [15:0] status_rd = {8'h00, (status & {8{reg_rd[STATUS]}})} << (8 & {4{STATUS[0]}});
|
wire [15:0] status_rd = {8'h00, (status & {8{reg_rd[STATUS]}})} << (8 & {4{STATUS[0]}});
|
wire [15:0] baud_lo_rd = {8'h00, (baud_lo & {8{reg_rd[BAUD_LO]}})} << (8 & {4{BAUD_LO[0]}});
|
wire [15:0] baud_lo_rd = {8'h00, (baud_lo & {8{reg_rd[BAUD_LO]}})} << (8 & {4{BAUD_LO[0]}});
|
wire [15:0] baud_hi_rd = {8'h00, (baud_hi & {8{reg_rd[BAUD_HI]}})} << (8 & {4{BAUD_HI[0]}});
|
wire [15:0] baud_hi_rd = {8'h00, (baud_hi & {8{reg_rd[BAUD_HI]}})} << (8 & {4{BAUD_HI[0]}});
|
wire [15:0] data_tx_rd = {8'h00, (data_tx & {8{reg_rd[DATA_TX]}})} << (8 & {4{DATA_TX[0]}});
|
wire [15:0] data_tx_rd = {8'h00, (data_tx & {8{reg_rd[DATA_TX]}})} << (8 & {4{DATA_TX[0]}});
|
wire [15:0] data_rx_rd = {8'h00, (data_rx & {8{reg_rd[DATA_RX]}})} << (8 & {4{DATA_RX[0]}});
|
wire [15:0] data_rx_rd = {8'h00, (data_rx & {8{reg_rd[DATA_RX]}})} << (8 & {4{DATA_RX[0]}});
|
|
|
wire [15:0] per_dout = ctrl_rd |
|
wire [15:0] per_dout = ctrl_rd |
|
status_rd |
|
status_rd |
|
baud_lo_rd |
|
baud_lo_rd |
|
baud_hi_rd |
|
baud_hi_rd |
|
data_tx_rd |
|
data_tx_rd |
|
data_rx_rd;
|
data_rx_rd;
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|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 5) UART CLOCK SELECTION
|
// 5) UART CLOCK SELECTION
|
//=============================================================================
|
//=============================================================================
|
|
|
wire uclk_en = ctrl_smclk_sel ? smclk_en : 1'b1;
|
wire uclk_en = ctrl_smclk_sel ? smclk_en : 1'b1;
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|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 5) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
|
// 5) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
|
//=============================================================================
|
//=============================================================================
|
|
|
// Synchronize RXD input
|
// Synchronize RXD input
|
//--------------------------------
|
//--------------------------------
|
wire uart_rxd_sync_n;
|
wire uart_rxd_sync_n;
|
|
|
omsp_sync_cell sync_cell_uart_rxd (
|
omsp_sync_cell sync_cell_uart_rxd (
|
.data_out (uart_rxd_sync_n),
|
.data_out (uart_rxd_sync_n),
|
.clk (mclk),
|
.data_meta (),
|
.data_in (~uart_rxd),
|
.data_in (~uart_rxd),
|
|
.clk (mclk),
|
.rst (puc_rst)
|
.rst (puc_rst)
|
);
|
);
|
wire uart_rxd_sync = ~uart_rxd_sync_n;
|
wire uart_rxd_sync = ~uart_rxd_sync_n;
|
|
|
// RXD input buffer
|
// RXD input buffer
|
//--------------------------------
|
//--------------------------------
|
reg [1:0] rxd_buf;
|
reg [1:0] rxd_buf;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) rxd_buf <= 2'h3;
|
if (puc_rst) rxd_buf <= 2'h3;
|
else rxd_buf <= {rxd_buf[0], uart_rxd_sync};
|
else rxd_buf <= {rxd_buf[0], uart_rxd_sync};
|
|
|
// Majority decision
|
// Majority decision
|
//------------------------
|
//------------------------
|
reg rxd_maj;
|
reg rxd_maj;
|
|
|
wire [1:0] rxd_maj_cnt = {1'b0, uart_rxd_sync} +
|
wire [1:0] rxd_maj_cnt = {1'b0, uart_rxd_sync} +
|
{1'b0, rxd_buf[0]} +
|
{1'b0, rxd_buf[0]} +
|
{1'b0, rxd_buf[1]};
|
{1'b0, rxd_buf[1]};
|
wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
|
wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) rxd_maj <= 1'b1;
|
if (puc_rst) rxd_maj <= 1'b1;
|
else rxd_maj <= rxd_maj_nxt;
|
else rxd_maj <= rxd_maj_nxt;
|
|
|
wire rxd_s = rxd_maj;
|
wire rxd_s = rxd_maj;
|
wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
|
wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 6) UART RECEIVE
|
// 6) UART RECEIVE
|
//=============================================================================
|
//=============================================================================
|
|
|
// RX Transfer counter
|
// RX Transfer counter
|
//------------------------
|
//------------------------
|
reg [3:0] rxfer_bit;
|
reg [3:0] rxfer_bit;
|
reg [15:0] rxfer_cnt;
|
reg [15:0] rxfer_cnt;
|
|
|
wire rxfer_start = (rxfer_bit==4'h0) & rxd_fe;
|
wire rxfer_start = (rxfer_bit==4'h0) & rxd_fe;
|
wire rxfer_bit_inc = (rxfer_bit!=4'h0) & (rxfer_cnt=={16{1'b0}});
|
wire rxfer_bit_inc = (rxfer_bit!=4'h0) & (rxfer_cnt=={16{1'b0}});
|
wire rxfer_done = (rxfer_bit==4'ha);
|
wire rxfer_done = (rxfer_bit==4'ha);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) rxfer_bit <= 4'h0;
|
if (puc_rst) rxfer_bit <= 4'h0;
|
else if (~ctrl_en) rxfer_bit <= 4'h0;
|
else if (~ctrl_en) rxfer_bit <= 4'h0;
|
else if (rxfer_start) rxfer_bit <= 4'h1;
|
else if (rxfer_start) rxfer_bit <= 4'h1;
|
else if (uclk_en)
|
else if (uclk_en)
|
begin
|
begin
|
if (rxfer_done) rxfer_bit <= 4'h0;
|
if (rxfer_done) rxfer_bit <= 4'h0;
|
else if (rxfer_bit_inc) rxfer_bit <= rxfer_bit+4'h1;
|
else if (rxfer_bit_inc) rxfer_bit <= rxfer_bit+4'h1;
|
end
|
end
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) rxfer_cnt <= {16{1'b0}};
|
if (puc_rst) rxfer_cnt <= {16{1'b0}};
|
else if (~ctrl_en) rxfer_cnt <= {16{1'b0}};
|
else if (~ctrl_en) rxfer_cnt <= {16{1'b0}};
|
else if (rxfer_start) rxfer_cnt <= {1'b0, baudrate[15:1]};
|
else if (rxfer_start) rxfer_cnt <= {1'b0, baudrate[15:1]};
|
else if (uclk_en)
|
else if (uclk_en)
|
begin
|
begin
|
if (rxfer_bit_inc) rxfer_cnt <= baudrate;
|
if (rxfer_bit_inc) rxfer_cnt <= baudrate;
|
else if (|rxfer_cnt) rxfer_cnt <= rxfer_cnt+{16{1'b1}};
|
else if (|rxfer_cnt) rxfer_cnt <= rxfer_cnt+{16{1'b1}};
|
end
|
end
|
|
|
|
|
// Receive buffer
|
// Receive buffer
|
//-------------------------
|
//-------------------------
|
wire [7:0] rxfer_buf_nxt = {rxd_s, rxfer_buf[7:1]};
|
wire [7:0] rxfer_buf_nxt = {rxd_s, rxfer_buf[7:1]};
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) rxfer_buf <= 8'h00;
|
if (puc_rst) rxfer_buf <= 8'h00;
|
else if (~ctrl_en) rxfer_buf <= 8'h00;
|
else if (~ctrl_en) rxfer_buf <= 8'h00;
|
else if (uclk_en)
|
else if (uclk_en)
|
begin
|
begin
|
if (rxfer_bit_inc) rxfer_buf <= rxfer_buf_nxt;
|
if (rxfer_bit_inc) rxfer_buf <= rxfer_buf_nxt;
|
end
|
end
|
|
|
|
|
// Status flags
|
// Status flags
|
//-------------------------
|
//-------------------------
|
|
|
// Edge detection required for the case when
|
// Edge detection required for the case when
|
// the transmit base clock is SMCLK
|
// the transmit base clock is SMCLK
|
reg rxfer_done_dly;
|
reg rxfer_done_dly;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) rxfer_done_dly <= 1'b0;
|
if (puc_rst) rxfer_done_dly <= 1'b0;
|
else rxfer_done_dly <= rxfer_done;
|
else rxfer_done_dly <= rxfer_done;
|
|
|
|
|
assign status_rx_pnd_set = rxfer_done & ~rxfer_done_dly;
|
assign status_rx_pnd_set = rxfer_done & ~rxfer_done_dly;
|
assign status_rx_ovflw_pnd_set = status_rx_pnd_set & status_rx_pnd;
|
assign status_rx_ovflw_pnd_set = status_rx_pnd_set & status_rx_pnd;
|
assign status_rx_busy = (rxfer_bit!=4'h0);
|
assign status_rx_busy = (rxfer_bit!=4'h0);
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 5) UART TRANSMIT
|
// 5) UART TRANSMIT
|
//============================================================================
|
//============================================================================
|
|
|
// TX Transfer start detection
|
// TX Transfer start detection
|
//-----------------------------
|
//-----------------------------
|
reg txfer_triggered;
|
reg txfer_triggered;
|
wire txfer_start;
|
wire txfer_start;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) txfer_triggered <= 1'b0;
|
if (puc_rst) txfer_triggered <= 1'b0;
|
else if (data_tx_wr) txfer_triggered <= 1'b1;
|
else if (data_tx_wr) txfer_triggered <= 1'b1;
|
else if (txfer_start) txfer_triggered <= 1'b0;
|
else if (txfer_start) txfer_triggered <= 1'b0;
|
|
|
|
|
// TX Transfer counter
|
// TX Transfer counter
|
//------------------------
|
//------------------------
|
reg [3:0] txfer_bit;
|
reg [3:0] txfer_bit;
|
reg [15:0] txfer_cnt;
|
reg [15:0] txfer_cnt;
|
|
|
assign txfer_start = (txfer_bit==4'h0) & txfer_triggered;
|
assign txfer_start = (txfer_bit==4'h0) & txfer_triggered;
|
wire txfer_bit_inc = (txfer_bit!=4'h0) & (txfer_cnt=={16{1'b0}});
|
wire txfer_bit_inc = (txfer_bit!=4'h0) & (txfer_cnt=={16{1'b0}});
|
wire txfer_done = (txfer_bit==4'hb);
|
wire txfer_done = (txfer_bit==4'hb);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) txfer_bit <= 4'h0;
|
if (puc_rst) txfer_bit <= 4'h0;
|
else if (~ctrl_en) txfer_bit <= 4'h0;
|
else if (~ctrl_en) txfer_bit <= 4'h0;
|
else if (txfer_start) txfer_bit <= 4'h1;
|
else if (txfer_start) txfer_bit <= 4'h1;
|
else if (uclk_en)
|
else if (uclk_en)
|
begin
|
begin
|
if (txfer_done) txfer_bit <= 4'h0;
|
if (txfer_done) txfer_bit <= 4'h0;
|
else if (txfer_bit_inc) txfer_bit <= txfer_bit+4'h1;
|
else if (txfer_bit_inc) txfer_bit <= txfer_bit+4'h1;
|
end
|
end
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) txfer_cnt <= {16{1'b0}};
|
if (puc_rst) txfer_cnt <= {16{1'b0}};
|
else if (~ctrl_en) txfer_cnt <= {16{1'b0}};
|
else if (~ctrl_en) txfer_cnt <= {16{1'b0}};
|
else if (txfer_start) txfer_cnt <= baudrate;
|
else if (txfer_start) txfer_cnt <= baudrate;
|
else if (uclk_en)
|
else if (uclk_en)
|
begin
|
begin
|
if (txfer_bit_inc) txfer_cnt <= baudrate;
|
if (txfer_bit_inc) txfer_cnt <= baudrate;
|
else if (|txfer_cnt) txfer_cnt <= txfer_cnt+{16{1'b1}};
|
else if (|txfer_cnt) txfer_cnt <= txfer_cnt+{16{1'b1}};
|
end
|
end
|
|
|
|
|
// Transmit buffer
|
// Transmit buffer
|
//-------------------------
|
//-------------------------
|
reg [8:0] txfer_buf;
|
reg [8:0] txfer_buf;
|
|
|
wire [8:0] txfer_buf_nxt = {1'b1, txfer_buf[8:1]};
|
wire [8:0] txfer_buf_nxt = {1'b1, txfer_buf[8:1]};
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) txfer_buf <= 9'h1ff;
|
if (puc_rst) txfer_buf <= 9'h1ff;
|
else if (~ctrl_en) txfer_buf <= 9'h1ff;
|
else if (~ctrl_en) txfer_buf <= 9'h1ff;
|
else if (txfer_start) txfer_buf <= {data_tx, 1'b0};
|
else if (txfer_start) txfer_buf <= {data_tx, 1'b0};
|
else if (uclk_en)
|
else if (uclk_en)
|
begin
|
begin
|
if (txfer_bit_inc) txfer_buf <= txfer_buf_nxt;
|
if (txfer_bit_inc) txfer_buf <= txfer_buf_nxt;
|
end
|
end
|
|
|
assign uart_txd = txfer_buf[0];
|
assign uart_txd = txfer_buf[0];
|
|
|
|
|
// Status flags
|
// Status flags
|
//-------------------------
|
//-------------------------
|
|
|
// Edge detection required for the case when
|
// Edge detection required for the case when
|
// the transmit base clock is SMCLK
|
// the transmit base clock is SMCLK
|
reg txfer_done_dly;
|
reg txfer_done_dly;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) txfer_done_dly <= 1'b0;
|
if (puc_rst) txfer_done_dly <= 1'b0;
|
else txfer_done_dly <= txfer_done;
|
else txfer_done_dly <= txfer_done;
|
|
|
|
|
assign status_tx_pnd_set = txfer_done & ~txfer_done_dly;
|
assign status_tx_pnd_set = txfer_done & ~txfer_done_dly;
|
assign status_tx_empty_pnd_set = status_tx_pnd_set & ~txfer_triggered;
|
assign status_tx_empty_pnd_set = status_tx_pnd_set & ~txfer_triggered;
|
assign status_tx_busy = (txfer_bit!=4'h0) | txfer_triggered;
|
assign status_tx_busy = (txfer_bit!=4'h0) | txfer_triggered;
|
assign status_tx_full = status_tx_busy & txfer_triggered;
|
assign status_tx_full = status_tx_busy & txfer_triggered;
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 6) INTERRUPTS
|
// 6) INTERRUPTS
|
//============================================================================
|
//============================================================================
|
|
|
// Receive interrupt can be generated with the completion of a received byte
|
// Receive interrupt can be generated with the completion of a received byte
|
// or an overflow occures.
|
// or an overflow occures.
|
assign irq_uart_rx = (status_rx_pnd & ctrl_ien_rx) |
|
assign irq_uart_rx = (status_rx_pnd & ctrl_ien_rx) |
|
(status_rx_ovflw_pnd & ctrl_ien_rx_ovflw);
|
(status_rx_ovflw_pnd & ctrl_ien_rx_ovflw);
|
|
|
|
|
// Transmit interrupt can be generated with the transmition completion of
|
// Transmit interrupt can be generated with the transmition completion of
|
// a byte or when the tranmit buffer is empty (i.e. nothing left to transmit)
|
// a byte or when the tranmit buffer is empty (i.e. nothing left to transmit)
|
assign irq_uart_tx = (status_tx_pnd & ctrl_ien_tx) |
|
assign irq_uart_tx = (status_tx_pnd & ctrl_ien_tx) |
|
(status_tx_empty_pnd & ctrl_ien_tx_empty);
|
(status_tx_empty_pnd & ctrl_ien_tx_empty);
|
|
|
|
|
endmodule // uart
|
endmodule // uart
|
|
|
|
|