//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2001 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: omsp_alu.v
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// *File Name: omsp_alu.v
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//
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//
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// *Module Description:
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// *Module Description:
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// openMSP430 ALU
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// openMSP430 ALU
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 34 $
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// $Rev: 37 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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|
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module omsp_alu (
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module omsp_alu (
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// OUTPUTs
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// OUTPUTs
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alu_out, // ALU output value
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alu_out, // ALU output value
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alu_out_add, // ALU adder output value
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alu_out_add, // ALU adder output value
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alu_stat, // ALU Status {V,N,Z,C}
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alu_stat, // ALU Status {V,N,Z,C}
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alu_stat_wr, // ALU Status write {V,N,Z,C}
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alu_stat_wr, // ALU Status write {V,N,Z,C}
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|
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// INPUTs
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// INPUTs
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dbg_halt_st, // Halt/Run status from CPU
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dbg_halt_st, // Halt/Run status from CPU
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exec_cycle, // Instruction execution cycle
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exec_cycle, // Instruction execution cycle
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inst_alu, // ALU control signals
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inst_alu, // ALU control signals
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inst_bw, // Decoded Inst: byte width
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inst_bw, // Decoded Inst: byte width
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inst_jmp, // Decoded Inst: Conditional jump
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inst_jmp, // Decoded Inst: Conditional jump
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inst_so, // Single-operand arithmetic
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inst_so, // Single-operand arithmetic
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op_dst, // Destination operand
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op_dst, // Destination operand
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op_src, // Source operand
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op_src, // Source operand
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status // R2 Status {V,N,Z,C}
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status // R2 Status {V,N,Z,C}
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [15:0] alu_out; // ALU output value
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output [15:0] alu_out; // ALU output value
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output [15:0] alu_out_add; // ALU adder output value
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output [15:0] alu_out_add; // ALU adder output value
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output [3:0] alu_stat; // ALU Status {V,N,Z,C}
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output [3:0] alu_stat; // ALU Status {V,N,Z,C}
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output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
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output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
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// INPUTs
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// INPUTs
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//=========
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//=========
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input dbg_halt_st; // Halt/Run status from CPU
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input dbg_halt_st; // Halt/Run status from CPU
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input exec_cycle; // Instruction execution cycle
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input exec_cycle; // Instruction execution cycle
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input [11:0] inst_alu; // ALU control signals
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input [11:0] inst_alu; // ALU control signals
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input inst_bw; // Decoded Inst: byte width
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input inst_bw; // Decoded Inst: byte width
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input [7:0] inst_jmp; // Decoded Inst: Conditional jump
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input [7:0] inst_jmp; // Decoded Inst: Conditional jump
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input [7:0] inst_so; // Single-operand arithmetic
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input [7:0] inst_so; // Single-operand arithmetic
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input [15:0] op_dst; // Destination operand
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input [15:0] op_dst; // Destination operand
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input [15:0] op_src; // Source operand
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input [15:0] op_src; // Source operand
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input [3:0] status; // R2 Status {V,N,Z,C}
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input [3:0] status; // R2 Status {V,N,Z,C}
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//=============================================================================
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//=============================================================================
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// 1) FUNCTIONS
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// 1) FUNCTIONS
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//=============================================================================
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//=============================================================================
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function [4:0] bcd_add;
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function [4:0] bcd_add;
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input [3:0] X;
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input [3:0] X;
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input [3:0] Y;
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input [3:0] Y;
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input C;
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input C;
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reg [4:0] Z;
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reg [4:0] Z;
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begin
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begin
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Z = {1'b0,X}+{1'b0,Y}+C;
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Z = {1'b0,X}+{1'b0,Y}+C;
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if (Z<10) bcd_add = Z;
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if (Z<10) bcd_add = Z;
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else bcd_add = Z+6;
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else bcd_add = Z+6;
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end
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end
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endfunction
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endfunction
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//=============================================================================
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//=============================================================================
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// 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE
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// 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE
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//=============================================================================
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//=============================================================================
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// SINGLE-OPERAND ARITHMETIC:
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// SINGLE-OPERAND ARITHMETIC:
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Mnemonic S-Reg, Operation Status bits
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// Mnemonic S-Reg, Operation Status bits
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// D-Reg, V N Z C
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// D-Reg, V N Z C
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//
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//
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// RRC dst C->MSB->...LSB->C * * * *
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// RRC dst C->MSB->...LSB->C * * * *
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// RRA dst MSB->MSB->...LSB->C 0 * * *
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// RRA dst MSB->MSB->...LSB->C 0 * * *
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// SWPB dst Swap bytes - - - -
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// SWPB dst Swap bytes - - - -
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// SXT dst Bit7->Bit8...Bit15 0 * * *
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// SXT dst Bit7->Bit8...Bit15 0 * * *
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// PUSH src SP-2->SP, src->@SP - - - -
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// PUSH src SP-2->SP, src->@SP - - - -
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// CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - -
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// CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - -
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// RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * *
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// RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * *
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// TWO-OPERAND ARITHMETIC:
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// TWO-OPERAND ARITHMETIC:
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Mnemonic S-Reg, Operation Status bits
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// Mnemonic S-Reg, Operation Status bits
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// D-Reg, V N Z C
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// D-Reg, V N Z C
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//
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//
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// MOV src,dst src -> dst - - - -
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// MOV src,dst src -> dst - - - -
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// ADD src,dst src + dst -> dst * * * *
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// ADD src,dst src + dst -> dst * * * *
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// ADDC src,dst src + dst + C -> dst * * * *
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// ADDC src,dst src + dst + C -> dst * * * *
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// SUB src,dst dst + ~src + 1 -> dst * * * *
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// SUB src,dst dst + ~src + 1 -> dst * * * *
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// SUBC src,dst dst + ~src + C -> dst * * * *
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// SUBC src,dst dst + ~src + C -> dst * * * *
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// CMP src,dst dst + ~src + 1 * * * *
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// CMP src,dst dst + ~src + 1 * * * *
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// DADD src,dst src + dst + C -> dst (decimaly) * * * *
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// DADD src,dst src + dst + C -> dst (decimaly) * * * *
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// BIT src,dst src & dst 0 * * *
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// BIT src,dst src & dst 0 * * *
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// BIC src,dst ~src & dst -> dst - - - -
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// BIC src,dst ~src & dst -> dst - - - -
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// BIS src,dst src | dst -> dst - - - -
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// BIS src,dst src | dst -> dst - - - -
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// XOR src,dst src ^ dst -> dst * * * *
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// XOR src,dst src ^ dst -> dst * * * *
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// AND src,dst src & dst -> dst 0 * * *
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// AND src,dst src & dst -> dst 0 * * *
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// * the status bit is affected
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// * the status bit is affected
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// - the status bit is not affected
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// - the status bit is not affected
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// 0 the status bit is cleared
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// 0 the status bit is cleared
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// 1 the status bit is set
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// 1 the status bit is set
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Invert source for substract and compare instructions.
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// Invert source for substract and compare instructions.
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wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);
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wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);
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wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src;
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wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src;
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// Mask the bit 8 for the Byte instructions for correct flags generation
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// Mask the bit 8 for the Byte instructions for correct flags generation
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wire op_bit8_msk = ~exec_cycle | ~inst_bw;
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wire op_bit8_msk = ~exec_cycle | ~inst_bw;
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wire [16:0] op_src_in = {1'b0, op_src_inv[15:9], op_src_inv[8] & op_bit8_msk, op_src_inv[7:0]};
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wire [16:0] op_src_in = {1'b0, op_src_inv[15:9], op_src_inv[8] & op_bit8_msk, op_src_inv[7:0]};
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wire [16:0] op_dst_in = {1'b0, op_dst[15:9], op_dst[8] & op_bit8_msk, op_dst[7:0]};
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wire [16:0] op_dst_in = {1'b0, op_dst[15:9], op_dst[8] & op_bit8_msk, op_dst[7:0]};
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// Clear the source operand (= jump offset) for conditional jumps
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// Clear the source operand (= jump offset) for conditional jumps
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wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) |
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wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) |
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(inst_jmp[`JGE] & (status[3]^status[2])) |
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(inst_jmp[`JGE] & (status[3]^status[2])) |
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(inst_jmp[`JN] & ~status[2]) |
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(inst_jmp[`JN] & ~status[2]) |
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(inst_jmp[`JC] & ~status[0]) |
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(inst_jmp[`JC] & ~status[0]) |
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(inst_jmp[`JNC] & status[0]) |
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(inst_jmp[`JNC] & status[0]) |
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(inst_jmp[`JEQ] & ~status[1]) |
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(inst_jmp[`JEQ] & ~status[1]) |
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(inst_jmp[`JNE] & status[1]);
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(inst_jmp[`JNE] & status[1]);
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wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}};
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wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}};
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// Adder / AND / OR / XOR
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// Adder / AND / OR / XOR
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wire [16:0] alu_add = op_src_in_jmp + op_dst_in;
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wire [16:0] alu_add = op_src_in_jmp + op_dst_in;
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wire [16:0] alu_and = op_src_in & op_dst_in;
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wire [16:0] alu_and = op_src_in & op_dst_in;
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wire [16:0] alu_or = op_src_in | op_dst_in;
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wire [16:0] alu_or = op_src_in | op_dst_in;
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wire [16:0] alu_xor = op_src_in ^ op_dst_in;
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wire [16:0] alu_xor = op_src_in ^ op_dst_in;
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// Incrementer
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// Incrementer
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wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |
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wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |
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inst_alu[`ALU_INC]);
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inst_alu[`ALU_INC]);
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wire [16:0] alu_add_inc = alu_add + {16'h0000, alu_inc};
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wire [16:0] alu_add_inc = alu_add + {16'h0000, alu_inc};
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// Decimal adder (DADD)
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// Decimal adder (DADD)
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wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]);
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wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]);
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wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]);
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wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]);
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wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]);
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wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]);
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wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
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wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
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wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};
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wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};
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// Shifter for rotate instructions (RRC & RRA)
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// Shifter for rotate instructions (RRC & RRA)
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wire alu_shift_msb = inst_so[`RRC] ? status[0] :
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wire alu_shift_msb = inst_so[`RRC] ? status[0] :
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inst_bw ? op_src[7] : op_src[15];
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inst_bw ? op_src[7] : op_src[15];
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wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8];
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wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8];
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wire [16:0] alu_shift = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};
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wire [16:0] alu_shift = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};
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// Swap bytes / Extend Sign
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// Swap bytes / Extend Sign
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wire [16:0] alu_swpb = {1'b0, op_src[7:0],op_src[15:8]};
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wire [16:0] alu_swpb = {1'b0, op_src[7:0],op_src[15:8]};
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wire [16:0] alu_sxt = {1'b0, {8{op_src[7]}},op_src[7:0]};
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wire [16:0] alu_sxt = {1'b0, {8{op_src[7]}},op_src[7:0]};
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// Combine short paths toghether to simplify final ALU mux
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// Combine short paths toghether to simplify final ALU mux
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wire alu_short_thro = ~(inst_alu[`ALU_AND] |
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wire alu_short_thro = ~(inst_alu[`ALU_AND] |
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inst_alu[`ALU_OR] |
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inst_alu[`ALU_OR] |
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inst_alu[`ALU_XOR] |
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inst_alu[`ALU_XOR] |
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inst_alu[`ALU_SHIFT] |
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inst_alu[`ALU_SHIFT] |
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inst_so[`SWPB] |
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inst_so[`SWPB] |
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inst_so[`SXT]);
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inst_so[`SXT]);
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wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) |
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wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) |
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({16{inst_alu[`ALU_OR]}} & alu_or) |
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({16{inst_alu[`ALU_OR]}} & alu_or) |
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({16{inst_alu[`ALU_XOR]}} & alu_xor) |
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({16{inst_alu[`ALU_XOR]}} & alu_xor) |
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({16{inst_alu[`ALU_SHIFT]}} & alu_shift) |
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({16{inst_alu[`ALU_SHIFT]}} & alu_shift) |
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({16{inst_so[`SWPB]}} & alu_swpb) |
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({16{inst_so[`SWPB]}} & alu_swpb) |
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({16{inst_so[`SXT]}} & alu_sxt) |
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({16{inst_so[`SXT]}} & alu_sxt) |
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({16{alu_short_thro}} & op_src_in);
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({16{alu_short_thro}} & op_src_in);
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// ALU output mux
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// ALU output mux
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wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st |
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wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st |
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inst_alu[`ALU_ADD]) ? alu_add_inc :
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inst_alu[`ALU_ADD]) ? alu_add_inc :
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inst_alu[`ALU_DADD] ? alu_dadd : alu_short;
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inst_alu[`ALU_DADD] ? alu_dadd : alu_short;
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|
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assign alu_out = alu_out_nxt[15:0];
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assign alu_out = alu_out_nxt[15:0];
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assign alu_out_add = alu_add[15:0];
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assign alu_out_add = alu_add[15:0];
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|
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// STATUS FLAG GENERATION
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// STATUS FLAG GENERATION
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
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|
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wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) :
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wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) :
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(op_src_in[15] & op_dst_in[15]);
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(op_src_in[15] & op_dst_in[15]);
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|
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wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) |
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wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) |
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( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) :
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( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) :
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((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) |
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((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) |
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( op_src_in[15] & op_dst_in[15] & ~alu_out[15]));
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( op_src_in[15] & op_dst_in[15] & ~alu_out[15]));
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|
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wire N = inst_bw ? alu_out[7] : alu_out[15];
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wire N = inst_bw ? alu_out[7] : alu_out[15];
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wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
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wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
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wire C = inst_bw ? alu_out[8] : alu_out_nxt[16];
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wire C = inst_bw ? alu_out[8] : alu_out_nxt[16];
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assign alu_stat = inst_alu[`ALU_SHIFT] ? {1'b0, N,Z,op_src_in[0]} :
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assign alu_stat = inst_alu[`ALU_SHIFT] ? {1'b0, N,Z,op_src_in[0]} :
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inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z} :
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inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z} :
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inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C};
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inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C};
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assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000;
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assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000;
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endmodule // omsp_alu
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endmodule // omsp_alu
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`include "openMSP430_undefines.v"
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`include "openMSP430_undefines.v"
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