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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2001 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: omsp_multiplier.v
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// *File Name: omsp_multiplier.v
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//
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//
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// *Module Description:
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// *Module Description:
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// 16x16 Hardware multiplier.
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// 16x16 Hardware multiplier.
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $Rev: 23 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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module omsp_multiplier (
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module omsp_multiplier (
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// OUTPUTs
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// OUTPUTs
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per_dout, // Peripheral data output
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per_dout, // Peripheral data output
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|
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// INPUTs
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// INPUTs
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mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_wen, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc // Main system reset
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puc // Main system reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [15:0] per_dout; // Peripheral data output
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output [15:0] per_dout; // Peripheral data output
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|
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// INPUTs
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// INPUTs
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//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [7:0] per_addr; // Peripheral address
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input [7:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_wen; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc; // Main system reset
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input puc; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER/REGISTERS & WIRE DECLARATION
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// 1) PARAMETER/REGISTERS & WIRE DECLARATION
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//=============================================================================
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//=============================================================================
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// Register addresses
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// Register addresses
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parameter OP1_MPY = 9'h130;
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parameter OP1_MPY = 9'h130;
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parameter OP1_MPYS = 9'h132;
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parameter OP1_MPYS = 9'h132;
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parameter OP1_MAC = 9'h134;
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parameter OP1_MAC = 9'h134;
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parameter OP1_MACS = 9'h136;
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parameter OP1_MACS = 9'h136;
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parameter OP2 = 9'h138;
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parameter OP2 = 9'h138;
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parameter RESLO = 9'h13A;
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parameter RESLO = 9'h13A;
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parameter RESHI = 9'h13C;
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parameter RESHI = 9'h13C;
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parameter SUMEXT = 9'h13E;
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parameter SUMEXT = 9'h13E;
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// Register one-hot decoder
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// Register one-hot decoder
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parameter OP1_MPY_D = (512'h1 << OP1_MPY);
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parameter OP1_MPY_D = (512'h1 << OP1_MPY);
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parameter OP1_MPYS_D = (512'h1 << OP1_MPYS);
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parameter OP1_MPYS_D = (512'h1 << OP1_MPYS);
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parameter OP1_MAC_D = (512'h1 << OP1_MAC);
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parameter OP1_MAC_D = (512'h1 << OP1_MAC);
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parameter OP1_MACS_D = (512'h1 << OP1_MACS);
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parameter OP1_MACS_D = (512'h1 << OP1_MACS);
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parameter OP2_D = (512'h1 << OP2);
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parameter OP2_D = (512'h1 << OP2);
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parameter RESLO_D = (512'h1 << RESLO);
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parameter RESLO_D = (512'h1 << RESLO);
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parameter RESHI_D = (512'h1 << RESHI);
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parameter RESHI_D = (512'h1 << RESHI);
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parameter SUMEXT_D = (512'h1 << SUMEXT);
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parameter SUMEXT_D = (512'h1 << SUMEXT);
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// Wire pre-declarations
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// Wire pre-declarations
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wire result_wr;
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wire result_wr;
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wire result_clr;
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wire result_clr;
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wire early_read;
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wire early_read;
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// Register address decode
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// Register address decode
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reg [511:0] reg_dec;
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reg [511:0] reg_dec;
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always @(per_addr)
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always @(per_addr)
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case ({per_addr,1'b0})
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case ({per_addr,1'b0})
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OP1_MPY : reg_dec = OP1_MPY_D;
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OP1_MPY : reg_dec = OP1_MPY_D;
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OP1_MPYS : reg_dec = OP1_MPYS_D;
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OP1_MPYS : reg_dec = OP1_MPYS_D;
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OP1_MAC : reg_dec = OP1_MAC_D;
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OP1_MAC : reg_dec = OP1_MAC_D;
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OP1_MACS : reg_dec = OP1_MACS_D;
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OP1_MACS : reg_dec = OP1_MACS_D;
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OP2 : reg_dec = OP2_D;
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OP2 : reg_dec = OP2_D;
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RESLO : reg_dec = RESLO_D;
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RESLO : reg_dec = RESLO_D;
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RESHI : reg_dec = RESHI_D;
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RESHI : reg_dec = RESHI_D;
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SUMEXT : reg_dec = SUMEXT_D;
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SUMEXT : reg_dec = SUMEXT_D;
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default : reg_dec = {512{1'b0}};
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default : reg_dec = {512{1'b0}};
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endcase
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_write = |per_wen & per_en;
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wire reg_write = |per_we & per_en;
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wire reg_read = ~|per_wen & per_en;
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wire reg_read = ~|per_we & per_en;
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// Read/Write vectors
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// Read/Write vectors
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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//============================================================================
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//============================================================================
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// 3) REGISTERS
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// 3) REGISTERS
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//============================================================================
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//============================================================================
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// OP1 Register
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// OP1 Register
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//-----------------
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//-----------------
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reg [15:0] op1;
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reg [15:0] op1;
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wire op1_wr = reg_wr[OP1_MPY] |
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wire op1_wr = reg_wr[OP1_MPY] |
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reg_wr[OP1_MPYS] |
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reg_wr[OP1_MPYS] |
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reg_wr[OP1_MAC] |
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reg_wr[OP1_MAC] |
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reg_wr[OP1_MACS];
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reg_wr[OP1_MACS];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) op1 <= 16'h0000;
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if (puc) op1 <= 16'h0000;
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else if (op1_wr) op1 <= per_din;
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else if (op1_wr) op1 <= per_din;
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wire [15:0] op1_rd = op1;
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wire [15:0] op1_rd = op1;
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// OP2 Register
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// OP2 Register
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//-----------------
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//-----------------
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reg [15:0] op2;
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reg [15:0] op2;
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|
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wire op2_wr = reg_wr[OP2];
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wire op2_wr = reg_wr[OP2];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) op2 <= 16'h0000;
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if (puc) op2 <= 16'h0000;
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else if (op2_wr) op2 <= per_din;
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else if (op2_wr) op2 <= per_din;
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wire [15:0] op2_rd = op2;
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wire [15:0] op2_rd = op2;
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// RESLO Register
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// RESLO Register
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//-----------------
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//-----------------
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reg [15:0] reslo;
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reg [15:0] reslo;
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wire [15:0] reslo_nxt;
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wire [15:0] reslo_nxt;
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wire reslo_wr = reg_wr[RESLO];
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wire reslo_wr = reg_wr[RESLO];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) reslo <= 16'h0000;
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if (puc) reslo <= 16'h0000;
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else if (reslo_wr) reslo <= per_din;
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else if (reslo_wr) reslo <= per_din;
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else if (result_clr) reslo <= 16'h0000;
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else if (result_clr) reslo <= 16'h0000;
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else if (result_wr) reslo <= reslo_nxt;
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else if (result_wr) reslo <= reslo_nxt;
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wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
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wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
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// RESHI Register
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// RESHI Register
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//-----------------
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//-----------------
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reg [15:0] reshi;
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reg [15:0] reshi;
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wire [15:0] reshi_nxt;
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wire [15:0] reshi_nxt;
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wire reshi_wr = reg_wr[RESHI];
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wire reshi_wr = reg_wr[RESHI];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) reshi <= 16'h0000;
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if (puc) reshi <= 16'h0000;
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else if (reshi_wr) reshi <= per_din;
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else if (reshi_wr) reshi <= per_din;
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else if (result_clr) reshi <= 16'h0000;
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else if (result_clr) reshi <= 16'h0000;
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else if (result_wr) reshi <= reshi_nxt;
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else if (result_wr) reshi <= reshi_nxt;
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wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi;
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wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi;
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// SUMEXT Register
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// SUMEXT Register
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//-----------------
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//-----------------
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reg [1:0] sumext_s;
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reg [1:0] sumext_s;
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wire [1:0] sumext_s_nxt;
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wire [1:0] sumext_s_nxt;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) sumext_s <= 2'b00;
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if (puc) sumext_s <= 2'b00;
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else if (op2_wr) sumext_s <= 2'b00;
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else if (op2_wr) sumext_s <= 2'b00;
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else if (result_wr) sumext_s <= sumext_s_nxt;
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else if (result_wr) sumext_s <= sumext_s_nxt;
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wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt};
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wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt};
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wire [15:0] sumext = {{14{sumext_s[1]}}, sumext_s};
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wire [15:0] sumext = {{14{sumext_s[1]}}, sumext_s};
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wire [15:0] sumext_rd = early_read ? sumext_nxt : sumext;
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wire [15:0] sumext_rd = early_read ? sumext_nxt : sumext;
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//============================================================================
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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//============================================================================
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// Data output mux
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// Data output mux
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wire [15:0] op1_mux = op1_rd & {16{reg_rd[OP1_MPY] |
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wire [15:0] op1_mux = op1_rd & {16{reg_rd[OP1_MPY] |
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reg_rd[OP1_MPYS] |
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reg_rd[OP1_MPYS] |
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reg_rd[OP1_MAC] |
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reg_rd[OP1_MAC] |
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reg_rd[OP1_MACS]}};
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reg_rd[OP1_MACS]}};
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wire [15:0] op2_mux = op2_rd & {16{reg_rd[OP2]}};
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wire [15:0] op2_mux = op2_rd & {16{reg_rd[OP2]}};
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wire [15:0] reslo_mux = reslo_rd & {16{reg_rd[RESLO]}};
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wire [15:0] reslo_mux = reslo_rd & {16{reg_rd[RESLO]}};
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wire [15:0] reshi_mux = reshi_rd & {16{reg_rd[RESHI]}};
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wire [15:0] reshi_mux = reshi_rd & {16{reg_rd[RESHI]}};
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wire [15:0] sumext_mux = sumext_rd & {16{reg_rd[SUMEXT]}};
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wire [15:0] sumext_mux = sumext_rd & {16{reg_rd[SUMEXT]}};
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|
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wire [15:0] per_dout = op1_mux |
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wire [15:0] per_dout = op1_mux |
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op2_mux |
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op2_mux |
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reslo_mux |
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reslo_mux |
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reshi_mux |
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reshi_mux |
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sumext_mux;
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sumext_mux;
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|
|
|
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//============================================================================
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//============================================================================
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// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
|
// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
|
//============================================================================
|
//============================================================================
|
|
|
// Multiplier configuration
|
// Multiplier configuration
|
//--------------------------
|
//--------------------------
|
|
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// Detect signed mode
|
// Detect signed mode
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reg sign_sel;
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reg sign_sel;
|
always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) sign_sel <= 1'b0;
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if (puc) sign_sel <= 1'b0;
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else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
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else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
|
|
|
|
|
// Detect accumulate mode
|
// Detect accumulate mode
|
reg acc_sel;
|
reg acc_sel;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc)
|
if (puc) acc_sel <= 1'b0;
|
if (puc) acc_sel <= 1'b0;
|
else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
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else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
|
|
|
|
|
// Detect whenever the RESHI and RESLO registers should be cleared
|
// Detect whenever the RESHI and RESLO registers should be cleared
|
assign result_clr = op2_wr & ~acc_sel;
|
assign result_clr = op2_wr & ~acc_sel;
|
|
|
// Combine RESHI & RESLO
|
// Combine RESHI & RESLO
|
wire [31:0] result = {reshi, reslo};
|
wire [31:0] result = {reshi, reslo};
|
|
|
|
|
// 16x16 Multiplier (result computed in 1 clock cycle)
|
// 16x16 Multiplier (result computed in 1 clock cycle)
|
//-----------------------------------------------------
|
//-----------------------------------------------------
|
`ifdef MPY_16x16
|
`ifdef MPY_16x16
|
|
|
// Detect start of a multiplication
|
// Detect start of a multiplication
|
reg cycle;
|
reg cycle;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc)
|
if (puc) cycle <= 1'b0;
|
if (puc) cycle <= 1'b0;
|
else cycle <= op2_wr;
|
else cycle <= op2_wr;
|
|
|
assign result_wr = cycle;
|
assign result_wr = cycle;
|
|
|
// Expand the operands to support signed & unsigned operations
|
// Expand the operands to support signed & unsigned operations
|
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
|
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
|
wire signed [16:0] op2_xp = {sign_sel & op2[15], op2};
|
wire signed [16:0] op2_xp = {sign_sel & op2[15], op2};
|
|
|
|
|
// 17x17 signed multiplication
|
// 17x17 signed multiplication
|
wire signed [33:0] product = op1_xp * op2_xp;
|
wire signed [33:0] product = op1_xp * op2_xp;
|
|
|
// Accumulate
|
// Accumulate
|
wire [32:0] result_nxt = {1'b0, result} + {1'b0, product[31:0]};
|
wire [32:0] result_nxt = {1'b0, result} + {1'b0, product[31:0]};
|
|
|
|
|
// Next register values
|
// Next register values
|
assign reslo_nxt = result_nxt[15:0];
|
assign reslo_nxt = result_nxt[15:0];
|
assign reshi_nxt = result_nxt[31:16];
|
assign reshi_nxt = result_nxt[31:16];
|
assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} :
|
assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} :
|
{1'b0, result_nxt[32]};
|
{1'b0, result_nxt[32]};
|
|
|
|
|
// Since the MAC is completed within 1 clock cycle,
|
// Since the MAC is completed within 1 clock cycle,
|
// an early read can't happen.
|
// an early read can't happen.
|
assign early_read = 1'b0;
|
assign early_read = 1'b0;
|
|
|
|
|
// 16x8 Multiplier (result computed in 2 clock cycles)
|
// 16x8 Multiplier (result computed in 2 clock cycles)
|
//-----------------------------------------------------
|
//-----------------------------------------------------
|
`else
|
`else
|
|
|
// Detect start of a multiplication
|
// Detect start of a multiplication
|
reg [1:0] cycle;
|
reg [1:0] cycle;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc)
|
if (puc) cycle <= 2'b00;
|
if (puc) cycle <= 2'b00;
|
else cycle <= {cycle[0], op2_wr};
|
else cycle <= {cycle[0], op2_wr};
|
|
|
assign result_wr = |cycle;
|
assign result_wr = |cycle;
|
|
|
|
|
// Expand the operands to support signed & unsigned operations
|
// Expand the operands to support signed & unsigned operations
|
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
|
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
|
wire signed [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]};
|
wire signed [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]};
|
wire signed [8:0] op2_lo_xp = { 1'b0, op2[7:0]};
|
wire signed [8:0] op2_lo_xp = { 1'b0, op2[7:0]};
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wire signed [8:0] op2_xp = cycle[0] ? op2_hi_xp : op2_lo_xp;
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wire signed [8:0] op2_xp = cycle[0] ? op2_hi_xp : op2_lo_xp;
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// 17x9 signed multiplication
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// 17x9 signed multiplication
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wire signed [25:0] product = op1_xp * op2_xp;
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wire signed [25:0] product = op1_xp * op2_xp;
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wire [31:0] product_xp = cycle[0] ? {product[23:0], 8'h00} :
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wire [31:0] product_xp = cycle[0] ? {product[23:0], 8'h00} :
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{{8{sign_sel & product[23]}}, product[23:0]};
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{{8{sign_sel & product[23]}}, product[23:0]};
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// Accumulate
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// Accumulate
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wire [32:0] result_nxt = {1'b0, result} + {1'b0, product_xp[31:0]};
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wire [32:0] result_nxt = {1'b0, result} + {1'b0, product_xp[31:0]};
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// Next register values
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// Next register values
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assign reslo_nxt = result_nxt[15:0];
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assign reslo_nxt = result_nxt[15:0];
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assign reshi_nxt = result_nxt[31:16];
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assign reshi_nxt = result_nxt[31:16];
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assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} :
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assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} :
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{1'b0, result_nxt[32] | sumext_s[0]};
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{1'b0, result_nxt[32] | sumext_s[0]};
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// Since the MAC is completed within 2 clock cycle,
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// Since the MAC is completed within 2 clock cycle,
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// an early read can happen during the second cycle.
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// an early read can happen during the second cycle.
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assign early_read = cycle[1];
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assign early_read = cycle[1];
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`endif
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`endif
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endmodule // omsp_multiplier
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endmodule // omsp_multiplier
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_undefines.v"
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`include "openMSP430_undefines.v"
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`endif
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`endif
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