//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2009 , Olivier Girard
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//
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//
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// This source file may be used and distributed without restriction provided
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// Redistribution and use in source and binary forms, with or without
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// that this copyright statement is not removed from the file and that any
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// modification, are permitted provided that the following conditions
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// derivative work contains the original copyright notice and the associated
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// are met:
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// disclaimer.
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// it under the terms of the GNU Lesser General Public License as published
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// by the Free Software Foundation; either version 2.1 of the License, or
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// (at your option) any later version.
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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//
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// License for more details.
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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//
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// You should have received a copy of the GNU Lesser General Public License
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// THE POSSIBILITY OF SUCH DAMAGE
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: omsp_timerA.v
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// *File Name: omsp_timerA.v
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//
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//
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// *Module Description:
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// *Module Description:
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// Timer A top-level
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// Timer A top-level
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 111 $
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// $Rev: 136 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_TA_NO_INCLUDE
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`ifdef OMSP_TA_NO_INCLUDE
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`else
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`else
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`include "omsp_timerA_defines.v"
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`include "omsp_timerA_defines.v"
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`endif
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`endif
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module omsp_timerA (
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module omsp_timerA (
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// OUTPUTs
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// OUTPUTs
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irq_ta0, // Timer A interrupt: TACCR0
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irq_ta0, // Timer A interrupt: TACCR0
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irq_ta1, // Timer A interrupt: TAIV, TACCR1, TACCR2
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irq_ta1, // Timer A interrupt: TAIV, TACCR1, TACCR2
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per_dout, // Peripheral data output
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per_dout, // Peripheral data output
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ta_out0, // Timer A output 0
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ta_out0, // Timer A output 0
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ta_out0_en, // Timer A output 0 enable
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ta_out0_en, // Timer A output 0 enable
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ta_out1, // Timer A output 1
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ta_out1, // Timer A output 1
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ta_out1_en, // Timer A output 1 enable
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ta_out1_en, // Timer A output 1 enable
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ta_out2, // Timer A output 2
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ta_out2, // Timer A output 2
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ta_out2_en, // Timer A output 2 enable
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ta_out2_en, // Timer A output 2 enable
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// INPUTs
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// INPUTs
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aclk_en, // ACLK enable (from CPU)
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aclk_en, // ACLK enable (from CPU)
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dbg_freeze, // Freeze Timer A counter
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dbg_freeze, // Freeze Timer A counter
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inclk, // INCLK external timer clock (SLOW)
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inclk, // INCLK external timer clock (SLOW)
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irq_ta0_acc, // Interrupt request TACCR0 accepted
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irq_ta0_acc, // Interrupt request TACCR0 accepted
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mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc_rst, // Main system reset
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puc_rst, // Main system reset
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smclk_en, // SMCLK enable (from CPU)
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smclk_en, // SMCLK enable (from CPU)
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ta_cci0a, // Timer A capture 0 input A
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ta_cci0a, // Timer A capture 0 input A
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ta_cci0b, // Timer A capture 0 input B
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ta_cci0b, // Timer A capture 0 input B
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ta_cci1a, // Timer A capture 1 input A
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ta_cci1a, // Timer A capture 1 input A
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ta_cci1b, // Timer A capture 1 input B
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ta_cci1b, // Timer A capture 1 input B
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ta_cci2a, // Timer A capture 2 input A
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ta_cci2a, // Timer A capture 2 input A
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ta_cci2b, // Timer A capture 2 input B
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ta_cci2b, // Timer A capture 2 input B
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taclk // TACLK external timer clock (SLOW)
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taclk // TACLK external timer clock (SLOW)
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output irq_ta0; // Timer A interrupt: TACCR0
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output irq_ta0; // Timer A interrupt: TACCR0
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output irq_ta1; // Timer A interrupt: TAIV, TACCR1, TACCR2
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output irq_ta1; // Timer A interrupt: TAIV, TACCR1, TACCR2
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output [15:0] per_dout; // Peripheral data output
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output [15:0] per_dout; // Peripheral data output
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output ta_out0; // Timer A output 0
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output ta_out0; // Timer A output 0
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output ta_out0_en; // Timer A output 0 enable
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output ta_out0_en; // Timer A output 0 enable
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output ta_out1; // Timer A output 1
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output ta_out1; // Timer A output 1
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output ta_out1_en; // Timer A output 1 enable
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output ta_out1_en; // Timer A output 1 enable
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output ta_out2; // Timer A output 2
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output ta_out2; // Timer A output 2
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output ta_out2_en; // Timer A output 2 enable
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output ta_out2_en; // Timer A output 2 enable
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// INPUTs
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// INPUTs
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//=========
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//=========
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input aclk_en; // ACLK enable (from CPU)
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input aclk_en; // ACLK enable (from CPU)
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input dbg_freeze; // Freeze Timer A counter
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input dbg_freeze; // Freeze Timer A counter
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input inclk; // INCLK external timer clock (SLOW)
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input inclk; // INCLK external timer clock (SLOW)
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input irq_ta0_acc; // Interrupt request TACCR0 accepted
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input irq_ta0_acc; // Interrupt request TACCR0 accepted
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [13:0] per_addr; // Peripheral address
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input smclk_en; // SMCLK enable (from CPU)
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input smclk_en; // SMCLK enable (from CPU)
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input ta_cci0a; // Timer A capture 0 input A
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input ta_cci0a; // Timer A capture 0 input A
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input ta_cci0b; // Timer A capture 0 input B
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input ta_cci0b; // Timer A capture 0 input B
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input ta_cci1a; // Timer A capture 1 input A
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input ta_cci1a; // Timer A capture 1 input A
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input ta_cci1b; // Timer A capture 1 input B
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input ta_cci1b; // Timer A capture 1 input B
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input ta_cci2a; // Timer A capture 2 input A
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input ta_cci2a; // Timer A capture 2 input A
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input ta_cci2b; // Timer A capture 2 input B
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input ta_cci2b; // Timer A capture 2 input B
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input taclk; // TACLK external timer clock (SLOW)
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input taclk; // TACLK external timer clock (SLOW)
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER DECLARATION
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// 1) PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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// Register base address (must be aligned to decoder bit width)
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// Register base address (must be aligned to decoder bit width)
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parameter [14:0] BASE_ADDR = 15'h0100;
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parameter [14:0] BASE_ADDR = 15'h0100;
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// Decoder bit width (defines how many bits are considered for address decoding)
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DEC_WD = 7;
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parameter DEC_WD = 7;
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// Register addresses offset
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// Register addresses offset
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parameter [DEC_WD-1:0] TACTL = 'h60,
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parameter [DEC_WD-1:0] TACTL = 'h60,
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TAR = 'h70,
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TAR = 'h70,
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TACCTL0 = 'h62,
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TACCTL0 = 'h62,
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TACCR0 = 'h72,
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TACCR0 = 'h72,
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TACCTL1 = 'h64,
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TACCTL1 = 'h64,
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TACCR1 = 'h74,
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TACCR1 = 'h74,
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TACCTL2 = 'h66,
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TACCTL2 = 'h66,
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TACCR2 = 'h76,
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TACCR2 = 'h76,
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TAIV = 'h2E;
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TAIV = 'h2E;
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// Register one-hot decoder utilities
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter DEC_SZ = (1 << DEC_WD);
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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// Register one-hot decoder
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parameter [DEC_SZ-1:0] TACTL_D = (BASE_REG << TACTL),
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parameter [DEC_SZ-1:0] TACTL_D = (BASE_REG << TACTL),
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TAR_D = (BASE_REG << TAR),
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TAR_D = (BASE_REG << TAR),
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TACCTL0_D = (BASE_REG << TACCTL0),
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TACCTL0_D = (BASE_REG << TACCTL0),
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TACCR0_D = (BASE_REG << TACCR0),
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TACCR0_D = (BASE_REG << TACCR0),
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TACCTL1_D = (BASE_REG << TACCTL1),
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TACCTL1_D = (BASE_REG << TACCTL1),
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TACCR1_D = (BASE_REG << TACCR1),
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TACCR1_D = (BASE_REG << TACCR1),
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TACCTL2_D = (BASE_REG << TACCTL2),
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TACCTL2_D = (BASE_REG << TACCTL2),
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TACCR2_D = (BASE_REG << TACCR2),
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TACCR2_D = (BASE_REG << TACCR2),
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TAIV_D = (BASE_REG << TAIV);
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TAIV_D = (BASE_REG << TAIV);
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// Local register selection
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// Local register selection
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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// Register local address
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wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
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wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
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// Register address decode
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// Register address decode
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wire [DEC_SZ-1:0] reg_dec = (TACTL_D & {DEC_SZ{(reg_addr == TACTL )}}) |
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wire [DEC_SZ-1:0] reg_dec = (TACTL_D & {DEC_SZ{(reg_addr == TACTL )}}) |
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(TAR_D & {DEC_SZ{(reg_addr == TAR )}}) |
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(TAR_D & {DEC_SZ{(reg_addr == TAR )}}) |
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(TACCTL0_D & {DEC_SZ{(reg_addr == TACCTL0 )}}) |
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(TACCTL0_D & {DEC_SZ{(reg_addr == TACCTL0 )}}) |
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(TACCR0_D & {DEC_SZ{(reg_addr == TACCR0 )}}) |
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(TACCR0_D & {DEC_SZ{(reg_addr == TACCR0 )}}) |
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(TACCTL1_D & {DEC_SZ{(reg_addr == TACCTL1 )}}) |
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(TACCTL1_D & {DEC_SZ{(reg_addr == TACCTL1 )}}) |
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(TACCR1_D & {DEC_SZ{(reg_addr == TACCR1 )}}) |
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(TACCR1_D & {DEC_SZ{(reg_addr == TACCR1 )}}) |
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(TACCTL2_D & {DEC_SZ{(reg_addr == TACCTL2 )}}) |
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(TACCTL2_D & {DEC_SZ{(reg_addr == TACCTL2 )}}) |
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(TACCR2_D & {DEC_SZ{(reg_addr == TACCR2 )}}) |
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(TACCR2_D & {DEC_SZ{(reg_addr == TACCR2 )}}) |
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(TAIV_D & {DEC_SZ{(reg_addr == TAIV )}});
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(TAIV_D & {DEC_SZ{(reg_addr == TAIV )}});
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// Read/Write probes
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// Read/Write probes
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wire reg_write = |per_we & reg_sel;
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wire reg_write = |per_we & reg_sel;
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wire reg_read = ~|per_we & reg_sel;
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wire reg_read = ~|per_we & reg_sel;
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// Read/Write vectors
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// Read/Write vectors
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wire [DEC_SZ-1:0] reg_wr = reg_dec & {512{reg_write}};
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wire [DEC_SZ-1:0] reg_wr = reg_dec & {512{reg_write}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {512{reg_read}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {512{reg_read}};
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//============================================================================
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//============================================================================
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// 3) REGISTERS
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// 3) REGISTERS
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//============================================================================
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//============================================================================
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// TACTL Register
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// TACTL Register
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//-----------------
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//-----------------
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reg [9:0] tactl;
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reg [9:0] tactl;
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wire tactl_wr = reg_wr[TACTL];
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wire tactl_wr = reg_wr[TACTL];
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wire taclr = tactl_wr & per_din[`TACLR];
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wire taclr = tactl_wr & per_din[`TACLR];
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wire taifg_set;
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wire taifg_set;
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wire taifg_clr;
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wire taifg_clr;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) tactl <= 10'h000;
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if (puc_rst) tactl <= 10'h000;
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else if (tactl_wr) tactl <= ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
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else if (tactl_wr) tactl <= ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
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else tactl <= (tactl | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
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else tactl <= (tactl | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
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// TAR Register
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// TAR Register
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//-----------------
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//-----------------
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reg [15:0] tar;
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reg [15:0] tar;
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wire tar_wr = reg_wr[TAR];
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wire tar_wr = reg_wr[TAR];
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wire tar_clk;
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wire tar_clk;
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wire tar_clr;
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wire tar_clr;
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wire tar_inc;
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wire tar_inc;
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wire tar_dec;
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wire tar_dec;
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wire [15:0] tar_add = tar_inc ? 16'h0001 :
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wire [15:0] tar_add = tar_inc ? 16'h0001 :
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tar_dec ? 16'hffff : 16'h0000;
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tar_dec ? 16'hffff : 16'h0000;
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wire [15:0] tar_nxt = tar_clr ? 16'h0000 : (tar+tar_add);
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wire [15:0] tar_nxt = tar_clr ? 16'h0000 : (tar+tar_add);
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) tar <= 16'h0000;
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if (puc_rst) tar <= 16'h0000;
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else if (tar_wr) tar <= per_din;
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else if (tar_wr) tar <= per_din;
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else if (taclr) tar <= 16'h0000;
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else if (taclr) tar <= 16'h0000;
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else if (tar_clk & ~dbg_freeze) tar <= tar_nxt;
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else if (tar_clk & ~dbg_freeze) tar <= tar_nxt;
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// TACCTL0 Register
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// TACCTL0 Register
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//------------------
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//------------------
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reg [15:0] tacctl0;
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reg [15:0] tacctl0;
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wire tacctl0_wr = reg_wr[TACCTL0];
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wire tacctl0_wr = reg_wr[TACCTL0];
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wire ccifg0_set;
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wire ccifg0_set;
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wire cov0_set;
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wire cov0_set;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) tacctl0 <= 16'h0000;
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if (puc_rst) tacctl0 <= 16'h0000;
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else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
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else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
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else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
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else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
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wire cci0;
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wire cci0;
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reg scci0;
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reg scci0;
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wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0, 3'h0};
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wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0, 3'h0};
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// TACCR0 Register
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// TACCR0 Register
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//------------------
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//------------------
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reg [15:0] taccr0;
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reg [15:0] taccr0;
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|
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wire taccr0_wr = reg_wr[TACCR0];
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wire taccr0_wr = reg_wr[TACCR0];
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wire cci0_cap;
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wire cci0_cap;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) taccr0 <= 16'h0000;
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if (puc_rst) taccr0 <= 16'h0000;
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else if (taccr0_wr) taccr0 <= per_din;
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else if (taccr0_wr) taccr0 <= per_din;
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else if (cci0_cap) taccr0 <= tar;
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else if (cci0_cap) taccr0 <= tar;
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// TACCTL1 Register
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// TACCTL1 Register
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//------------------
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//------------------
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reg [15:0] tacctl1;
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reg [15:0] tacctl1;
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|
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wire tacctl1_wr = reg_wr[TACCTL1];
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wire tacctl1_wr = reg_wr[TACCTL1];
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wire ccifg1_set;
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wire ccifg1_set;
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wire ccifg1_clr;
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wire ccifg1_clr;
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wire cov1_set;
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wire cov1_set;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) tacctl1 <= 16'h0000;
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if (puc_rst) tacctl1 <= 16'h0000;
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else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
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else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
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else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
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else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
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wire cci1;
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wire cci1;
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reg scci1;
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reg scci1;
|
wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1, 3'h0};
|
wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1, 3'h0};
|
|
|
|
|
// TACCR1 Register
|
// TACCR1 Register
|
//------------------
|
//------------------
|
reg [15:0] taccr1;
|
reg [15:0] taccr1;
|
|
|
wire taccr1_wr = reg_wr[TACCR1];
|
wire taccr1_wr = reg_wr[TACCR1];
|
wire cci1_cap;
|
wire cci1_cap;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) taccr1 <= 16'h0000;
|
if (puc_rst) taccr1 <= 16'h0000;
|
else if (taccr1_wr) taccr1 <= per_din;
|
else if (taccr1_wr) taccr1 <= per_din;
|
else if (cci1_cap) taccr1 <= tar;
|
else if (cci1_cap) taccr1 <= tar;
|
|
|
|
|
// TACCTL2 Register
|
// TACCTL2 Register
|
//------------------
|
//------------------
|
reg [15:0] tacctl2;
|
reg [15:0] tacctl2;
|
|
|
wire tacctl2_wr = reg_wr[TACCTL2];
|
wire tacctl2_wr = reg_wr[TACCTL2];
|
wire ccifg2_set;
|
wire ccifg2_set;
|
wire ccifg2_clr;
|
wire ccifg2_clr;
|
wire cov2_set;
|
wire cov2_set;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) tacctl2 <= 16'h0000;
|
if (puc_rst) tacctl2 <= 16'h0000;
|
else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
|
else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
|
else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
|
else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
|
|
|
wire cci2;
|
wire cci2;
|
reg scci2;
|
reg scci2;
|
wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2, 3'h0};
|
wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2, 3'h0};
|
|
|
|
|
// TACCR2 Register
|
// TACCR2 Register
|
//------------------
|
//------------------
|
reg [15:0] taccr2;
|
reg [15:0] taccr2;
|
|
|
wire taccr2_wr = reg_wr[TACCR2];
|
wire taccr2_wr = reg_wr[TACCR2];
|
wire cci2_cap;
|
wire cci2_cap;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) taccr2 <= 16'h0000;
|
if (puc_rst) taccr2 <= 16'h0000;
|
else if (taccr2_wr) taccr2 <= per_din;
|
else if (taccr2_wr) taccr2 <= per_din;
|
else if (cci2_cap) taccr2 <= tar;
|
else if (cci2_cap) taccr2 <= tar;
|
|
|
|
|
// TAIV Register
|
// TAIV Register
|
//------------------
|
//------------------
|
|
|
wire [3:0] taiv = (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) ? 4'h2 :
|
wire [3:0] taiv = (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) ? 4'h2 :
|
(tacctl2[`TACCIFG] & tacctl2[`TACCIE]) ? 4'h4 :
|
(tacctl2[`TACCIFG] & tacctl2[`TACCIE]) ? 4'h4 :
|
(tactl[`TAIFG] & tactl[`TAIE]) ? 4'hA :
|
(tactl[`TAIFG] & tactl[`TAIE]) ? 4'hA :
|
4'h0;
|
4'h0;
|
|
|
assign ccifg1_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h2);
|
assign ccifg1_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h2);
|
assign ccifg2_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h4);
|
assign ccifg2_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h4);
|
assign taifg_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'hA);
|
assign taifg_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'hA);
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 4) DATA OUTPUT GENERATION
|
// 4) DATA OUTPUT GENERATION
|
//============================================================================
|
//============================================================================
|
|
|
// Data output mux
|
// Data output mux
|
wire [15:0] tactl_rd = {6'h00, tactl} & {16{reg_rd[TACTL]}};
|
wire [15:0] tactl_rd = {6'h00, tactl} & {16{reg_rd[TACTL]}};
|
wire [15:0] tar_rd = tar & {16{reg_rd[TAR]}};
|
wire [15:0] tar_rd = tar & {16{reg_rd[TAR]}};
|
wire [15:0] tacctl0_rd = tacctl0_full & {16{reg_rd[TACCTL0]}};
|
wire [15:0] tacctl0_rd = tacctl0_full & {16{reg_rd[TACCTL0]}};
|
wire [15:0] taccr0_rd = taccr0 & {16{reg_rd[TACCR0]}};
|
wire [15:0] taccr0_rd = taccr0 & {16{reg_rd[TACCR0]}};
|
wire [15:0] tacctl1_rd = tacctl1_full & {16{reg_rd[TACCTL1]}};
|
wire [15:0] tacctl1_rd = tacctl1_full & {16{reg_rd[TACCTL1]}};
|
wire [15:0] taccr1_rd = taccr1 & {16{reg_rd[TACCR1]}};
|
wire [15:0] taccr1_rd = taccr1 & {16{reg_rd[TACCR1]}};
|
wire [15:0] tacctl2_rd = tacctl2_full & {16{reg_rd[TACCTL2]}};
|
wire [15:0] tacctl2_rd = tacctl2_full & {16{reg_rd[TACCTL2]}};
|
wire [15:0] taccr2_rd = taccr2 & {16{reg_rd[TACCR2]}};
|
wire [15:0] taccr2_rd = taccr2 & {16{reg_rd[TACCR2]}};
|
wire [15:0] taiv_rd = {12'h000, taiv} & {16{reg_rd[TAIV]}};
|
wire [15:0] taiv_rd = {12'h000, taiv} & {16{reg_rd[TAIV]}};
|
|
|
wire [15:0] per_dout = tactl_rd |
|
wire [15:0] per_dout = tactl_rd |
|
tar_rd |
|
tar_rd |
|
tacctl0_rd |
|
tacctl0_rd |
|
taccr0_rd |
|
taccr0_rd |
|
tacctl1_rd |
|
tacctl1_rd |
|
taccr1_rd |
|
taccr1_rd |
|
tacctl2_rd |
|
tacctl2_rd |
|
taccr2_rd |
|
taccr2_rd |
|
taiv_rd;
|
taiv_rd;
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 5) Timer A counter control
|
// 5) Timer A counter control
|
//============================================================================
|
//============================================================================
|
|
|
// Clock input synchronization (TACLK & INCLK)
|
// Clock input synchronization (TACLK & INCLK)
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
wire taclk_s;
|
wire taclk_s;
|
wire inclk_s;
|
wire inclk_s;
|
|
|
omsp_sync_cell sync_cell_taclk (
|
omsp_sync_cell sync_cell_taclk (
|
.data_out (taclk_s),
|
.data_out (taclk_s),
|
.clk (mclk),
|
|
.data_in (taclk),
|
.data_in (taclk),
|
|
.clk (mclk),
|
.rst (puc_rst)
|
.rst (puc_rst)
|
);
|
);
|
|
|
omsp_sync_cell sync_cell_inclk (
|
omsp_sync_cell sync_cell_inclk (
|
.data_out (inclk_s),
|
.data_out (inclk_s),
|
.clk (mclk),
|
|
.data_in (inclk),
|
.data_in (inclk),
|
|
.clk (mclk),
|
.rst (puc_rst)
|
.rst (puc_rst)
|
);
|
);
|
|
|
|
|
// Clock edge detection (TACLK & INCLK)
|
// Clock edge detection (TACLK & INCLK)
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
|
|
reg taclk_dly;
|
reg taclk_dly;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) taclk_dly <= 1'b0;
|
if (puc_rst) taclk_dly <= 1'b0;
|
else taclk_dly <= taclk_s;
|
else taclk_dly <= taclk_s;
|
|
|
wire taclk_en = taclk_s & ~taclk_dly;
|
wire taclk_en = taclk_s & ~taclk_dly;
|
|
|
|
|
reg inclk_dly;
|
reg inclk_dly;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) inclk_dly <= 1'b0;
|
if (puc_rst) inclk_dly <= 1'b0;
|
else inclk_dly <= inclk_s;
|
else inclk_dly <= inclk_s;
|
|
|
wire inclk_en = inclk_s & ~inclk_dly;
|
wire inclk_en = inclk_s & ~inclk_dly;
|
|
|
|
|
// Timer clock input mux
|
// Timer clock input mux
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
|
|
wire sel_clk = (tactl[`TASSELx]==2'b00) ? taclk_en :
|
wire sel_clk = (tactl[`TASSELx]==2'b00) ? taclk_en :
|
(tactl[`TASSELx]==2'b01) ? aclk_en :
|
(tactl[`TASSELx]==2'b01) ? aclk_en :
|
(tactl[`TASSELx]==2'b10) ? smclk_en : inclk_en;
|
(tactl[`TASSELx]==2'b10) ? smclk_en : inclk_en;
|
|
|
|
|
// Generate update pluse for the counter (<=> divided clock)
|
// Generate update pluse for the counter (<=> divided clock)
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
reg [2:0] clk_div;
|
reg [2:0] clk_div;
|
|
|
assign tar_clk = sel_clk & ((tactl[`TAIDx]==2'b00) ? 1'b1 :
|
assign tar_clk = sel_clk & ((tactl[`TAIDx]==2'b00) ? 1'b1 :
|
(tactl[`TAIDx]==2'b01) ? clk_div[0] :
|
(tactl[`TAIDx]==2'b01) ? clk_div[0] :
|
(tactl[`TAIDx]==2'b10) ? &clk_div[1:0] :
|
(tactl[`TAIDx]==2'b10) ? &clk_div[1:0] :
|
&clk_div[2:0]);
|
&clk_div[2:0]);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) clk_div <= 3'h0;
|
if (puc_rst) clk_div <= 3'h0;
|
else if (tar_clk | taclr) clk_div <= 3'h0;
|
else if (tar_clk | taclr) clk_div <= 3'h0;
|
else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <= clk_div+3'h1;
|
else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <= clk_div+3'h1;
|
|
|
|
|
// Time counter control signals
|
// Time counter control signals
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
|
|
assign tar_clr = ((tactl[`TAMCx]==2'b01) & (tar>=taccr0)) |
|
assign tar_clr = ((tactl[`TAMCx]==2'b01) & (tar>=taccr0)) |
|
((tactl[`TAMCx]==2'b11) & (taccr0==16'h0000));
|
((tactl[`TAMCx]==2'b11) & (taccr0==16'h0000));
|
|
|
assign tar_inc = (tactl[`TAMCx]==2'b01) | (tactl[`TAMCx]==2'b10) |
|
assign tar_inc = (tactl[`TAMCx]==2'b01) | (tactl[`TAMCx]==2'b10) |
|
((tactl[`TAMCx]==2'b11) & ~tar_dec);
|
((tactl[`TAMCx]==2'b11) & ~tar_dec);
|
|
|
reg tar_dir;
|
reg tar_dir;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) tar_dir <= 1'b0;
|
if (puc_rst) tar_dir <= 1'b0;
|
else if (taclr) tar_dir <= 1'b0;
|
else if (taclr) tar_dir <= 1'b0;
|
else if (tactl[`TAMCx]==2'b11)
|
else if (tactl[`TAMCx]==2'b11)
|
begin
|
begin
|
if (tar_clk & (tar==16'h0001)) tar_dir <= 1'b0;
|
if (tar_clk & (tar==16'h0001)) tar_dir <= 1'b0;
|
else if (tar>=taccr0) tar_dir <= 1'b1;
|
else if (tar>=taccr0) tar_dir <= 1'b1;
|
end
|
end
|
else tar_dir <= 1'b0;
|
else tar_dir <= 1'b0;
|
|
|
assign tar_dec = tar_dir | ((tactl[`TAMCx]==2'b11) & (tar>=taccr0));
|
assign tar_dec = tar_dir | ((tactl[`TAMCx]==2'b11) & (tar>=taccr0));
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 6) Timer A comparator
|
// 6) Timer A comparator
|
//============================================================================
|
//============================================================================
|
|
|
wire equ0 = (tar_nxt==taccr0) & (tar!=taccr0);
|
wire equ0 = (tar_nxt==taccr0) & (tar!=taccr0);
|
wire equ1 = (tar_nxt==taccr1) & (tar!=taccr1);
|
wire equ1 = (tar_nxt==taccr1) & (tar!=taccr1);
|
wire equ2 = (tar_nxt==taccr2) & (tar!=taccr2);
|
wire equ2 = (tar_nxt==taccr2) & (tar!=taccr2);
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 7) Timer A capture logic
|
// 7) Timer A capture logic
|
//============================================================================
|
//============================================================================
|
|
|
// Input selection
|
// Input selection
|
//------------------
|
//------------------
|
assign cci0 = (tacctl0[`TACCISx]==2'b00) ? ta_cci0a :
|
assign cci0 = (tacctl0[`TACCISx]==2'b00) ? ta_cci0a :
|
(tacctl0[`TACCISx]==2'b01) ? ta_cci0b :
|
(tacctl0[`TACCISx]==2'b01) ? ta_cci0b :
|
(tacctl0[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
|
(tacctl0[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
|
|
|
assign cci1 = (tacctl1[`TACCISx]==2'b00) ? ta_cci1a :
|
assign cci1 = (tacctl1[`TACCISx]==2'b00) ? ta_cci1a :
|
(tacctl1[`TACCISx]==2'b01) ? ta_cci1b :
|
(tacctl1[`TACCISx]==2'b01) ? ta_cci1b :
|
(tacctl1[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
|
(tacctl1[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
|
|
|
assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
|
assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
|
(tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
|
(tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
|
(tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
|
(tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
|
|
|
// CCIx synchronization
|
// CCIx synchronization
|
wire cci0_s;
|
wire cci0_s;
|
wire cci1_s;
|
wire cci1_s;
|
wire cci2_s;
|
wire cci2_s;
|
|
|
omsp_sync_cell sync_cell_cci0 (
|
omsp_sync_cell sync_cell_cci0 (
|
.data_out (cci0_s),
|
.data_out (cci0_s),
|
.clk (mclk),
|
|
.data_in (cci0),
|
.data_in (cci0),
|
|
.clk (mclk),
|
.rst (puc_rst)
|
.rst (puc_rst)
|
);
|
);
|
omsp_sync_cell sync_cell_cci1 (
|
omsp_sync_cell sync_cell_cci1 (
|
.data_out (cci1_s),
|
.data_out (cci1_s),
|
.clk (mclk),
|
|
.data_in (cci1),
|
.data_in (cci1),
|
|
.clk (mclk),
|
.rst (puc_rst)
|
.rst (puc_rst)
|
);
|
);
|
omsp_sync_cell sync_cell_cci2 (
|
omsp_sync_cell sync_cell_cci2 (
|
.data_out (cci2_s),
|
.data_out (cci2_s),
|
.clk (mclk),
|
|
.data_in (cci2),
|
.data_in (cci2),
|
|
.clk (mclk),
|
.rst (puc_rst)
|
.rst (puc_rst)
|
);
|
);
|
|
|
// Register CCIx for edge detection
|
// Register CCIx for edge detection
|
reg cci0_dly;
|
reg cci0_dly;
|
reg cci1_dly;
|
reg cci1_dly;
|
reg cci2_dly;
|
reg cci2_dly;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst)
|
if (puc_rst)
|
begin
|
begin
|
cci0_dly <= 1'b0;
|
cci0_dly <= 1'b0;
|
cci1_dly <= 1'b0;
|
cci1_dly <= 1'b0;
|
cci2_dly <= 1'b0;
|
cci2_dly <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cci0_dly <= cci0_s;
|
cci0_dly <= cci0_s;
|
cci1_dly <= cci1_s;
|
cci1_dly <= cci1_s;
|
cci2_dly <= cci2_s;
|
cci2_dly <= cci2_s;
|
end
|
end
|
|
|
|
|
// Generate SCCIx
|
// Generate SCCIx
|
//------------------
|
//------------------
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) scci0 <= 1'b0;
|
if (puc_rst) scci0 <= 1'b0;
|
else if (tar_clk & equ0) scci0 <= cci0_s;
|
else if (tar_clk & equ0) scci0 <= cci0_s;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) scci1 <= 1'b0;
|
if (puc_rst) scci1 <= 1'b0;
|
else if (tar_clk & equ1) scci1 <= cci1_s;
|
else if (tar_clk & equ1) scci1 <= cci1_s;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) scci2 <= 1'b0;
|
if (puc_rst) scci2 <= 1'b0;
|
else if (tar_clk & equ2) scci2 <= cci2_s;
|
else if (tar_clk & equ2) scci2 <= cci2_s;
|
|
|
|
|
// Capture mode
|
// Capture mode
|
//------------------
|
//------------------
|
wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0 :
|
wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0 :
|
(tacctl0[`TACMx]==2'b01) ? ( cci0_s & ~cci0_dly) : // Rising edge
|
(tacctl0[`TACMx]==2'b01) ? ( cci0_s & ~cci0_dly) : // Rising edge
|
(tacctl0[`TACMx]==2'b10) ? (~cci0_s & cci0_dly) : // Falling edge
|
(tacctl0[`TACMx]==2'b10) ? (~cci0_s & cci0_dly) : // Falling edge
|
( cci0_s ^ cci0_dly); // Both edges
|
( cci0_s ^ cci0_dly); // Both edges
|
|
|
wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0 :
|
wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0 :
|
(tacctl1[`TACMx]==2'b01) ? ( cci1_s & ~cci1_dly) : // Rising edge
|
(tacctl1[`TACMx]==2'b01) ? ( cci1_s & ~cci1_dly) : // Rising edge
|
(tacctl1[`TACMx]==2'b10) ? (~cci1_s & cci1_dly) : // Falling edge
|
(tacctl1[`TACMx]==2'b10) ? (~cci1_s & cci1_dly) : // Falling edge
|
( cci1_s ^ cci1_dly); // Both edges
|
( cci1_s ^ cci1_dly); // Both edges
|
|
|
wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0 :
|
wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0 :
|
(tacctl2[`TACMx]==2'b01) ? ( cci2_s & ~cci2_dly) : // Rising edge
|
(tacctl2[`TACMx]==2'b01) ? ( cci2_s & ~cci2_dly) : // Rising edge
|
(tacctl2[`TACMx]==2'b10) ? (~cci2_s & cci2_dly) : // Falling edge
|
(tacctl2[`TACMx]==2'b10) ? (~cci2_s & cci2_dly) : // Falling edge
|
( cci2_s ^ cci2_dly); // Both edges
|
( cci2_s ^ cci2_dly); // Both edges
|
|
|
// Event Synchronization
|
// Event Synchronization
|
//-----------------------
|
//-----------------------
|
|
|
reg cci0_evt_s;
|
reg cci0_evt_s;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cci0_evt_s <= 1'b0;
|
if (puc_rst) cci0_evt_s <= 1'b0;
|
else if (tar_clk) cci0_evt_s <= 1'b0;
|
else if (tar_clk) cci0_evt_s <= 1'b0;
|
else if (cci0_evt) cci0_evt_s <= 1'b1;
|
else if (cci0_evt) cci0_evt_s <= 1'b1;
|
|
|
reg cci1_evt_s;
|
reg cci1_evt_s;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cci1_evt_s <= 1'b0;
|
if (puc_rst) cci1_evt_s <= 1'b0;
|
else if (tar_clk) cci1_evt_s <= 1'b0;
|
else if (tar_clk) cci1_evt_s <= 1'b0;
|
else if (cci1_evt) cci1_evt_s <= 1'b1;
|
else if (cci1_evt) cci1_evt_s <= 1'b1;
|
|
|
reg cci2_evt_s;
|
reg cci2_evt_s;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cci2_evt_s <= 1'b0;
|
if (puc_rst) cci2_evt_s <= 1'b0;
|
else if (tar_clk) cci2_evt_s <= 1'b0;
|
else if (tar_clk) cci2_evt_s <= 1'b0;
|
else if (cci2_evt) cci2_evt_s <= 1'b1;
|
else if (cci2_evt) cci2_evt_s <= 1'b1;
|
|
|
reg cci0_sync;
|
reg cci0_sync;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cci0_sync <= 1'b0;
|
if (puc_rst) cci0_sync <= 1'b0;
|
else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s);
|
else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s);
|
|
|
reg cci1_sync;
|
reg cci1_sync;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cci1_sync <= 1'b0;
|
if (puc_rst) cci1_sync <= 1'b0;
|
else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s);
|
else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s);
|
|
|
reg cci2_sync;
|
reg cci2_sync;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cci2_sync <= 1'b0;
|
if (puc_rst) cci2_sync <= 1'b0;
|
else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s);
|
else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s);
|
|
|
|
|
// Generate final capture command
|
// Generate final capture command
|
//-----------------------------------
|
//-----------------------------------
|
|
|
assign cci0_cap = tacctl0[`TASCS] ? cci0_sync : cci0_evt;
|
assign cci0_cap = tacctl0[`TASCS] ? cci0_sync : cci0_evt;
|
assign cci1_cap = tacctl1[`TASCS] ? cci1_sync : cci1_evt;
|
assign cci1_cap = tacctl1[`TASCS] ? cci1_sync : cci1_evt;
|
assign cci2_cap = tacctl2[`TASCS] ? cci2_sync : cci2_evt;
|
assign cci2_cap = tacctl2[`TASCS] ? cci2_sync : cci2_evt;
|
|
|
|
|
// Generate capture overflow flag
|
// Generate capture overflow flag
|
//-----------------------------------
|
//-----------------------------------
|
|
|
reg cap0_taken;
|
reg cap0_taken;
|
wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]);
|
wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]);
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cap0_taken <= 1'b0;
|
if (puc_rst) cap0_taken <= 1'b0;
|
else if (cci0_cap) cap0_taken <= 1'b1;
|
else if (cci0_cap) cap0_taken <= 1'b1;
|
else if (cap0_taken_clr) cap0_taken <= 1'b0;
|
else if (cap0_taken_clr) cap0_taken <= 1'b0;
|
|
|
reg cap1_taken;
|
reg cap1_taken;
|
wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]);
|
wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]);
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cap1_taken <= 1'b0;
|
if (puc_rst) cap1_taken <= 1'b0;
|
else if (cci1_cap) cap1_taken <= 1'b1;
|
else if (cci1_cap) cap1_taken <= 1'b1;
|
else if (cap1_taken_clr) cap1_taken <= 1'b0;
|
else if (cap1_taken_clr) cap1_taken <= 1'b0;
|
|
|
reg cap2_taken;
|
reg cap2_taken;
|
wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]);
|
wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]);
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) cap2_taken <= 1'b0;
|
if (puc_rst) cap2_taken <= 1'b0;
|
else if (cci2_cap) cap2_taken <= 1'b1;
|
else if (cci2_cap) cap2_taken <= 1'b1;
|
else if (cap2_taken_clr) cap2_taken <= 1'b0;
|
else if (cap2_taken_clr) cap2_taken <= 1'b0;
|
|
|
|
|
assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0];
|
assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0];
|
assign cov1_set = cap1_taken & cci1_cap & ~reg_rd[TACCR1];
|
assign cov1_set = cap1_taken & cci1_cap & ~reg_rd[TACCR1];
|
assign cov2_set = cap2_taken & cci2_cap & ~reg_rd[TACCR2];
|
assign cov2_set = cap2_taken & cci2_cap & ~reg_rd[TACCR2];
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 8) Timer A output unit
|
// 8) Timer A output unit
|
//============================================================================
|
//============================================================================
|
|
|
// Output unit 0
|
// Output unit 0
|
//-------------------
|
//-------------------
|
reg ta_out0;
|
reg ta_out0;
|
|
|
wire ta_out0_mode0 = tacctl0[`TAOUT]; // Output
|
wire ta_out0_mode0 = tacctl0[`TAOUT]; // Output
|
wire ta_out0_mode1 = equ0 ? 1'b1 : ta_out0; // Set
|
wire ta_out0_mode1 = equ0 ? 1'b1 : ta_out0; // Set
|
wire ta_out0_mode2 = equ0 ? ~ta_out0 : // Toggle/Reset
|
wire ta_out0_mode2 = equ0 ? ~ta_out0 : // Toggle/Reset
|
equ0 ? 1'b0 : ta_out0;
|
equ0 ? 1'b0 : ta_out0;
|
wire ta_out0_mode3 = equ0 ? 1'b1 : // Set/Reset
|
wire ta_out0_mode3 = equ0 ? 1'b1 : // Set/Reset
|
equ0 ? 1'b0 : ta_out0;
|
equ0 ? 1'b0 : ta_out0;
|
wire ta_out0_mode4 = equ0 ? ~ta_out0 : ta_out0; // Toggle
|
wire ta_out0_mode4 = equ0 ? ~ta_out0 : ta_out0; // Toggle
|
wire ta_out0_mode5 = equ0 ? 1'b0 : ta_out0; // Reset
|
wire ta_out0_mode5 = equ0 ? 1'b0 : ta_out0; // Reset
|
wire ta_out0_mode6 = equ0 ? ~ta_out0 : // Toggle/Set
|
wire ta_out0_mode6 = equ0 ? ~ta_out0 : // Toggle/Set
|
equ0 ? 1'b1 : ta_out0;
|
equ0 ? 1'b1 : ta_out0;
|
wire ta_out0_mode7 = equ0 ? 1'b0 : // Reset/Set
|
wire ta_out0_mode7 = equ0 ? 1'b0 : // Reset/Set
|
equ0 ? 1'b1 : ta_out0;
|
equ0 ? 1'b1 : ta_out0;
|
|
|
wire ta_out0_nxt = (tacctl0[`TAOUTMODx]==3'b000) ? ta_out0_mode0 :
|
wire ta_out0_nxt = (tacctl0[`TAOUTMODx]==3'b000) ? ta_out0_mode0 :
|
(tacctl0[`TAOUTMODx]==3'b001) ? ta_out0_mode1 :
|
(tacctl0[`TAOUTMODx]==3'b001) ? ta_out0_mode1 :
|
(tacctl0[`TAOUTMODx]==3'b010) ? ta_out0_mode2 :
|
(tacctl0[`TAOUTMODx]==3'b010) ? ta_out0_mode2 :
|
(tacctl0[`TAOUTMODx]==3'b011) ? ta_out0_mode3 :
|
(tacctl0[`TAOUTMODx]==3'b011) ? ta_out0_mode3 :
|
(tacctl0[`TAOUTMODx]==3'b100) ? ta_out0_mode4 :
|
(tacctl0[`TAOUTMODx]==3'b100) ? ta_out0_mode4 :
|
(tacctl0[`TAOUTMODx]==3'b101) ? ta_out0_mode5 :
|
(tacctl0[`TAOUTMODx]==3'b101) ? ta_out0_mode5 :
|
(tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 :
|
(tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 :
|
ta_out0_mode7;
|
ta_out0_mode7;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) ta_out0 <= 1'b0;
|
if (puc_rst) ta_out0 <= 1'b0;
|
else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr) ta_out0 <= 1'b0;
|
else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr) ta_out0 <= 1'b0;
|
else if (tar_clk) ta_out0 <= ta_out0_nxt;
|
else if (tar_clk) ta_out0 <= ta_out0_nxt;
|
|
|
assign ta_out0_en = ~tacctl0[`TACAP];
|
assign ta_out0_en = ~tacctl0[`TACAP];
|
|
|
|
|
// Output unit 1
|
// Output unit 1
|
//-------------------
|
//-------------------
|
reg ta_out1;
|
reg ta_out1;
|
|
|
wire ta_out1_mode0 = tacctl1[`TAOUT]; // Output
|
wire ta_out1_mode0 = tacctl1[`TAOUT]; // Output
|
wire ta_out1_mode1 = equ1 ? 1'b1 : ta_out1; // Set
|
wire ta_out1_mode1 = equ1 ? 1'b1 : ta_out1; // Set
|
wire ta_out1_mode2 = equ1 ? ~ta_out1 : // Toggle/Reset
|
wire ta_out1_mode2 = equ1 ? ~ta_out1 : // Toggle/Reset
|
equ0 ? 1'b0 : ta_out1;
|
equ0 ? 1'b0 : ta_out1;
|
wire ta_out1_mode3 = equ1 ? 1'b1 : // Set/Reset
|
wire ta_out1_mode3 = equ1 ? 1'b1 : // Set/Reset
|
equ0 ? 1'b0 : ta_out1;
|
equ0 ? 1'b0 : ta_out1;
|
wire ta_out1_mode4 = equ1 ? ~ta_out1 : ta_out1; // Toggle
|
wire ta_out1_mode4 = equ1 ? ~ta_out1 : ta_out1; // Toggle
|
wire ta_out1_mode5 = equ1 ? 1'b0 : ta_out1; // Reset
|
wire ta_out1_mode5 = equ1 ? 1'b0 : ta_out1; // Reset
|
wire ta_out1_mode6 = equ1 ? ~ta_out1 : // Toggle/Set
|
wire ta_out1_mode6 = equ1 ? ~ta_out1 : // Toggle/Set
|
equ0 ? 1'b1 : ta_out1;
|
equ0 ? 1'b1 : ta_out1;
|
wire ta_out1_mode7 = equ1 ? 1'b0 : // Reset/Set
|
wire ta_out1_mode7 = equ1 ? 1'b0 : // Reset/Set
|
equ0 ? 1'b1 : ta_out1;
|
equ0 ? 1'b1 : ta_out1;
|
|
|
wire ta_out1_nxt = (tacctl1[`TAOUTMODx]==3'b000) ? ta_out1_mode0 :
|
wire ta_out1_nxt = (tacctl1[`TAOUTMODx]==3'b000) ? ta_out1_mode0 :
|
(tacctl1[`TAOUTMODx]==3'b001) ? ta_out1_mode1 :
|
(tacctl1[`TAOUTMODx]==3'b001) ? ta_out1_mode1 :
|
(tacctl1[`TAOUTMODx]==3'b010) ? ta_out1_mode2 :
|
(tacctl1[`TAOUTMODx]==3'b010) ? ta_out1_mode2 :
|
(tacctl1[`TAOUTMODx]==3'b011) ? ta_out1_mode3 :
|
(tacctl1[`TAOUTMODx]==3'b011) ? ta_out1_mode3 :
|
(tacctl1[`TAOUTMODx]==3'b100) ? ta_out1_mode4 :
|
(tacctl1[`TAOUTMODx]==3'b100) ? ta_out1_mode4 :
|
(tacctl1[`TAOUTMODx]==3'b101) ? ta_out1_mode5 :
|
(tacctl1[`TAOUTMODx]==3'b101) ? ta_out1_mode5 :
|
(tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 :
|
(tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 :
|
ta_out1_mode7;
|
ta_out1_mode7;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) ta_out1 <= 1'b0;
|
if (puc_rst) ta_out1 <= 1'b0;
|
else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr) ta_out1 <= 1'b0;
|
else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr) ta_out1 <= 1'b0;
|
else if (tar_clk) ta_out1 <= ta_out1_nxt;
|
else if (tar_clk) ta_out1 <= ta_out1_nxt;
|
|
|
assign ta_out1_en = ~tacctl1[`TACAP];
|
assign ta_out1_en = ~tacctl1[`TACAP];
|
|
|
|
|
// Output unit 2
|
// Output unit 2
|
//-------------------
|
//-------------------
|
reg ta_out2;
|
reg ta_out2;
|
|
|
wire ta_out2_mode0 = tacctl2[`TAOUT]; // Output
|
wire ta_out2_mode0 = tacctl2[`TAOUT]; // Output
|
wire ta_out2_mode1 = equ2 ? 1'b1 : ta_out2; // Set
|
wire ta_out2_mode1 = equ2 ? 1'b1 : ta_out2; // Set
|
wire ta_out2_mode2 = equ2 ? ~ta_out2 : // Toggle/Reset
|
wire ta_out2_mode2 = equ2 ? ~ta_out2 : // Toggle/Reset
|
equ0 ? 1'b0 : ta_out2;
|
equ0 ? 1'b0 : ta_out2;
|
wire ta_out2_mode3 = equ2 ? 1'b1 : // Set/Reset
|
wire ta_out2_mode3 = equ2 ? 1'b1 : // Set/Reset
|
equ0 ? 1'b0 : ta_out2;
|
equ0 ? 1'b0 : ta_out2;
|
wire ta_out2_mode4 = equ2 ? ~ta_out2 : ta_out2; // Toggle
|
wire ta_out2_mode4 = equ2 ? ~ta_out2 : ta_out2; // Toggle
|
wire ta_out2_mode5 = equ2 ? 1'b0 : ta_out2; // Reset
|
wire ta_out2_mode5 = equ2 ? 1'b0 : ta_out2; // Reset
|
wire ta_out2_mode6 = equ2 ? ~ta_out2 : // Toggle/Set
|
wire ta_out2_mode6 = equ2 ? ~ta_out2 : // Toggle/Set
|
equ0 ? 1'b1 : ta_out2;
|
equ0 ? 1'b1 : ta_out2;
|
wire ta_out2_mode7 = equ2 ? 1'b0 : // Reset/Set
|
wire ta_out2_mode7 = equ2 ? 1'b0 : // Reset/Set
|
equ0 ? 1'b1 : ta_out2;
|
equ0 ? 1'b1 : ta_out2;
|
|
|
wire ta_out2_nxt = (tacctl2[`TAOUTMODx]==3'b000) ? ta_out2_mode0 :
|
wire ta_out2_nxt = (tacctl2[`TAOUTMODx]==3'b000) ? ta_out2_mode0 :
|
(tacctl2[`TAOUTMODx]==3'b001) ? ta_out2_mode1 :
|
(tacctl2[`TAOUTMODx]==3'b001) ? ta_out2_mode1 :
|
(tacctl2[`TAOUTMODx]==3'b010) ? ta_out2_mode2 :
|
(tacctl2[`TAOUTMODx]==3'b010) ? ta_out2_mode2 :
|
(tacctl2[`TAOUTMODx]==3'b011) ? ta_out2_mode3 :
|
(tacctl2[`TAOUTMODx]==3'b011) ? ta_out2_mode3 :
|
(tacctl2[`TAOUTMODx]==3'b100) ? ta_out2_mode4 :
|
(tacctl2[`TAOUTMODx]==3'b100) ? ta_out2_mode4 :
|
(tacctl2[`TAOUTMODx]==3'b101) ? ta_out2_mode5 :
|
(tacctl2[`TAOUTMODx]==3'b101) ? ta_out2_mode5 :
|
(tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 :
|
(tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 :
|
ta_out2_mode7;
|
ta_out2_mode7;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) ta_out2 <= 1'b0;
|
if (puc_rst) ta_out2 <= 1'b0;
|
else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr) ta_out2 <= 1'b0;
|
else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr) ta_out2 <= 1'b0;
|
else if (tar_clk) ta_out2 <= ta_out2_nxt;
|
else if (tar_clk) ta_out2 <= ta_out2_nxt;
|
|
|
assign ta_out2_en = ~tacctl2[`TACAP];
|
assign ta_out2_en = ~tacctl2[`TACAP];
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 9) Timer A interrupt generation
|
// 9) Timer A interrupt generation
|
//============================================================================
|
//============================================================================
|
|
|
|
|
assign taifg_set = tar_clk & (((tactl[`TAMCx]==2'b01) & (tar==taccr0)) |
|
assign taifg_set = tar_clk & (((tactl[`TAMCx]==2'b01) & (tar==taccr0)) |
|
((tactl[`TAMCx]==2'b10) & (tar==16'hffff)) |
|
((tactl[`TAMCx]==2'b10) & (tar==16'hffff)) |
|
((tactl[`TAMCx]==2'b11) & (tar_nxt==16'h0000) & tar_dec));
|
((tactl[`TAMCx]==2'b11) & (tar_nxt==16'h0000) & tar_dec));
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assign ccifg0_set = tacctl0[`TACAP] ? cci0_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ0));
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assign ccifg0_set = tacctl0[`TACAP] ? cci0_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ0));
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assign ccifg1_set = tacctl1[`TACAP] ? cci1_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ1));
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assign ccifg1_set = tacctl1[`TACAP] ? cci1_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ1));
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assign ccifg2_set = tacctl2[`TACAP] ? cci2_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ2));
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assign ccifg2_set = tacctl2[`TACAP] ? cci2_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ2));
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wire irq_ta0 = (tacctl0[`TACCIFG] & tacctl0[`TACCIE]);
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wire irq_ta0 = (tacctl0[`TACCIFG] & tacctl0[`TACCIE]);
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wire irq_ta1 = (tactl[`TAIFG] & tactl[`TAIE]) |
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wire irq_ta1 = (tactl[`TAIFG] & tactl[`TAIE]) |
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(tacctl1[`TACCIFG] & tacctl1[`TACCIE]) |
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(tacctl1[`TACCIFG] & tacctl1[`TACCIE]) |
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(tacctl2[`TACCIFG] & tacctl2[`TACCIE]);
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(tacctl2[`TACCIFG] & tacctl2[`TACCIE]);
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endmodule // omsp_timerA
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endmodule // omsp_timerA
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`ifdef OMSP_TA_NO_INCLUDE
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`ifdef OMSP_TA_NO_INCLUDE
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`else
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`else
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`include "omsp_timerA_undefines.v"
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`include "omsp_timerA_undefines.v"
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`endif
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`endif
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