#!/usr/bin/wish
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#!/usr/bin/wish
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# Copyright (C) 2001 Authors
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# Copyright (C) 2001 Authors
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#
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#
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# This source file may be used and distributed without restriction provided
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# This source file may be used and distributed without restriction provided
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# that this copyright statement is not removed from the file and that any
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# that this copyright statement is not removed from the file and that any
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# derivative work contains the original copyright notice and the associated
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# derivative work contains the original copyright notice and the associated
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# disclaimer.
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# disclaimer.
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#
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#
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# This source file is free software; you can redistribute it and/or modify
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# This source file is free software; you can redistribute it and/or modify
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# it under the terms of the GNU Lesser General Public License as published
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# it under the terms of the GNU Lesser General Public License as published
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# by the Free Software Foundation; either version 2.1 of the License, or
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# by the Free Software Foundation; either version 2.1 of the License, or
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# (at your option) any later version.
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# (at your option) any later version.
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#
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#
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# This source is distributed in the hope that it will be useful, but WITHOUT
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# This source is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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# License for more details.
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# License for more details.
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#
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#
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# You should have received a copy of the GNU Lesser General Public License
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# You should have received a copy of the GNU Lesser General Public License
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# along with this source; if not, write to the Free Software Foundation,
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# along with this source; if not, write to the Free Software Foundation,
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# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#
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#
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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#
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#
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# File Name: commands.tcl
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# File Name: commands.tcl
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#
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#
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# Author(s):
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# Author(s):
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# - Olivier Girard, olgirard@gmail.com
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# - Olivier Girard, olgirard@gmail.com
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#
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#
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# $Rev: 198 $
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# $Rev: 217 $
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# $LastChangedBy: olivier.girard $
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# $LastChangedBy: olivier.girard $
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# $LastChangedDate: 2014-10-07 21:30:05 +0200 (Tue, 07 Oct 2014) $
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# $LastChangedDate: 2016-08-01 23:04:04 +0200 (Mon, 01 Aug 2016) $
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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global mem_breakpoint
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global mem_breakpoint
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global mem_mapping
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global mem_mapping
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global breakSelect
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global breakSelect
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###############################################################################
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###############################################################################
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# #
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# #
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# RSP COMMAND PARSER #
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# RSP COMMAND PARSER #
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# #
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# #
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###############################################################################
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###############################################################################
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proc rspParse {CpuNr sock rsp_cmd} {
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proc rspParse {CpuNr sock rsp_cmd} {
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set rsp_answer ""
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set rsp_answer ""
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set cmd_tail [string range $rsp_cmd 1 [string length $rsp_cmd]]
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set cmd_tail [string range $rsp_cmd 1 [string length $rsp_cmd]]
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switch -exact -- [string index $rsp_cmd 0] {
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switch -exact -- [string index $rsp_cmd 0] {
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"!" {set rsp_answer "OK"}
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"!" {set rsp_answer "OK"}
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"?" {set rsp_answer [rsp_stop_reply $CpuNr $sock "?"]}
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"?" {set rsp_answer [rsp_stop_reply $CpuNr $sock "?"]}
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"A" {}
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"A" {}
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"b" {}
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"b" {}
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"c" {set rsp_answer [rsp_c $CpuNr $sock $cmd_tail]}
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"c" {set rsp_answer [rsp_c $CpuNr $sock $cmd_tail]}
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"C" {set rsp_answer [rsp_c $CpuNr $sock $cmd_tail]}
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"C" {set rsp_answer [rsp_c $CpuNr $sock $cmd_tail]}
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"D" {}
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"D" {}
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"F" {}
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"F" {}
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"g" {set rsp_answer [rsp_g $CpuNr]}
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"g" {set rsp_answer [rsp_g $CpuNr]}
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"G" {set rsp_answer [rsp_G $CpuNr $cmd_tail]}
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"G" {set rsp_answer [rsp_G $CpuNr $cmd_tail]}
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"H" {set rsp_answer ""}
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"H" {set rsp_answer ""}
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"i" {}
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"i" {}
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"I" {}
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"I" {}
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"k" {set rsp_answer [rsp_k $CpuNr $cmd_tail]}
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"k" {set rsp_answer [rsp_k $CpuNr $cmd_tail]}
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"m" {set rsp_answer [rsp_m $CpuNr $cmd_tail]}
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"m" {set rsp_answer [rsp_m $CpuNr $cmd_tail]}
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"M" {set rsp_answer [rsp_M $CpuNr $cmd_tail]}
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"M" {set rsp_answer [rsp_M $CpuNr $cmd_tail]}
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"p" {}
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"p" {}
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"P" {}
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"P" {}
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"q" {set rsp_answer [rsp_q $CpuNr $sock $cmd_tail]}
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"q" {set rsp_answer [rsp_q $CpuNr $sock $cmd_tail]}
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"Q" {}
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"Q" {}
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"R" {}
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"R" {}
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"s" {set rsp_answer [rsp_s $CpuNr $sock $cmd_tail]}
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"s" {set rsp_answer [rsp_s $CpuNr $sock $cmd_tail]}
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"S" {set rsp_answer [rsp_s $CpuNr $sock $cmd_tail]}
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"S" {set rsp_answer [rsp_s $CpuNr $sock $cmd_tail]}
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"t" {}
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"t" {}
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"T" {}
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"T" {}
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"v" {}
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"v" {}
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"X" {}
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"X" {}
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"z" {set rsp_answer [rsp_z $CpuNr $sock $cmd_tail]}
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"z" {set rsp_answer [rsp_z $CpuNr $sock $cmd_tail]}
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"Z" {set rsp_answer [rsp_Z $CpuNr $sock $cmd_tail]}
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"Z" {set rsp_answer [rsp_Z $CpuNr $sock $cmd_tail]}
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default {}
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default {}
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}
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}
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return $rsp_answer
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return $rsp_answer
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}
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}
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###############################################################################
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###############################################################################
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# #
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# #
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# RSP COMMANDS #
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# RSP COMMANDS #
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# #
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# #
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###############################################################################
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###############################################################################
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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# Read CPU registers #
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# Read CPU registers #
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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proc rsp_g {CpuNr} {
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proc rsp_g {CpuNr} {
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global mspgcc_compat_mode
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# Read register value
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# Read register value
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set reg_val [ReadRegAll $CpuNr]
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set reg_val [ReadRegAll $CpuNr]
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# Format answer
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# Format answer
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set rsp_answer ""
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set rsp_answer ""
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for {set i 0} {$i < [llength $reg_val]} {incr i} {
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for {set i 0} {$i < [llength $reg_val]} {incr i} {
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regexp {0x(..)(..)} [lindex $reg_val $i] match msb lsb
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regexp {0x(..)(..)} [lindex $reg_val $i] match msb lsb
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if {$mspgcc_compat_mode} {
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append rsp_answer "$lsb$msb"
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append rsp_answer "$lsb$msb"
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} else {
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append rsp_answer "$lsb${msb}0000"
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}
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}
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}
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return $rsp_answer
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return $rsp_answer
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}
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}
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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# Write CPU registers #
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# Write CPU registers #
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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proc rsp_G {CpuNr cmd} {
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proc rsp_G {CpuNr cmd} {
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global mspgcc_compat_mode
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# Format register value
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# Format register value
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if {$mspgcc_compat_mode} {
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set num_reg [expr [string length $cmd]/4]
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set num_reg [expr [string length $cmd]/4]
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} else {
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set num_reg [expr [string length $cmd]/8]
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}
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set reg_val ""
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set reg_val ""
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for {set i 0} {$i < $num_reg} {incr i} {
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for {set i 0} {$i < $num_reg} {incr i} {
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if {$mspgcc_compat_mode} {
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set lsb "[string index $cmd [expr $i*4+0]][string index $cmd [expr $i*4+1]]"
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set lsb "[string index $cmd [expr $i*4+0]][string index $cmd [expr $i*4+1]]"
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set msb "[string index $cmd [expr $i*4+2]][string index $cmd [expr $i*4+3]]"
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set msb "[string index $cmd [expr $i*4+2]][string index $cmd [expr $i*4+3]]"
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} else {
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set lsb "[string index $cmd [expr $i*8+0]][string index $cmd [expr $i*8+1]]"
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set msb "[string index $cmd [expr $i*8+2]][string index $cmd [expr $i*8+3]]"
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}
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lappend reg_val "0x$msb$lsb"
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lappend reg_val "0x$msb$lsb"
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}
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}
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# Write registers
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# Write registers
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WriteRegAll $CpuNr $reg_val
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WriteRegAll $CpuNr $reg_val
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return "OK"
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return "OK"
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}
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}
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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# Kill request. #
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# Kill request. #
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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proc rsp_k {CpuNr cmd} {
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proc rsp_k {CpuNr cmd} {
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# Reset & Stop CPU
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# Reset & Stop CPU
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ExecutePOR_Halt $CpuNr
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ExecutePOR_Halt $CpuNr
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return "-1"
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return "-1"
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}
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}
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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# Write length bytes of memory. #
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# Write length bytes of memory. #
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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proc rsp_M {CpuNr cmd} {
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proc rsp_M {CpuNr cmd} {
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global mem_breakpoint
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global mem_breakpoint
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global mem_mapping
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global mem_mapping
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global breakSelect
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global breakSelect
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# Parse command
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# Parse command
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regexp {(.*),(.*):(.*)} $cmd match addr length data
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regexp {(.*),(.*):(.*)} $cmd match addr length data
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set addr [format %04x "0x$addr"]
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set addr [format %04x "0x$addr"]
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set length [format %d "0x$length"]
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set length [format %d "0x$length"]
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# Format data
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# Format data
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set mem_val ""
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set mem_val ""
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for {set i 0} {$i<$length} {incr i} {
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for {set i 0} {$i<$length} {incr i} {
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lappend mem_val "0x[string range $data [expr $i*2] [expr $i*2+1]]"
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lappend mem_val "0x[string range $data [expr $i*2] [expr $i*2+1]]"
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}
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}
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# Write memory
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# Write memory
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if {$length==2} {
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if {$length==2} {
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regexp {(..)(..)} $data match data_lo data_hi
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regexp {(..)(..)} $data match data_lo data_hi
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WriteMem $CpuNr 0 "0x$addr" "0x${data_hi}${data_lo}"
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WriteMem $CpuNr 0 "0x$addr" "0x${data_hi}${data_lo}"
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} else {
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} else {
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WriteMemQuick8 $CpuNr "0x$addr" $mem_val
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WriteMemQuick8 $CpuNr "0x$addr" $mem_val
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}
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}
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# Eventually re-set the software breakpoints in case they have been overwritten
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# Eventually re-set the software breakpoints in case they have been overwritten
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if {$breakSelect==0} {
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if {$breakSelect==0} {
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set addr_start [format %d "0x$addr"]
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set addr_start [format %d "0x$addr"]
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foreach {brk_addr brk_val} [array get mem_breakpoint] {
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foreach {brk_addr brk_val} [array get mem_breakpoint] {
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regsub {,} $brk_addr { } brk_addr_lst
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regsub {,} $brk_addr { } brk_addr_lst
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if {[lindex $brk_addr_lst 0]==$mem_mapping($CpuNr)} {
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if {[lindex $brk_addr_lst 0]==$mem_mapping($CpuNr)} {
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set brk_addr_dec [format %d "0x[lindex $brk_addr_lst 1]"]
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set brk_addr_dec [format %d "0x[lindex $brk_addr_lst 1]"]
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set brk_addr_offset [expr $brk_addr_dec-$addr_start]
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set brk_addr_offset [expr $brk_addr_dec-$addr_start]
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if {(0<=$brk_addr_offset) && ($brk_addr_offset<=$length)} {
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if {(0<=$brk_addr_offset) && ($brk_addr_offset<=$length)} {
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set mem_breakpoint($brk_addr) [lindex $mem_val $brk_addr_offset]
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set mem_breakpoint($brk_addr) [lindex $mem_val $brk_addr_offset]
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WriteMem $CpuNr 0 "0x[lindex $brk_addr 1]" 0x4343
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WriteMem $CpuNr 0 "0x[lindex $brk_addr 1]" 0x4343
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}
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}
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}
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}
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}
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}
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}
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}
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return "OK"
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return "OK"
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}
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}
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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# Read length bytes from memory. #
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# Read length bytes from memory. #
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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proc rsp_m {CpuNr cmd} {
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proc rsp_m {CpuNr cmd} {
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global mem_breakpoint
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global mem_breakpoint
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global mem_mapping
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global mem_mapping
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global breakSelect
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global breakSelect
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# Parse command
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# Parse command
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regexp {(.*),(.*)} $cmd match addr length
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regexp {(.*),(.*)} $cmd match addr length
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set addr [format %04x "0x$addr"]
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set addr [format %04x "0x$addr"]
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set length [format %d "0x$length"]
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set length [format %d "0x$length"]
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# Read memory
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# Read memory
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set data [ReadMemQuick8 $CpuNr "0x$addr" $length]
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set data [ReadMemQuick8 $CpuNr "0x$addr" $length]
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# Eventually replace read data by the original software breakpoint value
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# Eventually replace read data by the original software breakpoint value
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if {$breakSelect==0} {
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if {$breakSelect==0} {
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set addr_start [format %d "0x$addr"]
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set addr_start [format %d "0x$addr"]
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foreach {brk_addr brk_val} [array get mem_breakpoint] {
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foreach {brk_addr brk_val} [array get mem_breakpoint] {
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regsub {,} $brk_addr { } brk_addr_lst
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regsub {,} $brk_addr { } brk_addr_lst
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if {[lindex $brk_addr_lst 0]==$mem_mapping($CpuNr)} {
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if {[lindex $brk_addr_lst 0]==$mem_mapping($CpuNr)} {
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set brk_addr_dec [format %d "0x[lindex $brk_addr_lst 1]"]
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set brk_addr_dec [format %d "0x[lindex $brk_addr_lst 1]"]
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set brk_addr_offset [expr $brk_addr_dec-$addr_start]
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set brk_addr_offset [expr $brk_addr_dec-$addr_start]
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if {(0<=$brk_addr_offset) && ($brk_addr_offset<=$length)} {
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if {(0<=$brk_addr_offset) && ($brk_addr_offset<=$length)} {
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set data [lreplace $data $brk_addr_offset $brk_addr_offset "0x$mem_breakpoint($brk_addr)"]
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set data [lreplace $data $brk_addr_offset $brk_addr_offset "0x$mem_breakpoint($brk_addr)"]
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}
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}
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}
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}
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}
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}
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}
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}
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# Format data
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# Format data
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regsub -all {0x} $data {} data
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regsub -all {0x} $data {} data
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regsub -all { } $data {} data
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regsub -all { } $data {} data
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return $data
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return $data
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}
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}
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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# Insert breakpoint. #
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# Insert breakpoint. #
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#-----------------------------------------------------------------------------#
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#-----------------------------------------------------------------------------#
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proc rsp_Z {CpuNr sock cmd} {
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proc rsp_Z {CpuNr sock cmd} {
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global mem_breakpoint
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global mem_breakpoint
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global mem_mapping
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global mem_mapping
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global breakSelect
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global breakSelect
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# Parse command
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# Parse command
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regexp {(.),(.*),(.*)} $cmd match type addr length
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regexp {(.),(.*),(.*)} $cmd match type addr length
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set addr [format %04x "0x$addr"]
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set addr [format %04x "0x$addr"]
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switch -exact -- $type {
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switch -exact -- $type {
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"0" {# Soft Memory breakpoint
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"0" {# Soft Memory breakpoint
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if {$breakSelect==0} {
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if {$breakSelect==0} {
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if {![info exists mem_breakpoint($mem_mapping($CpuNr),$addr)]} {
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if {![info exists mem_breakpoint($mem_mapping($CpuNr),$addr)]} {
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set mem_breakpoint($mem_mapping($CpuNr),$addr) [ReadMem $CpuNr 0 "0x$addr"]
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set mem_breakpoint($mem_mapping($CpuNr),$addr) [ReadMem $CpuNr 0 "0x$addr"]
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WriteMem $CpuNr 0 "0x$addr" 0x4343
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WriteMem $CpuNr 0 "0x$addr" 0x4343
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}
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}
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return "OK"
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return "OK"
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# Hard Memory breakpoint
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# Hard Memory breakpoint
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} else {
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} else {
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if {[SetHWBreak $CpuNr 1 [format "0x%04x" 0x$addr] 1 0]} {
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if {[SetHWBreak $CpuNr 1 [format "0x%04x" 0x$addr] 1 0]} {
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#putsLog "CORE $CpuNr: --- INFO --- SET HARDWARE MEMORY BREAKPOINT. "
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#putsLog "CORE $CpuNr: --- INFO --- SET HARDWARE MEMORY BREAKPOINT. "
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return "OK"
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return "OK"
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}
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}
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putsLog "CORE $CpuNr: --- ERROR --- NO MORE HARDWARE MEMORY BREAKPOINT AVAILABLE. "
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putsLog "CORE $CpuNr: --- ERROR --- NO MORE HARDWARE MEMORY BREAKPOINT AVAILABLE. "
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return ""
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return ""
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}
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}
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}
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}
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|
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"1" {# Hardware breakpoint
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"1" {# Hardware breakpoint
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if {[SetHWBreak $CpuNr 1 [format "0x%04x" 0x$addr] 1 0]} {
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if {[SetHWBreak $CpuNr 1 [format "0x%04x" 0x$addr] 1 0]} {
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return "OK"
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return "OK"
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}
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}
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putsLog "CORE $CpuNr: --- ERROR --- NO MORE HARDWARE BREAKPOINT AVAILABLE. "
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putsLog "CORE $CpuNr: --- ERROR --- NO MORE HARDWARE BREAKPOINT AVAILABLE. "
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return ""
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return ""
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}
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}
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|
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"2" {# Write watchpoint
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"2" {# Write watchpoint
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if {[SetHWBreak $CpuNr 0 [format "0x%04x" 0x$addr] 0 1]} {
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if {[SetHWBreak $CpuNr 0 [format "0x%04x" 0x$addr] 0 1]} {
|
return "OK"
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return "OK"
|
}
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}
|
putsLog "CORE $CpuNr: --- ERROR --- NO MORE WRITE WATCHPOINT AVAILABLE. "
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putsLog "CORE $CpuNr: --- ERROR --- NO MORE WRITE WATCHPOINT AVAILABLE. "
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return ""
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return ""
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}
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}
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|
|
"3" {# Read watchpoint
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"3" {# Read watchpoint
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if {[SetHWBreak $CpuNr 0 [format "0x%04x" 0x$addr] 1 0]} {
|
if {[SetHWBreak $CpuNr 0 [format "0x%04x" 0x$addr] 1 0]} {
|
return "OK"
|
return "OK"
|
}
|
}
|
putsLog "CORE $CpuNr: --- ERROR --- NO MORE READ WATCHPOINT AVAILABLE. "
|
putsLog "CORE $CpuNr: --- ERROR --- NO MORE READ WATCHPOINT AVAILABLE. "
|
return ""
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return ""
|
}
|
}
|
|
|
"4" {# Access watchpoint
|
"4" {# Access watchpoint
|
if {[SetHWBreak $CpuNr 0 [format "0x%04x" 0x$addr] 1 1]} {
|
if {[SetHWBreak $CpuNr 0 [format "0x%04x" 0x$addr] 1 1]} {
|
return "OK"
|
return "OK"
|
}
|
}
|
putsLog "CORE $CpuNr: --- ERROR --- NO MORE ACCESS WATCHPOINT AVAILABLE. "
|
putsLog "CORE $CpuNr: --- ERROR --- NO MORE ACCESS WATCHPOINT AVAILABLE. "
|
return ""
|
return ""
|
}
|
}
|
|
|
default {return ""}
|
default {return ""}
|
}
|
}
|
}
|
}
|
|
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
# Remove breakpoint. #
|
# Remove breakpoint. #
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
proc rsp_z {CpuNr sock cmd} {
|
proc rsp_z {CpuNr sock cmd} {
|
|
|
global mem_breakpoint
|
global mem_breakpoint
|
global mem_mapping
|
global mem_mapping
|
global breakSelect
|
global breakSelect
|
|
|
# Parse command
|
# Parse command
|
regexp {(.),(.*),(.*)} $cmd match type addr length
|
regexp {(.),(.*),(.*)} $cmd match type addr length
|
set addr [format %04x "0x$addr"]
|
set addr [format %04x "0x$addr"]
|
|
|
switch -exact -- $type {
|
switch -exact -- $type {
|
"0" {# Soft Memory breakpoint
|
"0" {# Soft Memory breakpoint
|
if {$breakSelect==0} {
|
if {$breakSelect==0} {
|
if {[info exists mem_breakpoint($mem_mapping($CpuNr),$addr)]} {
|
if {[info exists mem_breakpoint($mem_mapping($CpuNr),$addr)]} {
|
WriteMem $CpuNr 0 "0x$addr" $mem_breakpoint($mem_mapping($CpuNr),$addr)
|
WriteMem $CpuNr 0 "0x$addr" $mem_breakpoint($mem_mapping($CpuNr),$addr)
|
unset mem_breakpoint($mem_mapping($CpuNr),$addr)
|
unset mem_breakpoint($mem_mapping($CpuNr),$addr)
|
}
|
}
|
return "OK"
|
return "OK"
|
|
|
# Hard Memory breakpoint
|
# Hard Memory breakpoint
|
} else {
|
} else {
|
if {[ClearHWBreak $CpuNr 1 [format "0x%04x" 0x$addr]]} {
|
if {[ClearHWBreak $CpuNr 1 [format "0x%04x" 0x$addr]]} {
|
#putsLog "CORE $CpuNr: --- INFO --- RELEASE HARDWARE MEMORY BREAKPOINT. "
|
#putsLog "CORE $CpuNr: --- INFO --- RELEASE HARDWARE MEMORY BREAKPOINT. "
|
return "OK"
|
return "OK"
|
}
|
}
|
putsLog "CORE $CpuNr: --- ERROR --- COULD NOT REMOVE HARDWARE MEMORY BREAKPOINT. "
|
putsLog "CORE $CpuNr: --- ERROR --- COULD NOT REMOVE HARDWARE MEMORY BREAKPOINT. "
|
return ""
|
return ""
|
}
|
}
|
}
|
}
|
|
|
"1" {# Hardware breakpoint
|
"1" {# Hardware breakpoint
|
if {[ClearHWBreak $CpuNr 1 [format "0x%04x" 0x$addr]]} {
|
if {[ClearHWBreak $CpuNr 1 [format "0x%04x" 0x$addr]]} {
|
return "OK"
|
return "OK"
|
}
|
}
|
return ""
|
return ""
|
}
|
}
|
|
|
"2" {# Write watchpoint
|
"2" {# Write watchpoint
|
if {[ClearHWBreak $CpuNr 0 [format "0x%04x" 0x$addr]]} {
|
if {[ClearHWBreak $CpuNr 0 [format "0x%04x" 0x$addr]]} {
|
return "OK"
|
return "OK"
|
}
|
}
|
return ""
|
return ""
|
}
|
}
|
|
|
"3" {# Read watchpoint
|
"3" {# Read watchpoint
|
if {[ClearHWBreak $CpuNr 0 [format "0x%04x" 0x$addr]]} {
|
if {[ClearHWBreak $CpuNr 0 [format "0x%04x" 0x$addr]]} {
|
return "OK"
|
return "OK"
|
}
|
}
|
return ""
|
return ""
|
}
|
}
|
|
|
"4" {# Access watchpoint
|
"4" {# Access watchpoint
|
if {[ClearHWBreak $CpuNr 0 [format "0x%04x" 0x$addr]]} {
|
if {[ClearHWBreak $CpuNr 0 [format "0x%04x" 0x$addr]]} {
|
return "OK"
|
return "OK"
|
}
|
}
|
return ""
|
return ""
|
}
|
}
|
|
|
default {return ""}
|
default {return ""}
|
}
|
}
|
}
|
}
|
|
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
# Continue. #
|
# Continue. #
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
proc rsp_c {CpuNr sock cmd} {
|
proc rsp_c {CpuNr sock cmd} {
|
|
|
# Set address if required
|
# Set address if required
|
if {$cmd!=""} {
|
if {$cmd!=""} {
|
set cmd [format %04x "0x$cmd"]
|
set cmd [format %04x "0x$cmd"]
|
SetPC $CpuNr "0x$cmd"
|
SetPC $CpuNr "0x$cmd"
|
}
|
}
|
|
|
# Clear status
|
# Clear status
|
ClrStatus $CpuNr
|
ClrStatus $CpuNr
|
|
|
# Continue
|
# Continue
|
ReleaseCPU $CpuNr
|
ReleaseCPU $CpuNr
|
|
|
|
|
return [rsp_stop_reply $CpuNr $sock "c"]
|
return [rsp_stop_reply $CpuNr $sock "c"]
|
}
|
}
|
|
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
# Step. #
|
# Step. #
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
proc rsp_s {CpuNr sock cmd} {
|
proc rsp_s {CpuNr sock cmd} {
|
|
|
# Set address if required
|
# Set address if required
|
if {$cmd!=""} {
|
if {$cmd!=""} {
|
set cmd [format %04x "0x$cmd"]
|
set cmd [format %04x "0x$cmd"]
|
SetPC $CpuNr "0x$cmd"
|
SetPC $CpuNr "0x$cmd"
|
}
|
}
|
|
|
# Clear status
|
# Clear status
|
ClrStatus $CpuNr
|
ClrStatus $CpuNr
|
|
|
# Read current PC value
|
# Read current PC value
|
set pc [ReadReg $CpuNr 0]
|
set pc [ReadReg $CpuNr 0]
|
|
|
# Incremental step
|
# Incremental step
|
StepCPU $CpuNr
|
StepCPU $CpuNr
|
|
|
return [rsp_stop_reply $CpuNr $sock "s" $pc]
|
return [rsp_stop_reply $CpuNr $sock "s" $pc]
|
}
|
}
|
|
|
|
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
# The `C', `c', `S', `s', `vCont', `vAttach', `vRun', `vStopped', and `?' #
|
# The `C', `c', `S', `s', `vCont', `vAttach', `vRun', `vStopped', and `?' #
|
# packets can receive any of the below as a reply. Except for `?' and #
|
# packets can receive any of the below as a reply. Except for `?' and #
|
# `vStopped', that reply is only returned when the target halts. #
|
# `vStopped', that reply is only returned when the target halts. #
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
proc rsp_stop_reply {CpuNr sock cmd {opt_val "0"}} {
|
proc rsp_stop_reply {CpuNr sock cmd {opt_val "0"}} {
|
|
|
global mspgcc_compat_mode
|
global mspgcc_compat_mode
|
|
|
# Wait until halted
|
# Wait until halted
|
while {![IsHalted $CpuNr]} {
|
while {![IsHalted $CpuNr]} {
|
|
|
# Wait a few milliseconds to prevent the gui from freezing
|
# Wait a few milliseconds to prevent the gui from freezing
|
after 100 {set end 1}
|
after 100 {set end 1}
|
vwait end
|
vwait end
|
|
|
# Check if we are interrupted by GDB
|
# Check if we are interrupted by GDB
|
fconfigure $sock -blocking 0
|
fconfigure $sock -blocking 0
|
set break_char [read -nonewline $sock]
|
set break_char [read -nonewline $sock]
|
fconfigure $sock -blocking 1
|
fconfigure $sock -blocking 1
|
binary scan $break_char H* break_char
|
binary scan $break_char H* break_char
|
if {$break_char=="03"} {
|
if {$break_char=="03"} {
|
putsVerbose "--> BREAK"
|
putsVerbose "--> BREAK"
|
HaltCPU $CpuNr
|
HaltCPU $CpuNr
|
}
|
}
|
}
|
}
|
|
|
# Read some important registers
|
# Read some important registers
|
set pc [ReadReg $CpuNr 0]
|
set pc [ReadReg $CpuNr 0]
|
regexp {0x(..)(..)} $pc match pc_hi pc_lo
|
regexp {0x(..)(..)} $pc match pc_hi pc_lo
|
set r4 [ReadReg $CpuNr 4]
|
set r4 [ReadReg $CpuNr 4]
|
regexp {0x(..)(..)} $r4 match r4_hi r4_lo
|
regexp {0x(..)(..)} $r4 match r4_hi r4_lo
|
|
|
# In case of a single step command, make sure that the PC
|
# In case of a single step command, make sure that the PC
|
# value changes. If not, return an error otherwise GDB will
|
# value changes. If not, return an error otherwise GDB will
|
# end-up in an infinite loop.
|
# end-up in an infinite loop.
|
if {$cmd == "s"} {
|
if {$cmd == "s"} {
|
if {$opt_val == $pc} {
|
if {$opt_val == $pc} {
|
return "E05"
|
return "E05"
|
}
|
}
|
}
|
}
|
|
|
if {$mspgcc_compat_mode} {
|
if {$mspgcc_compat_mode} {
|
return "T0500:$pc_lo$pc_hi;04:$r4_lo$r4_hi;" ;# 16bit word Response for older MSPGCC versions
|
return "T0500:$pc_lo$pc_hi;04:$r4_lo$r4_hi;" ;# 16bit word Response for older MSPGCC versions
|
} else {
|
} else {
|
return "T0500:$pc_lo${pc_hi}0000;04:$r4_lo${r4_hi}0000;" ;# 32bit word Response starting with TI/RedHat GCC port
|
return "T0500:$pc_lo${pc_hi}0000;04:$r4_lo${r4_hi}0000;" ;# 32bit word Response starting with TI/RedHat GCC port
|
}
|
}
|
}
|
}
|
|
|
|
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
# #
|
# #
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
proc rsp_q {CpuNr sock cmd} {
|
proc rsp_q {CpuNr sock cmd} {
|
|
|
switch -regexp -- $cmd {
|
switch -regexp -- $cmd {
|
|
|
"C" {set rsp_answer ""}
|
"C" {set rsp_answer ""}
|
"Offsets" {set rsp_answer "Text=0;Data=0;Bss=0"}
|
"Offsets" {set rsp_answer "Text=0;Data=0;Bss=0"}
|
"Rcmd,.+" {set rsp_answer [rsp_qRcmd $CpuNr $sock $cmd]}
|
"Rcmd,.+" {set rsp_answer [rsp_qRcmd $CpuNr $sock $cmd]}
|
default {set rsp_answer ""}
|
default {set rsp_answer ""}
|
}
|
}
|
return $rsp_answer
|
return $rsp_answer
|
}
|
}
|
|
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
# qRcmd,command' #
|
# qRcmd,command' #
|
# command (hex encoded) is passed to the local interpreter for execution. #
|
# command (hex encoded) is passed to the local interpreter for execution. #
|
# Invalid commands should be reported using the output string. Before the #
|
# Invalid commands should be reported using the output string. Before the #
|
# final result packet, the target may also respond with a number of #
|
# final result packet, the target may also respond with a number of #
|
# intermediate `Ooutput' console output packets. Implementors should note #
|
# intermediate `Ooutput' console output packets. Implementors should note #
|
# that providing access to a stubs's interpreter may have security #
|
# that providing access to a stubs's interpreter may have security #
|
# implications. #
|
# implications. #
|
#-----------------------------------------------------------------------------#
|
#-----------------------------------------------------------------------------#
|
proc rsp_qRcmd {CpuNr sock cmd} {
|
proc rsp_qRcmd {CpuNr sock cmd} {
|
|
|
regsub {^Rcmd,} $cmd {} cmd
|
regsub {^Rcmd,} $cmd {} cmd
|
set cmd [binary format H* $cmd]; # Convert hex to ascii
|
set cmd [binary format H* $cmd]; # Convert hex to ascii
|
|
|
switch -exact -- $cmd {
|
switch -exact -- $cmd {
|
"erase all" {;# Convert ascii to hex
|
"erase all" {;# Convert ascii to hex
|
binary scan "Erasing target program memory..." H* text1
|
binary scan "Erasing target program memory..." H* text1
|
binary scan " Erased OK\n" H* text2
|
binary scan " Erased OK\n" H* text2
|
;# Execute erase command
|
;# Execute erase command
|
sendRSPpacket $sock "O$text1"
|
sendRSPpacket $sock "O$text1"
|
EraseROM $CpuNr
|
EraseROM $CpuNr
|
sendRSPpacket $sock "O$text2"
|
sendRSPpacket $sock "O$text2"
|
set rsp_answer "OK"
|
set rsp_answer "OK"
|
}
|
}
|
default {set rsp_answer "OK"}
|
default {set rsp_answer "OK"}
|
}
|
}
|
|
|
return $rsp_answer
|
return $rsp_answer
|
|
|
}
|
}
|
|
|
