//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// or1200_fpu_div ////
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//// or1200_fpu_div ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// division entity for the division unit ////
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//// division entity for the division unit ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Original design (FPU100) - ////
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//// - Original design (FPU100) - ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// Julius Baxter, julius@opencores.org ////
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//// Julius Baxter, julius@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2006, 2010
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// Copyright (C) 2006, 2010
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// POSSIBILITY OF SUCH DAMAGE.
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//
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//
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module or1200_fpu_div
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module or1200_fpu_div
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(
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(
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clk_i,
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clk_i,
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dvdnd_i,
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dvdnd_i,
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dvsor_i,
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dvsor_i,
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sign_dvd_i,
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sign_dvd_i,
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sign_div_i,
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sign_div_i,
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start_i,
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start_i,
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ready_o,
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ready_o,
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qutnt_o,
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qutnt_o,
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rmndr_o,
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rmndr_o,
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sign_o,
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sign_o,
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div_zero_o
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div_zero_o
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);
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);
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parameter FP_WIDTH = 32;
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parameter FP_WIDTH = 32;
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parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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parameter FRAC_WIDTH = 23;
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parameter FRAC_WIDTH = 23;
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parameter EXP_WIDTH = 8;
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parameter EXP_WIDTH = 8;
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parameter ZERO_VECTOR = 31'd0;
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parameter ZERO_VECTOR = 31'd0;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter QNAN = 31'b1111111110000000000000000000000;
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parameter QNAN = 31'b1111111110000000000000000000000;
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parameter SNAN = 31'b1111111100000000000000000000001;
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parameter SNAN = 31'b1111111100000000000000000000001;
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input clk_i;
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input clk_i;
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input [2*(FRAC_WIDTH+2)-1:0] dvdnd_i;
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input [2*(FRAC_WIDTH+2)-1:0] dvdnd_i;
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input [FRAC_WIDTH+3:0] dvsor_i;
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input [FRAC_WIDTH+3:0] dvsor_i;
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input sign_dvd_i;
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input sign_dvd_i;
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input sign_div_i;
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input sign_div_i;
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input start_i;
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input start_i;
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output ready_o;
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output ready_o;
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output [FRAC_WIDTH+3:0] qutnt_o;
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output [FRAC_WIDTH+3:0] qutnt_o;
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output [FRAC_WIDTH+3:0] rmndr_o;
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output [FRAC_WIDTH+3:0] rmndr_o;
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output sign_o;
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output sign_o;
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output div_zero_o;
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output div_zero_o;
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parameter t_state_waiting = 1'b0,
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parameter t_state_waiting = 1'b0,
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t_state_busy = 1'b1;
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t_state_busy = 1'b1;
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reg [FRAC_WIDTH+3:0] s_qutnt_o;
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reg [FRAC_WIDTH+3:0] s_qutnt_o;
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reg [FRAC_WIDTH+3:0] s_rmndr_o;
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reg [FRAC_WIDTH+3:0] s_rmndr_o;
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reg [2*(FRAC_WIDTH+2)-1:0] s_dvdnd_i;
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reg [2*(FRAC_WIDTH+2)-1:0] s_dvdnd_i;
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reg [FRAC_WIDTH+3:0] s_dvsor_i;
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reg [FRAC_WIDTH+3:0] s_dvsor_i;
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reg s_sign_dvd_i, s_sign_div_i;
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reg s_sign_dvd_i, s_sign_div_i;
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wire s_sign_o;
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wire s_sign_o;
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wire s_div_zero_o;
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wire s_div_zero_o;
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reg s_start_i;
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reg s_start_i;
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reg s_ready_o;
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reg s_ready_o;
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reg s_state;
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reg s_state;
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reg [4:0] s_count;
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reg [4:0] s_count;
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reg [FRAC_WIDTH+3:0] s_dvd;
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reg [FRAC_WIDTH+3:0] s_dvd;
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// Input Register
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// Input Register
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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s_dvdnd_i <= dvdnd_i;
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s_dvdnd_i <= dvdnd_i;
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s_dvsor_i <= dvsor_i;
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s_dvsor_i <= dvsor_i;
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s_sign_dvd_i<= sign_dvd_i;
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s_sign_dvd_i<= sign_dvd_i;
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s_sign_div_i<= sign_div_i;
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s_sign_div_i<= sign_div_i;
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s_start_i <= start_i;
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s_start_i <= start_i;
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end
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end
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assign qutnt_o = s_qutnt_o;
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assign qutnt_o = s_qutnt_o;
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assign rmndr_o = s_rmndr_o;
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assign rmndr_o = s_rmndr_o;
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assign sign_o = s_sign_o;
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assign sign_o = s_sign_o;
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assign ready_o = s_ready_o;
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assign ready_o = s_ready_o;
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assign div_zero_o = s_div_zero_o;
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assign div_zero_o = s_div_zero_o;
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assign s_sign_o = sign_dvd_i ^ sign_div_i;
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assign s_sign_o = sign_dvd_i ^ sign_div_i;
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assign s_div_zero_o = !(|s_dvsor_i) & (|s_dvdnd_i);
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assign s_div_zero_o = !(|s_dvsor_i) & (|s_dvdnd_i);
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (s_start_i)
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if (s_start_i)
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begin
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begin
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s_state <= t_state_busy;
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s_state <= t_state_busy;
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s_count <= 26;
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s_count <= 26;
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end
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end
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else if (!(|s_count) & s_state==t_state_busy)
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else if (!(|s_count) & s_state==t_state_busy)
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begin
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begin
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s_state <= t_state_waiting;
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s_state <= t_state_waiting;
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s_ready_o <= 1;
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s_ready_o <= 1;
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s_count <=26;
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s_count <=26;
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end
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end
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else if (s_state==t_state_busy)
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else if (s_state==t_state_busy)
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s_count <= s_count - 1;
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s_count <= s_count - 1;
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else
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else
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begin
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begin
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s_state <= t_state_waiting;
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s_state <= t_state_waiting;
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s_ready_o <= 0;
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s_ready_o <= 0;
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end
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end
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wire [26:0] v_div;
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wire [26:0] v_div;
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assign v_div = (s_count==26) ? {3'd0,s_dvdnd_i[49:26]} : s_dvd;
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assign v_div = (s_count==26) ? {3'd0,s_dvdnd_i[49:26]} : s_dvd;
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wire [26:0] v_div_minus_s_dvsor_i;
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wire [26:0] v_div_minus_s_dvsor_i;
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assign v_div_minus_s_dvsor_i = v_div - s_dvsor_i;
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assign v_div_minus_s_dvsor_i = v_div - s_dvsor_i;
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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//Reset
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//Reset
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if (s_start_i)
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if (s_start_i)
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begin
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begin
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s_qutnt_o <= 0;
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s_qutnt_o <= 0;
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s_rmndr_o <= 0;
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s_rmndr_o <= 0;
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end
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end
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else if (s_state==t_state_busy)
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else if (s_state==t_state_busy)
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begin
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begin
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if (v_div < s_dvsor_i)
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if (v_div < s_dvsor_i)
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begin
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begin
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s_qutnt_o[s_count] <= 1'b0;
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s_qutnt_o[s_count] <= 1'b0;
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s_dvd <= {v_div[25:0],1'b0};
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s_dvd <= {v_div[25:0],1'b0};
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end
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end
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else
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else
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begin
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begin
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s_qutnt_o[s_count] <= 1'b1;
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s_qutnt_o[s_count] <= 1'b1;
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s_dvd <= {v_div_minus_s_dvsor_i[25:0],1'b0};
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s_dvd <= {v_div_minus_s_dvsor_i[25:0],1'b0};
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end
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end
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s_rmndr_o <= v_div;
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s_rmndr_o <= v_div;
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end // if (s_state==t_state_busy)
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end // if (s_state==t_state_busy)
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end // always @ (posedge clk_i)
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end // always @ (posedge clk_i)
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endmodule // or1200_fpu_div
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endmodule // or1200_fpu_div
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