//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Data Cache top level ////
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//// OR1200's Data Cache top level ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of all IC blocks. ////
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//// Instantiation of all IC blocks. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
|
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// $Log: or1200_ic_top.v,v $
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// $Log: or1200_ic_top.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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// No update
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//
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// Revision 1.9 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.7.4.2 2003/12/09 11:46:48 simons
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|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
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|
// Added embedded memory QMEM.
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//
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// Revision 1.7 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.6 2002/03/29 15:16:55 lampret
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|
// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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|
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:53 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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//
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//
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// Data cache
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// Data cache
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//
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//
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module or1200_ic_top(
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module or1200_ic_top(
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// Rst, clk and clock control
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// Rst, clk and clock control
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clk, rst,
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clk, rst,
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|
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// External i/f
|
// External i/f
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icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
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icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
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icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
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icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
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|
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// Internal i/f
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// Internal i/f
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ic_en,
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ic_en,
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icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
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icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
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icqmem_sel_i, icqmem_tag_i,
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icqmem_sel_i, icqmem_tag_i,
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icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
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icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
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|
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
|
mbist_si_i, mbist_so_o, mbist_ctrl_i,
|
`endif
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`endif
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// SPRs
|
// SPRs
|
spr_cs, spr_write, spr_dat_i
|
spr_cs, spr_write, spr_dat_i
|
);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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|
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//
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//
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// I/O
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// I/O
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//
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//
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|
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//
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//
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// Clock and reset
|
// Clock and reset
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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|
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//
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//
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// External I/F
|
// External I/F
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//
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//
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output [dw-1:0] icbiu_dat_o;
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output [dw-1:0] icbiu_dat_o;
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output [31:0] icbiu_adr_o;
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output [31:0] icbiu_adr_o;
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output icbiu_cyc_o;
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output icbiu_cyc_o;
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output icbiu_stb_o;
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output icbiu_stb_o;
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output icbiu_we_o;
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output icbiu_we_o;
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output [3:0] icbiu_sel_o;
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output [3:0] icbiu_sel_o;
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output icbiu_cab_o;
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output icbiu_cab_o;
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input [dw-1:0] icbiu_dat_i;
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input [dw-1:0] icbiu_dat_i;
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input icbiu_ack_i;
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input icbiu_ack_i;
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input icbiu_err_i;
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input icbiu_err_i;
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|
|
//
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//
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// Internal I/F
|
// Internal I/F
|
//
|
//
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input ic_en;
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input ic_en;
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input [31:0] icqmem_adr_i;
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input [31:0] icqmem_adr_i;
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input icqmem_cycstb_i;
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input icqmem_cycstb_i;
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input icqmem_ci_i;
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input icqmem_ci_i;
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input [3:0] icqmem_sel_i;
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input [3:0] icqmem_sel_i;
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input [3:0] icqmem_tag_i;
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input [3:0] icqmem_tag_i;
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output [dw-1:0] icqmem_dat_o;
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output [dw-1:0] icqmem_dat_o;
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output icqmem_ack_o;
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output icqmem_ack_o;
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output icqmem_rty_o;
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output icqmem_rty_o;
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output icqmem_err_o;
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output icqmem_err_o;
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output [3:0] icqmem_tag_o;
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output [3:0] icqmem_tag_o;
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|
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`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
//
|
//
|
// RAM BIST
|
// RAM BIST
|
//
|
//
|
input mbist_si_i;
|
input mbist_si_i;
|
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
|
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
|
output mbist_so_o;
|
`endif
|
`endif
|
|
|
//
|
//
|
// SPR access
|
// SPR access
|
//
|
//
|
input spr_cs;
|
input spr_cs;
|
input spr_write;
|
input spr_write;
|
input [31:0] spr_dat_i;
|
input [31:0] spr_dat_i;
|
|
|
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
wire tag_v;
|
wire tag_v;
|
wire [`OR1200_ICTAG_W-2:0] tag;
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wire [`OR1200_ICTAG_W-2:0] tag;
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wire [dw-1:0] to_icram;
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wire [dw-1:0] to_icram;
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wire [dw-1:0] from_icram;
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wire [dw-1:0] from_icram;
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wire [31:0] saved_addr;
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wire [31:0] saved_addr;
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wire [3:0] icram_we;
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wire [3:0] icram_we;
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wire ictag_we;
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wire ictag_we;
|
wire [31:0] ic_addr;
|
wire [31:0] ic_addr;
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wire icfsm_biu_read;
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wire icfsm_biu_read;
|
reg tagcomp_miss;
|
reg tagcomp_miss;
|
wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr;
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wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr;
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wire ictag_en;
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wire ictag_en;
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wire ictag_v;
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wire ictag_v;
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wire ic_inv;
|
wire ic_inv;
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wire icfsm_first_hit_ack;
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wire icfsm_first_hit_ack;
|
wire icfsm_first_miss_ack;
|
wire icfsm_first_miss_ack;
|
wire icfsm_first_miss_err;
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wire icfsm_first_miss_err;
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wire icfsm_burst;
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wire icfsm_burst;
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wire icfsm_tag_we;
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wire icfsm_tag_we;
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`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
//
|
//
|
// RAM BIST
|
// RAM BIST
|
//
|
//
|
wire mbist_ram_so;
|
wire mbist_ram_so;
|
wire mbist_tag_so;
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wire mbist_tag_so;
|
wire mbist_ram_si = mbist_si_i;
|
wire mbist_ram_si = mbist_si_i;
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wire mbist_tag_si = mbist_ram_so;
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wire mbist_tag_si = mbist_ram_so;
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assign mbist_so_o = mbist_tag_so;
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assign mbist_so_o = mbist_tag_so;
|
`endif
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`endif
|
|
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//
|
//
|
// Simple assignments
|
// Simple assignments
|
//
|
//
|
assign icbiu_adr_o = ic_addr;
|
assign icbiu_adr_o = ic_addr;
|
assign ic_inv = spr_cs & spr_write;
|
assign ic_inv = spr_cs & spr_write;
|
assign ictag_we = icfsm_tag_we | ic_inv;
|
assign ictag_we = icfsm_tag_we | ic_inv;
|
assign ictag_addr = ic_inv ? spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] : ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
|
assign ictag_addr = ic_inv ?
|
|
spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] :
|
|
ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
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assign ictag_en = ic_inv | ic_en;
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assign ictag_en = ic_inv | ic_en;
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assign ictag_v = ~ic_inv;
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assign ictag_v = ~ic_inv;
|
|
|
//
|
//
|
// Data to BIU is from ICRAM when IC is enabled or from LSU when
|
// Data to BIU is from ICRAM when IC is enabled or from LSU when
|
// IC is disabled
|
// IC is disabled
|
//
|
//
|
assign icbiu_dat_o = 32'h00000000;
|
assign icbiu_dat_o = 32'h00000000;
|
|
|
//
|
//
|
// Bypases of the IC when IC is disabled
|
// Bypases of the IC when IC is disabled
|
//
|
//
|
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
|
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
|
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
|
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
|
assign icbiu_we_o = 1'b0;
|
assign icbiu_we_o = 1'b0;
|
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
|
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
|
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
|
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
|
assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
|
assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
|
assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
|
assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
|
|
|
//
|
//
|
// CPU normal and error termination
|
// CPU normal and error termination
|
//
|
//
|
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
|
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
|
assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
|
assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
|
|
|
//
|
//
|
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
|
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
|
//
|
//
|
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
|
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
|
|
|
//
|
//
|
// Select between input data generated by LSU or by BIU
|
// Select between input data generated by LSU or by BIU
|
//
|
//
|
assign to_icram = icbiu_dat_i;
|
assign to_icram = icbiu_dat_i;
|
|
|
//
|
//
|
// Select between data generated by ICRAM or passed by BIU
|
// Select between data generated by ICRAM or passed by BIU
|
//
|
//
|
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
|
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
|
|
|
//
|
//
|
// Tag comparison
|
// Tag comparison
|
//
|
//
|
always @(tag or saved_addr or tag_v) begin
|
always @(tag or saved_addr or tag_v) begin
|
if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
|
if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
|
tagcomp_miss = 1'b1;
|
tagcomp_miss = 1'b1;
|
else
|
else
|
tagcomp_miss = 1'b0;
|
tagcomp_miss = 1'b0;
|
end
|
end
|
|
|
//
|
//
|
// Instantiation of IC Finite State Machine
|
// Instantiation of IC Finite State Machine
|
//
|
//
|
or1200_ic_fsm or1200_ic_fsm(
|
or1200_ic_fsm or1200_ic_fsm(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
.ic_en(ic_en),
|
.ic_en(ic_en),
|
.icqmem_cycstb_i(icqmem_cycstb_i),
|
.icqmem_cycstb_i(icqmem_cycstb_i),
|
.icqmem_ci_i(icqmem_ci_i),
|
.icqmem_ci_i(icqmem_ci_i),
|
.tagcomp_miss(tagcomp_miss),
|
.tagcomp_miss(tagcomp_miss),
|
.biudata_valid(icbiu_ack_i),
|
.biudata_valid(icbiu_ack_i),
|
.biudata_error(icbiu_err_i),
|
.biudata_error(icbiu_err_i),
|
.start_addr(icqmem_adr_i),
|
.start_addr(icqmem_adr_i),
|
.saved_addr(saved_addr),
|
.saved_addr(saved_addr),
|
.icram_we(icram_we),
|
.icram_we(icram_we),
|
.biu_read(icfsm_biu_read),
|
.biu_read(icfsm_biu_read),
|
.first_hit_ack(icfsm_first_hit_ack),
|
.first_hit_ack(icfsm_first_hit_ack),
|
.first_miss_ack(icfsm_first_miss_ack),
|
.first_miss_ack(icfsm_first_miss_ack),
|
.first_miss_err(icfsm_first_miss_err),
|
.first_miss_err(icfsm_first_miss_err),
|
.burst(icfsm_burst),
|
.burst(icfsm_burst),
|
.tag_we(icfsm_tag_we)
|
.tag_we(icfsm_tag_we)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of IC main memory
|
// Instantiation of IC main memory
|
//
|
//
|
or1200_ic_ram or1200_ic_ram(
|
or1200_ic_ram or1200_ic_ram(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.mbist_si_i(mbist_ram_si),
|
.mbist_si_i(mbist_ram_si),
|
.mbist_so_o(mbist_ram_so),
|
.mbist_so_o(mbist_ram_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
.addr(ic_addr[`OR1200_ICINDXH:2]),
|
.addr(ic_addr[`OR1200_ICINDXH:2]),
|
.en(ic_en),
|
.en(ic_en),
|
.we(icram_we),
|
.we(icram_we),
|
.datain(to_icram),
|
.datain(to_icram),
|
.dataout(from_icram)
|
.dataout(from_icram)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of IC TAG memory
|
// Instantiation of IC TAG memory
|
//
|
//
|
or1200_ic_tag or1200_ic_tag(
|
or1200_ic_tag or1200_ic_tag(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.mbist_si_i(mbist_tag_si),
|
.mbist_si_i(mbist_tag_si),
|
.mbist_so_o(mbist_tag_so),
|
.mbist_so_o(mbist_tag_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
.addr(ictag_addr),
|
.addr(ictag_addr),
|
.en(ictag_en),
|
.en(ictag_en),
|
.we(ictag_we),
|
.we(ictag_we),
|
.datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
|
.datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
|
.tag_v(tag_v),
|
.tag_v(tag_v),
|
.tag(tag)
|
.tag(tag)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|