/* armrdi.c -- ARMulator RDI interface: ARM6 Instruction Emulator.
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/* armrdi.c -- ARMulator RDI interface: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#include <string.h>
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#include <string.h>
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#include <ctype.h>
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#include <ctype.h>
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#include "armdefs.h"
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#include "armdefs.h"
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#include "armemu.h"
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#include "armemu.h"
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#include "armos.h"
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#include "armos.h"
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#include "dbg_cp.h"
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#include "dbg_cp.h"
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#include "dbg_conf.h"
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#include "dbg_conf.h"
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#include "dbg_rdi.h"
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#include "dbg_rdi.h"
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#include "dbg_hif.h"
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#include "dbg_hif.h"
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#include "communicate.h"
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#include "communicate.h"
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/***************************************************************************\
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/***************************************************************************\
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* Declarations *
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* Declarations *
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\***************************************************************************/
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\***************************************************************************/
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#define Watch_AnyRead (RDIWatch_ByteRead+RDIWatch_HalfRead+RDIWatch_WordRead)
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#define Watch_AnyRead (RDIWatch_ByteRead+RDIWatch_HalfRead+RDIWatch_WordRead)
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#define Watch_AnyWrite (RDIWatch_ByteWrite+RDIWatch_HalfWrite+RDIWatch_WordWrite)
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#define Watch_AnyWrite (RDIWatch_ByteWrite+RDIWatch_HalfWrite+RDIWatch_WordWrite)
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static unsigned FPRegsAddr; /* last known address of FPE regs */
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static unsigned FPRegsAddr; /* last known address of FPE regs */
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#define FPESTART 0x2000L
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#define FPESTART 0x2000L
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#define FPEEND 0x8000L
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#define FPEEND 0x8000L
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#define IGNORE(d) (d = d)
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#define IGNORE(d) (d = d)
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#ifdef RDI_VERBOSE
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#ifdef RDI_VERBOSE
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#define TracePrint(s) \
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#define TracePrint(s) \
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if (rdi_log & 1) ARMul_DebugPrint s
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if (rdi_log & 1) ARMul_DebugPrint s
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#else
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#else
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#define TracePrint(s)
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#define TracePrint(s)
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#endif
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#endif
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static ARMul_State *state = NULL;
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static ARMul_State *state = NULL;
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static unsigned BreaksSet; /* The number of breakpoints set */
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static unsigned BreaksSet; /* The number of breakpoints set */
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static int rdi_log = 0; /* debugging ? */
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static int rdi_log = 0; /* debugging ? */
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#define LOWEST_RDI_LEVEL 0
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#define LOWEST_RDI_LEVEL 0
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#define HIGHEST_RDI_LEVEL 1
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#define HIGHEST_RDI_LEVEL 1
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static int MYrdi_level = LOWEST_RDI_LEVEL;
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static int MYrdi_level = LOWEST_RDI_LEVEL;
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typedef struct BreakNode BreakNode;
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typedef struct BreakNode BreakNode;
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typedef struct WatchNode WatchNode;
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typedef struct WatchNode WatchNode;
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struct BreakNode
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struct BreakNode
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{ /* A breakpoint list node */
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{ /* A breakpoint list node */
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BreakNode *next;
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BreakNode *next;
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ARMword address; /* The address of this breakpoint */
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ARMword address; /* The address of this breakpoint */
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unsigned type; /* The type of comparison */
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unsigned type; /* The type of comparison */
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ARMword bound; /* The other address for a range */
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ARMword bound; /* The other address for a range */
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ARMword inst;
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ARMword inst;
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};
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};
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struct WatchNode
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struct WatchNode
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{ /* A watchpoint list node */
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{ /* A watchpoint list node */
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WatchNode *next;
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WatchNode *next;
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ARMword address; /* The address of this watchpoint */
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ARMword address; /* The address of this watchpoint */
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unsigned type; /* The type of comparison */
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unsigned type; /* The type of comparison */
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unsigned datatype; /* The type of access to watch for */
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unsigned datatype; /* The type of access to watch for */
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ARMword bound; /* The other address for a range */
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ARMword bound; /* The other address for a range */
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};
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};
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BreakNode *BreakList = NULL;
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BreakNode *BreakList = NULL;
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WatchNode *WatchList = NULL;
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WatchNode *WatchList = NULL;
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void
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void
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ARMul_DebugPrint_i (const Dbg_HostosInterface * hostif, const char *format,
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ARMul_DebugPrint_i (const Dbg_HostosInterface * hostif, const char *format,
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...)
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...)
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{
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{
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va_list ap;
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va_list ap;
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va_start (ap, format);
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va_start (ap, format);
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hostif->dbgprint (hostif->dbgarg, format, ap);
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hostif->dbgprint (hostif->dbgarg, format, ap);
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va_end (ap);
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va_end (ap);
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}
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}
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void
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void
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ARMul_DebugPrint (ARMul_State * state, const char *format, ...)
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ARMul_DebugPrint (ARMul_State * state, const char *format, ...)
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{
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{
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va_list ap;
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va_list ap;
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va_start (ap, format);
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va_start (ap, format);
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if (!(rdi_log & 8))
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if (!(rdi_log & 8))
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state->hostif->dbgprint (state->hostif->dbgarg, format, ap);
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state->hostif->dbgprint (state->hostif->dbgarg, format, ap);
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va_end (ap);
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va_end (ap);
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}
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}
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#define CONSOLE_PRINT_MAX_LEN 128
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#define CONSOLE_PRINT_MAX_LEN 128
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void
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void
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ARMul_ConsolePrint (ARMul_State * state, const char *format, ...)
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ARMul_ConsolePrint (ARMul_State * state, const char *format, ...)
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{
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{
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va_list ap;
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va_list ap;
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int ch;
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int ch;
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char *str, buf[CONSOLE_PRINT_MAX_LEN];
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char *str, buf[CONSOLE_PRINT_MAX_LEN];
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int i, j;
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int i, j;
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ARMword junk;
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ARMword junk;
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va_start (ap, format);
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va_start (ap, format);
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vsprintf (buf, format, ap);
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vsprintf (buf, format, ap);
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for (i = 0; buf[i]; i++); /* The string is i chars long */
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for (i = 0; buf[i]; i++); /* The string is i chars long */
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str = buf;
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str = buf;
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while (i >= 32)
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while (i >= 32)
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{
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{
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MYwrite_char (kidmum[1], RDP_OSOp);
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MYwrite_char (kidmum[1], RDP_OSOp);
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MYwrite_word (kidmum[1], SWI_Write0);
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MYwrite_word (kidmum[1], SWI_Write0);
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MYwrite_char (kidmum[1], OS_SendString);
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MYwrite_char (kidmum[1], OS_SendString);
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MYwrite_char (kidmum[1], 32); /* Send string 32bytes at a time */
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MYwrite_char (kidmum[1], 32); /* Send string 32bytes at a time */
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for (j = 0; j < 32; j++, str++)
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for (j = 0; j < 32; j++, str++)
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MYwrite_char (kidmum[1], *str);
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MYwrite_char (kidmum[1], *str);
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wait_for_osreply (&junk);
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wait_for_osreply (&junk);
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i -= 32;
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i -= 32;
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}
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}
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if (i > 0)
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if (i > 0)
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{
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{
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MYwrite_char (kidmum[1], RDP_OSOp);
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MYwrite_char (kidmum[1], RDP_OSOp);
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MYwrite_word (kidmum[1], SWI_Write0);
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MYwrite_word (kidmum[1], SWI_Write0);
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MYwrite_char (kidmum[1], OS_SendString);
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MYwrite_char (kidmum[1], OS_SendString);
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MYwrite_char (kidmum[1], (unsigned char) i); /* Send remainder of string */
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MYwrite_char (kidmum[1], (unsigned char) i); /* Send remainder of string */
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for (j = 0; j < i; j++, str++)
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for (j = 0; j < i; j++, str++)
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MYwrite_char (kidmum[1], *str);
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MYwrite_char (kidmum[1], *str);
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wait_for_osreply (&junk);
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wait_for_osreply (&junk);
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}
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}
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va_end (ap);
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va_end (ap);
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return;
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return;
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/* str = buf; */
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/* str = buf; */
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/* while ((ch=*str++) != 0) */
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/* while ((ch=*str++) != 0) */
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/* state->hostif->writec(state->hostif->hostosarg, ch); */
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/* state->hostif->writec(state->hostif->hostosarg, ch); */
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}
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}
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void
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void
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ARMul_DebugPause (ARMul_State * state)
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ARMul_DebugPause (ARMul_State * state)
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{
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{
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if (!(rdi_log & 8))
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if (!(rdi_log & 8))
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state->hostif->dbgpause (state->hostif->dbgarg);
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state->hostif->dbgpause (state->hostif->dbgarg);
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}
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}
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/***************************************************************************\
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/***************************************************************************\
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* RDI_open *
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* RDI_open *
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\***************************************************************************/
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\***************************************************************************/
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static void
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static void
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InitFail (int exitcode, char const *which)
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InitFail (int exitcode, char const *which)
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{
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{
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ARMul_ConsolePrint (state, "%s interface failed to initialise. Exiting\n",
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ARMul_ConsolePrint (state, "%s interface failed to initialise. Exiting\n",
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which);
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which);
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exit (exitcode);
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exit (exitcode);
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}
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}
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static void
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static void
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RDIInit (unsigned type)
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RDIInit (unsigned type)
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{
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{
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if (type == 0)
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if (type == 0)
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{ /* cold start */
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{ /* cold start */
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state->CallDebug = state->MemReadDebug = state->MemWriteDebug = 0;
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state->CallDebug = state->MemReadDebug = state->MemWriteDebug = 0;
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BreaksSet = 0;
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BreaksSet = 0;
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}
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}
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}
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}
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#define UNKNOWNPROC 0
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#define UNKNOWNPROC 0
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typedef struct
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typedef struct
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{
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{
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char name[16];
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char name[16];
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unsigned properties;
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unsigned properties;
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}
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}
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Processor;
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Processor;
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Processor const p_arm2 = { "ARM2", ARM_Fix26_Prop };
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Processor const p_arm2 = { "ARM2", ARM_Fix26_Prop };
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Processor const p_arm2as = { "ARM2AS", ARM_Fix26_Prop };
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Processor const p_arm2as = { "ARM2AS", ARM_Fix26_Prop };
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Processor const p_arm61 = { "ARM61", ARM_Fix26_Prop };
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Processor const p_arm61 = { "ARM61", ARM_Fix26_Prop };
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Processor const p_arm3 = { "ARM3", ARM_Fix26_Prop };
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Processor const p_arm3 = { "ARM3", ARM_Fix26_Prop };
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Processor const p_arm6 = { "ARM6", ARM_Lock_Prop };
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Processor const p_arm6 = { "ARM6", ARM_Lock_Prop };
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Processor const p_arm60 = { "ARM60", ARM_Lock_Prop };
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Processor const p_arm60 = { "ARM60", ARM_Lock_Prop };
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Processor const p_arm600 = { "ARM600", ARM_Lock_Prop };
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Processor const p_arm600 = { "ARM600", ARM_Lock_Prop };
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Processor const p_arm610 = { "ARM610", ARM_Lock_Prop };
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Processor const p_arm610 = { "ARM610", ARM_Lock_Prop };
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Processor const p_arm620 = { "ARM620", ARM_Lock_Prop };
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Processor const p_arm620 = { "ARM620", ARM_Lock_Prop };
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Processor const p_unknown = { "", 0 };
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Processor const p_unknown = { "", 0 };
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Processor const *const processors[] =
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Processor const *const processors[] =
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{
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{
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&p_arm6, /* default: must come first */
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&p_arm6, /* default: must come first */
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&p_arm2,
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&p_arm2,
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&p_arm2as,
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&p_arm2as,
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&p_arm61,
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&p_arm61,
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&p_arm3,
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&p_arm3,
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&p_arm60,
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&p_arm60,
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&p_arm600,
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&p_arm600,
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&p_arm610,
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&p_arm610,
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&p_arm620,
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&p_arm620,
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&p_unknown
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&p_unknown
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};
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};
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typedef struct ProcessorConfig ProcessorConfig;
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typedef struct ProcessorConfig ProcessorConfig;
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struct ProcessorConfig
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struct ProcessorConfig
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{
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{
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long id[2];
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long id[2];
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ProcessorConfig const *self;
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ProcessorConfig const *self;
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long count;
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long count;
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Processor const *const *processors;
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Processor const *const *processors;
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};
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};
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ProcessorConfig const processorconfig = {
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ProcessorConfig const processorconfig = {
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{((((((long) 'x' << 8) | ' ') << 8) | 'c') << 8) | 'p',
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{((((((long) 'x' << 8) | ' ') << 8) | 'c') << 8) | 'p',
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((((((long) 'u' << 8) | 's') << 8) | ' ') << 8) | 'x'},
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((((((long) 'u' << 8) | 's') << 8) | ' ') << 8) | 'x'},
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&processorconfig,
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&processorconfig,
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16,
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16,
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processors
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processors
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};
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};
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static int
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static int
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RDI_open (unsigned type, const Dbg_ConfigBlock * config,
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RDI_open (unsigned type, const Dbg_ConfigBlock * config,
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const Dbg_HostosInterface * hostif, struct Dbg_MCState *dbg_state)
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const Dbg_HostosInterface * hostif, struct Dbg_MCState *dbg_state)
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/* Initialise everything */
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/* Initialise everything */
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{
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{
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int virgin = (state == NULL);
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int virgin = (state == NULL);
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IGNORE (dbg_state);
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IGNORE (dbg_state);
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#ifdef RDI_VERBOSE
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#ifdef RDI_VERBOSE
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if (rdi_log & 1)
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if (rdi_log & 1)
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{
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{
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if (virgin)
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if (virgin)
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ARMul_DebugPrint_i (hostif, "RDI_open: type = %d\n", type);
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ARMul_DebugPrint_i (hostif, "RDI_open: type = %d\n", type);
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else
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else
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ARMul_DebugPrint (state, "RDI_open: type = %d\n", type);
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ARMul_DebugPrint (state, "RDI_open: type = %d\n", type);
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}
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}
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#endif
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#endif
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if (type & 1)
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if (type & 1)
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{ /* Warm start */
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{ /* Warm start */
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ARMul_Reset (state);
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ARMul_Reset (state);
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RDIInit (1);
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RDIInit (1);
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}
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}
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else
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else
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{
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{
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if (virgin)
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if (virgin)
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{
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{
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ARMul_EmulateInit ();
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ARMul_EmulateInit ();
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state = ARMul_NewState ();
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state = ARMul_NewState ();
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state->hostif = hostif;
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state->hostif = hostif;
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{
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{
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int req = config->processor;
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int req = config->processor;
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unsigned processor = processors[req]->val;
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unsigned processor = processors[req]->val;
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ARMul_SelectProcessor (state, processor);
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ARMul_SelectProcessor (state, processor);
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ARMul_Reset (state);
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ARMul_Reset (state);
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ARMul_ConsolePrint (state, "ARMulator V1.50, %s",
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ARMul_ConsolePrint (state, "ARMulator V1.50, %s",
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processors[req]->name);
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processors[req]->name);
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}
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}
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if (ARMul_MemoryInit (state, config->memorysize) == FALSE)
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if (ARMul_MemoryInit (state, config->memorysize) == FALSE)
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InitFail (1, "Memory");
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InitFail (1, "Memory");
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if (config->bytesex != RDISex_DontCare)
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if (config->bytesex != RDISex_DontCare)
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state->bigendSig = config->bytesex;
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state->bigendSig = config->bytesex;
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if (ARMul_CoProInit (state) == FALSE)
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if (ARMul_CoProInit (state) == FALSE)
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InitFail (2, "Co-Processor");
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InitFail (2, "Co-Processor");
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if (ARMul_OSInit (state) == FALSE)
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if (ARMul_OSInit (state) == FALSE)
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InitFail (3, "Operating System");
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InitFail (3, "Operating System");
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}
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}
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ARMul_Reset (state);
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ARMul_Reset (state);
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RDIInit (0);
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RDIInit (0);
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}
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}
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if (type & 2)
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if (type & 2)
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{ /* Reset the comms link */
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{ /* Reset the comms link */
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/* what comms link ? */
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/* what comms link ? */
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}
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}
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if (virgin && (type & 1) == 0) /* Cold start */
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if (virgin && (type & 1) == 0) /* Cold start */
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ARMul_ConsolePrint (state, ", %s endian.\n",
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ARMul_ConsolePrint (state, ", %s endian.\n",
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state->bigendSig ? "Big" : "Little");
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state->bigendSig ? "Big" : "Little");
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|
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if (config->bytesex == RDISex_DontCare)
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if (config->bytesex == RDISex_DontCare)
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return (state->bigendSig ? RDIError_BigEndian : RDIError_LittleEndian);
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return (state->bigendSig ? RDIError_BigEndian : RDIError_LittleEndian);
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else
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else
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return (RDIError_NoError);
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return (RDIError_NoError);
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}
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}
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|
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/***************************************************************************\
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/***************************************************************************\
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* RDI_close *
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* RDI_close *
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\***************************************************************************/
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\***************************************************************************/
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|
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static int
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static int
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RDI_close (void)
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RDI_close (void)
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{
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{
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TracePrint ((state, "RDI_close\n"));
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TracePrint ((state, "RDI_close\n"));
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ARMul_OSExit (state);
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ARMul_OSExit (state);
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ARMul_CoProExit (state);
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ARMul_CoProExit (state);
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ARMul_MemoryExit (state);
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ARMul_MemoryExit (state);
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return (RDIError_NoError);
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return (RDIError_NoError);
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_read *
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* RDI_read *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
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static int
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RDI_read (ARMword source, void *dest, unsigned *nbytes)
|
RDI_read (ARMword source, void *dest, unsigned *nbytes)
|
{
|
{
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unsigned i;
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unsigned i;
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char *memptr = (char *) dest;
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char *memptr = (char *) dest;
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|
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TracePrint ((state, "RDI_read: source=%.8lx dest=%p nbytes=%.8x\n",
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TracePrint ((state, "RDI_read: source=%.8lx dest=%p nbytes=%.8x\n",
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source, dest, *nbytes));
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source, dest, *nbytes));
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|
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for (i = 0; i < *nbytes; i++)
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for (i = 0; i < *nbytes; i++)
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*memptr++ = (char) ARMul_ReadByte (state, source++);
|
*memptr++ = (char) ARMul_ReadByte (state, source++);
|
if (state->abortSig)
|
if (state->abortSig)
|
{
|
{
|
state->abortSig = LOW;
|
state->abortSig = LOW;
|
return (RDIError_DataAbort);
|
return (RDIError_DataAbort);
|
}
|
}
|
return (RDIError_NoError);
|
return (RDIError_NoError);
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_write *
|
* RDI_write *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_write (const void *source, ARMword dest, unsigned *nbytes)
|
RDI_write (const void *source, ARMword dest, unsigned *nbytes)
|
{
|
{
|
unsigned i;
|
unsigned i;
|
char *memptr = (char *) source;
|
char *memptr = (char *) source;
|
|
|
TracePrint ((state, "RDI_write: source=%p dest=%.8lx nbytes=%.8x\n",
|
TracePrint ((state, "RDI_write: source=%p dest=%.8lx nbytes=%.8x\n",
|
source, dest, *nbytes));
|
source, dest, *nbytes));
|
|
|
for (i = 0; i < *nbytes; i++)
|
for (i = 0; i < *nbytes; i++)
|
ARMul_WriteByte (state, (ARMword) dest++, (ARMword) * memptr++);
|
ARMul_WriteByte (state, (ARMword) dest++, (ARMword) * memptr++);
|
|
|
if (state->abortSig)
|
if (state->abortSig)
|
{
|
{
|
state->abortSig = LOW;
|
state->abortSig = LOW;
|
return (RDIError_DataAbort);
|
return (RDIError_DataAbort);
|
}
|
}
|
return (RDIError_NoError);
|
return (RDIError_NoError);
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_CPUread *
|
* RDI_CPUread *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_CPUread (unsigned mode, unsigned long mask, ARMword buffer[])
|
RDI_CPUread (unsigned mode, unsigned long mask, ARMword buffer[])
|
{
|
{
|
unsigned i, upto;
|
unsigned i, upto;
|
|
|
if (mode == RDIMode_Curr)
|
if (mode == RDIMode_Curr)
|
mode = (unsigned) (ARMul_GetCPSR (state) & MODEBITS);
|
mode = (unsigned) (ARMul_GetCPSR (state) & MODEBITS);
|
|
|
for (upto = 0, i = 0; i < 15; i++)
|
for (upto = 0, i = 0; i < 15; i++)
|
if (mask & (1L << i))
|
if (mask & (1L << i))
|
{
|
{
|
buffer[upto++] = ARMul_GetReg (state, mode, i);
|
buffer[upto++] = ARMul_GetReg (state, mode, i);
|
}
|
}
|
|
|
if (mask & RDIReg_R15)
|
if (mask & RDIReg_R15)
|
{
|
{
|
buffer[upto++] = ARMul_GetR15 (state);
|
buffer[upto++] = ARMul_GetR15 (state);
|
}
|
}
|
|
|
if (mask & RDIReg_PC)
|
if (mask & RDIReg_PC)
|
{
|
{
|
buffer[upto++] = ARMul_GetPC (state);
|
buffer[upto++] = ARMul_GetPC (state);
|
}
|
}
|
|
|
if (mask & RDIReg_CPSR)
|
if (mask & RDIReg_CPSR)
|
buffer[upto++] = ARMul_GetCPSR (state);
|
buffer[upto++] = ARMul_GetCPSR (state);
|
|
|
if (mask & RDIReg_SPSR)
|
if (mask & RDIReg_SPSR)
|
buffer[upto++] = ARMul_GetSPSR (state, mode);
|
buffer[upto++] = ARMul_GetSPSR (state, mode);
|
|
|
TracePrint ((state, "RDI_CPUread: mode=%.8x mask=%.8lx", mode, mask));
|
TracePrint ((state, "RDI_CPUread: mode=%.8x mask=%.8lx", mode, mask));
|
#ifdef RDI_VERBOSE
|
#ifdef RDI_VERBOSE
|
if (rdi_log & 1)
|
if (rdi_log & 1)
|
{
|
{
|
for (upto = 0, i = 0; i <= 20; i++)
|
for (upto = 0, i = 0; i <= 20; i++)
|
if (mask & (1L << i))
|
if (mask & (1L << i))
|
{
|
{
|
ARMul_DebugPrint (state, "%c%.8lx", upto % 4 == 0 ? '\n' : ' ',
|
ARMul_DebugPrint (state, "%c%.8lx", upto % 4 == 0 ? '\n' : ' ',
|
buffer[upto]);
|
buffer[upto]);
|
upto++;
|
upto++;
|
}
|
}
|
ARMul_DebugPrint (state, "\n");
|
ARMul_DebugPrint (state, "\n");
|
}
|
}
|
#endif
|
#endif
|
|
|
return (RDIError_NoError);
|
return (RDIError_NoError);
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_CPUwrite *
|
* RDI_CPUwrite *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_CPUwrite (unsigned mode, unsigned long mask, ARMword const buffer[])
|
RDI_CPUwrite (unsigned mode, unsigned long mask, ARMword const buffer[])
|
{
|
{
|
int i, upto;
|
int i, upto;
|
|
|
|
|
TracePrint ((state, "RDI_CPUwrite: mode=%.8x mask=%.8lx", mode, mask));
|
TracePrint ((state, "RDI_CPUwrite: mode=%.8x mask=%.8lx", mode, mask));
|
#ifdef RDI_VERBOSE
|
#ifdef RDI_VERBOSE
|
if (rdi_log & 1)
|
if (rdi_log & 1)
|
{
|
{
|
for (upto = 0, i = 0; i <= 20; i++)
|
for (upto = 0, i = 0; i <= 20; i++)
|
if (mask & (1L << i))
|
if (mask & (1L << i))
|
{
|
{
|
ARMul_DebugPrint (state, "%c%.8lx", upto % 4 == 0 ? '\n' : ' ',
|
ARMul_DebugPrint (state, "%c%.8lx", upto % 4 == 0 ? '\n' : ' ',
|
buffer[upto]);
|
buffer[upto]);
|
upto++;
|
upto++;
|
}
|
}
|
ARMul_DebugPrint (state, "\n");
|
ARMul_DebugPrint (state, "\n");
|
}
|
}
|
#endif
|
#endif
|
|
|
if (mode == RDIMode_Curr)
|
if (mode == RDIMode_Curr)
|
mode = (unsigned) (ARMul_GetCPSR (state) & MODEBITS);
|
mode = (unsigned) (ARMul_GetCPSR (state) & MODEBITS);
|
|
|
for (upto = 0, i = 0; i < 15; i++)
|
for (upto = 0, i = 0; i < 15; i++)
|
if (mask & (1L << i))
|
if (mask & (1L << i))
|
ARMul_SetReg (state, mode, i, buffer[upto++]);
|
ARMul_SetReg (state, mode, i, buffer[upto++]);
|
|
|
if (mask & RDIReg_R15)
|
if (mask & RDIReg_R15)
|
ARMul_SetR15 (state, buffer[upto++]);
|
ARMul_SetR15 (state, buffer[upto++]);
|
|
|
if (mask & RDIReg_PC)
|
if (mask & RDIReg_PC)
|
{
|
{
|
|
|
ARMul_SetPC (state, buffer[upto++]);
|
ARMul_SetPC (state, buffer[upto++]);
|
}
|
}
|
if (mask & RDIReg_CPSR)
|
if (mask & RDIReg_CPSR)
|
ARMul_SetCPSR (state, buffer[upto++]);
|
ARMul_SetCPSR (state, buffer[upto++]);
|
|
|
if (mask & RDIReg_SPSR)
|
if (mask & RDIReg_SPSR)
|
ARMul_SetSPSR (state, mode, buffer[upto++]);
|
ARMul_SetSPSR (state, mode, buffer[upto++]);
|
|
|
return (RDIError_NoError);
|
return (RDIError_NoError);
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_CPread *
|
* RDI_CPread *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_CPread (unsigned CPnum, unsigned long mask, ARMword buffer[])
|
RDI_CPread (unsigned CPnum, unsigned long mask, ARMword buffer[])
|
{
|
{
|
ARMword fpregsaddr, word[4];
|
ARMword fpregsaddr, word[4];
|
|
|
unsigned r, w;
|
unsigned r, w;
|
unsigned upto;
|
unsigned upto;
|
|
|
if (CPnum != 1 && CPnum != 2)
|
if (CPnum != 1 && CPnum != 2)
|
{
|
{
|
unsigned char const *rmap = state->CPRegWords[CPnum];
|
unsigned char const *rmap = state->CPRegWords[CPnum];
|
if (rmap == NULL)
|
if (rmap == NULL)
|
return (RDIError_UnknownCoPro);
|
return (RDIError_UnknownCoPro);
|
for (upto = 0, r = 0; r < rmap[-1]; r++)
|
for (upto = 0, r = 0; r < rmap[-1]; r++)
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
{
|
{
|
(void) state->CPRead[CPnum] (state, r, &buffer[upto]);
|
(void) state->CPRead[CPnum] (state, r, &buffer[upto]);
|
upto += rmap[r];
|
upto += rmap[r];
|
}
|
}
|
TracePrint ((state, "RDI_CPread: CPnum=%d mask=%.8lx", CPnum, mask));
|
TracePrint ((state, "RDI_CPread: CPnum=%d mask=%.8lx", CPnum, mask));
|
#ifdef RDI_VERBOSE
|
#ifdef RDI_VERBOSE
|
if (rdi_log & 1)
|
if (rdi_log & 1)
|
{
|
{
|
w = 0;
|
w = 0;
|
for (upto = 0, r = 0; r < rmap[-1]; r++)
|
for (upto = 0, r = 0; r < rmap[-1]; r++)
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
{
|
{
|
int words = rmap[r];
|
int words = rmap[r];
|
ARMul_DebugPrint (state, "%c%2d",
|
ARMul_DebugPrint (state, "%c%2d",
|
(w >= 4 ? (w = 0, '\n') : ' '), r);
|
(w >= 4 ? (w = 0, '\n') : ' '), r);
|
while (--words >= 0)
|
while (--words >= 0)
|
{
|
{
|
ARMul_DebugPrint (state, " %.8lx", buffer[upto++]);
|
ARMul_DebugPrint (state, " %.8lx", buffer[upto++]);
|
w++;
|
w++;
|
}
|
}
|
}
|
}
|
ARMul_DebugPrint (state, "\n");
|
ARMul_DebugPrint (state, "\n");
|
}
|
}
|
#endif
|
#endif
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
|
|
#ifdef NOFPE
|
#ifdef NOFPE
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
|
|
#else
|
#else
|
if (FPRegsAddr == 0)
|
if (FPRegsAddr == 0)
|
{
|
{
|
fpregsaddr = ARMul_ReadWord (state, 4L);
|
fpregsaddr = ARMul_ReadWord (state, 4L);
|
if ((fpregsaddr & 0xff800000) != 0xea000000) /* Must be a forward branch */
|
if ((fpregsaddr & 0xff800000) != 0xea000000) /* Must be a forward branch */
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
fpregsaddr = ((fpregsaddr & 0xffffff) << 2) + 8; /* address in __fp_decode - 4 */
|
fpregsaddr = ((fpregsaddr & 0xffffff) << 2) + 8; /* address in __fp_decode - 4 */
|
if ((fpregsaddr < FPESTART) || (fpregsaddr >= FPEEND))
|
if ((fpregsaddr < FPESTART) || (fpregsaddr >= FPEEND))
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
fpregsaddr = ARMul_ReadWord (state, fpregsaddr); /* pointer to fp registers */
|
fpregsaddr = ARMul_ReadWord (state, fpregsaddr); /* pointer to fp registers */
|
FPRegsAddr = fpregsaddr;
|
FPRegsAddr = fpregsaddr;
|
}
|
}
|
else
|
else
|
fpregsaddr = FPRegsAddr;
|
fpregsaddr = FPRegsAddr;
|
|
|
if (fpregsaddr == 0)
|
if (fpregsaddr == 0)
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
for (upto = 0, r = 0; r < 8; r++)
|
for (upto = 0, r = 0; r < 8; r++)
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
{
|
{
|
for (w = 0; w < 4; w++)
|
for (w = 0; w < 4; w++)
|
word[w] =
|
word[w] =
|
ARMul_ReadWord (state,
|
ARMul_ReadWord (state,
|
fpregsaddr + (ARMword) r * 16 + (ARMword) w * 4);
|
fpregsaddr + (ARMword) r * 16 + (ARMword) w * 4);
|
switch ((int) (word[3] >> 29))
|
switch ((int) (word[3] >> 29))
|
{
|
{
|
case 0:
|
case 0:
|
case 2:
|
case 2:
|
case 4:
|
case 4:
|
case 6: /* its unpacked, convert to extended */
|
case 6: /* its unpacked, convert to extended */
|
buffer[upto++] = 2; /* mark as extended */
|
buffer[upto++] = 2; /* mark as extended */
|
buffer[upto++] = (word[3] & 0x7fff) | (word[0] & 0x80000000); /* exp and sign */
|
buffer[upto++] = (word[3] & 0x7fff) | (word[0] & 0x80000000); /* exp and sign */
|
buffer[upto++] = word[1]; /* mantissa 1 */
|
buffer[upto++] = word[1]; /* mantissa 1 */
|
buffer[upto++] = word[2]; /* mantissa 2 */
|
buffer[upto++] = word[2]; /* mantissa 2 */
|
break;
|
break;
|
case 1: /* packed single */
|
case 1: /* packed single */
|
buffer[upto++] = 0; /* mark as single */
|
buffer[upto++] = 0; /* mark as single */
|
buffer[upto++] = word[0]; /* sign, exp and mantissa */
|
buffer[upto++] = word[0]; /* sign, exp and mantissa */
|
buffer[upto++] = word[1]; /* padding */
|
buffer[upto++] = word[1]; /* padding */
|
buffer[upto++] = word[2]; /* padding */
|
buffer[upto++] = word[2]; /* padding */
|
break;
|
break;
|
case 3: /* packed double */
|
case 3: /* packed double */
|
buffer[upto++] = 1; /* mark as double */
|
buffer[upto++] = 1; /* mark as double */
|
buffer[upto++] = word[0]; /* sign, exp and mantissa1 */
|
buffer[upto++] = word[0]; /* sign, exp and mantissa1 */
|
buffer[upto++] = word[1]; /* mantissa 2 */
|
buffer[upto++] = word[1]; /* mantissa 2 */
|
buffer[upto++] = word[2]; /* padding */
|
buffer[upto++] = word[2]; /* padding */
|
break;
|
break;
|
case 5: /* packed extended */
|
case 5: /* packed extended */
|
buffer[upto++] = 2; /* mark as extended */
|
buffer[upto++] = 2; /* mark as extended */
|
buffer[upto++] = word[0]; /* sign and exp */
|
buffer[upto++] = word[0]; /* sign and exp */
|
buffer[upto++] = word[1]; /* mantissa 1 */
|
buffer[upto++] = word[1]; /* mantissa 1 */
|
buffer[upto++] = word[2]; /* mantissa 2 */
|
buffer[upto++] = word[2]; /* mantissa 2 */
|
break;
|
break;
|
case 7: /* packed decimal */
|
case 7: /* packed decimal */
|
buffer[upto++] = 3; /* mark as packed decimal */
|
buffer[upto++] = 3; /* mark as packed decimal */
|
buffer[upto++] = word[0]; /* sign, exp and mantissa1 */
|
buffer[upto++] = word[0]; /* sign, exp and mantissa1 */
|
buffer[upto++] = word[1]; /* mantissa 2 */
|
buffer[upto++] = word[1]; /* mantissa 2 */
|
buffer[upto++] = word[2]; /* mantissa 3 */
|
buffer[upto++] = word[2]; /* mantissa 3 */
|
break;
|
break;
|
}
|
}
|
}
|
}
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
buffer[upto++] = ARMul_ReadWord (state, fpregsaddr + 128); /* fpsr */
|
buffer[upto++] = ARMul_ReadWord (state, fpregsaddr + 128); /* fpsr */
|
if (mask & (1L << (r + 1)))
|
if (mask & (1L << (r + 1)))
|
buffer[upto++] = 0; /* fpcr */
|
buffer[upto++] = 0; /* fpcr */
|
|
|
TracePrint ((state, "RDI_CPread: CPnum=%d mask=%.8lx\n", CPnum, mask));
|
TracePrint ((state, "RDI_CPread: CPnum=%d mask=%.8lx\n", CPnum, mask));
|
#ifdef RDI_VERBOSE
|
#ifdef RDI_VERBOSE
|
if (rdi_log & 1)
|
if (rdi_log & 1)
|
{
|
{
|
for (upto = 0, r = 0; r < 9; r++)
|
for (upto = 0, r = 0; r < 9; r++)
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
{
|
{
|
if (r != 8)
|
if (r != 8)
|
{
|
{
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
}
|
}
|
ARMul_DebugPrint (state, "%08lx\n", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx\n", buffer[upto++]);
|
}
|
}
|
ARMul_DebugPrint (state, "\n");
|
ARMul_DebugPrint (state, "\n");
|
}
|
}
|
#endif
|
#endif
|
return (RDIError_NoError);
|
return (RDIError_NoError);
|
#endif /* NOFPE */
|
#endif /* NOFPE */
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_CPwrite *
|
* RDI_CPwrite *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_CPwrite (unsigned CPnum, unsigned long mask, ARMword const buffer[])
|
RDI_CPwrite (unsigned CPnum, unsigned long mask, ARMword const buffer[])
|
{
|
{
|
unsigned r;
|
unsigned r;
|
unsigned upto;
|
unsigned upto;
|
ARMword fpregsaddr;
|
ARMword fpregsaddr;
|
|
|
if (CPnum != 1 && CPnum != 2)
|
if (CPnum != 1 && CPnum != 2)
|
{
|
{
|
unsigned char const *rmap = state->CPRegWords[CPnum];
|
unsigned char const *rmap = state->CPRegWords[CPnum];
|
if (rmap == NULL)
|
if (rmap == NULL)
|
return (RDIError_UnknownCoPro);
|
return (RDIError_UnknownCoPro);
|
TracePrint ((state, "RDI_CPwrite: CPnum=%d mask=%.8lx", CPnum, mask));
|
TracePrint ((state, "RDI_CPwrite: CPnum=%d mask=%.8lx", CPnum, mask));
|
#ifdef RDI_VERBOSE
|
#ifdef RDI_VERBOSE
|
if (rdi_log & 1)
|
if (rdi_log & 1)
|
{
|
{
|
int w = 0;
|
int w = 0;
|
for (upto = 0, r = 0; r < rmap[-1]; r++)
|
for (upto = 0, r = 0; r < rmap[-1]; r++)
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
{
|
{
|
int words = rmap[r];
|
int words = rmap[r];
|
ARMul_DebugPrint (state, "%c%2d",
|
ARMul_DebugPrint (state, "%c%2d",
|
(w >= 4 ? (w = 0, '\n') : ' '), r);
|
(w >= 4 ? (w = 0, '\n') : ' '), r);
|
while (--words >= 0)
|
while (--words >= 0)
|
{
|
{
|
ARMul_DebugPrint (state, " %.8lx", buffer[upto++]);
|
ARMul_DebugPrint (state, " %.8lx", buffer[upto++]);
|
w++;
|
w++;
|
}
|
}
|
}
|
}
|
ARMul_DebugPrint (state, "\n");
|
ARMul_DebugPrint (state, "\n");
|
}
|
}
|
#endif
|
#endif
|
for (upto = 0, r = 0; r < rmap[-1]; r++)
|
for (upto = 0, r = 0; r < rmap[-1]; r++)
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
{
|
{
|
(void) state->CPWrite[CPnum] (state, r, &buffer[upto]);
|
(void) state->CPWrite[CPnum] (state, r, &buffer[upto]);
|
upto += rmap[r];
|
upto += rmap[r];
|
}
|
}
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
|
|
#ifdef NOFPE
|
#ifdef NOFPE
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
|
|
#else
|
#else
|
TracePrint ((state, "RDI_CPwrite: CPnum=%d mask=%.8lx", CPnum, mask));
|
TracePrint ((state, "RDI_CPwrite: CPnum=%d mask=%.8lx", CPnum, mask));
|
#ifdef RDI_VERBOSE
|
#ifdef RDI_VERBOSE
|
if (rdi_log & 1)
|
if (rdi_log & 1)
|
{
|
{
|
for (upto = 0, r = 0; r < 9; r++)
|
for (upto = 0, r = 0; r < 9; r++)
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
{
|
{
|
if (r != 8)
|
if (r != 8)
|
{
|
{
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx ", buffer[upto++]);
|
}
|
}
|
ARMul_DebugPrint (state, "%08lx\n", buffer[upto++]);
|
ARMul_DebugPrint (state, "%08lx\n", buffer[upto++]);
|
}
|
}
|
ARMul_DebugPrint (state, "\n");
|
ARMul_DebugPrint (state, "\n");
|
}
|
}
|
#endif
|
#endif
|
|
|
if (FPRegsAddr == 0)
|
if (FPRegsAddr == 0)
|
{
|
{
|
fpregsaddr = ARMul_ReadWord (state, 4L);
|
fpregsaddr = ARMul_ReadWord (state, 4L);
|
if ((fpregsaddr & 0xff800000) != 0xea000000) /* Must be a forward branch */
|
if ((fpregsaddr & 0xff800000) != 0xea000000) /* Must be a forward branch */
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
fpregsaddr = ((fpregsaddr & 0xffffff) << 2) + 8; /* address in __fp_decode - 4 */
|
fpregsaddr = ((fpregsaddr & 0xffffff) << 2) + 8; /* address in __fp_decode - 4 */
|
if ((fpregsaddr < FPESTART) || (fpregsaddr >= FPEEND))
|
if ((fpregsaddr < FPESTART) || (fpregsaddr >= FPEEND))
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
fpregsaddr = ARMul_ReadWord (state, fpregsaddr); /* pointer to fp registers */
|
fpregsaddr = ARMul_ReadWord (state, fpregsaddr); /* pointer to fp registers */
|
FPRegsAddr = fpregsaddr;
|
FPRegsAddr = fpregsaddr;
|
}
|
}
|
else
|
else
|
fpregsaddr = FPRegsAddr;
|
fpregsaddr = FPRegsAddr;
|
|
|
if (fpregsaddr == 0)
|
if (fpregsaddr == 0)
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
for (upto = 0, r = 0; r < 8; r++)
|
for (upto = 0, r = 0; r < 8; r++)
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
{
|
{
|
ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16,
|
ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16,
|
buffer[upto + 1]);
|
buffer[upto + 1]);
|
ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 4,
|
ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 4,
|
buffer[upto + 2]);
|
buffer[upto + 2]);
|
ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 8,
|
ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 8,
|
buffer[upto + 3]);
|
buffer[upto + 3]);
|
ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 12,
|
ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 12,
|
(buffer[upto] * 2 + 1) << 29); /* mark type */
|
(buffer[upto] * 2 + 1) << 29); /* mark type */
|
upto += 4;
|
upto += 4;
|
}
|
}
|
if (mask & (1L << r))
|
if (mask & (1L << r))
|
ARMul_WriteWord (state, fpregsaddr + 128, buffer[upto++]); /* fpsr */
|
ARMul_WriteWord (state, fpregsaddr + 128, buffer[upto++]); /* fpsr */
|
return (RDIError_NoError);
|
return (RDIError_NoError);
|
#endif /* NOFPE */
|
#endif /* NOFPE */
|
}
|
}
|
|
|
static void
|
static void
|
deletebreaknode (BreakNode ** prevp)
|
deletebreaknode (BreakNode ** prevp)
|
{
|
{
|
BreakNode *p = *prevp;
|
BreakNode *p = *prevp;
|
*prevp = p->next;
|
*prevp = p->next;
|
ARMul_WriteWord (state, p->address, p->inst);
|
ARMul_WriteWord (state, p->address, p->inst);
|
free ((char *) p);
|
free ((char *) p);
|
BreaksSet--;
|
BreaksSet--;
|
state->CallDebug--;
|
state->CallDebug--;
|
}
|
}
|
|
|
static int
|
static int
|
removebreak (ARMword address, unsigned type)
|
removebreak (ARMword address, unsigned type)
|
{
|
{
|
BreakNode *p, **prevp = &BreakList;
|
BreakNode *p, **prevp = &BreakList;
|
for (; (p = *prevp) != NULL; prevp = &p->next)
|
for (; (p = *prevp) != NULL; prevp = &p->next)
|
if (p->address == address && p->type == type)
|
if (p->address == address && p->type == type)
|
{
|
{
|
deletebreaknode (prevp);
|
deletebreaknode (prevp);
|
return TRUE;
|
return TRUE;
|
}
|
}
|
return FALSE;
|
return FALSE;
|
}
|
}
|
|
|
/* This routine installs a breakpoint into the breakpoint table */
|
/* This routine installs a breakpoint into the breakpoint table */
|
|
|
static BreakNode *
|
static BreakNode *
|
installbreak (ARMword address, unsigned type, ARMword bound)
|
installbreak (ARMword address, unsigned type, ARMword bound)
|
{
|
{
|
BreakNode *p = (BreakNode *) malloc (sizeof (BreakNode));
|
BreakNode *p = (BreakNode *) malloc (sizeof (BreakNode));
|
p->next = BreakList;
|
p->next = BreakList;
|
BreakList = p;
|
BreakList = p;
|
p->address = address;
|
p->address = address;
|
p->type = type;
|
p->type = type;
|
p->bound = bound;
|
p->bound = bound;
|
p->inst = ARMul_ReadWord (state, address);
|
p->inst = ARMul_ReadWord (state, address);
|
ARMul_WriteWord (state, address, 0xee000000L);
|
ARMul_WriteWord (state, address, 0xee000000L);
|
return p;
|
return p;
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_setbreak *
|
* RDI_setbreak *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_setbreak (ARMword address, unsigned type, ARMword bound,
|
RDI_setbreak (ARMword address, unsigned type, ARMword bound,
|
PointHandle * handle)
|
PointHandle * handle)
|
{
|
{
|
BreakNode *p;
|
BreakNode *p;
|
TracePrint ((state, "RDI_setbreak: address=%.8lx type=%d bound=%.8lx\n",
|
TracePrint ((state, "RDI_setbreak: address=%.8lx type=%d bound=%.8lx\n",
|
address, type, bound));
|
address, type, bound));
|
|
|
removebreak (address, type);
|
removebreak (address, type);
|
p = installbreak (address, type, bound);
|
p = installbreak (address, type, bound);
|
BreaksSet++;
|
BreaksSet++;
|
state->CallDebug++;
|
state->CallDebug++;
|
*handle = (PointHandle) p;
|
*handle = (PointHandle) p;
|
TracePrint ((state, " returns %.8lx\n", *handle));
|
TracePrint ((state, " returns %.8lx\n", *handle));
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_clearbreak *
|
* RDI_clearbreak *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_clearbreak (PointHandle handle)
|
RDI_clearbreak (PointHandle handle)
|
{
|
{
|
TracePrint ((state, "RDI_clearbreak: address=%.8lx\n", handle));
|
TracePrint ((state, "RDI_clearbreak: address=%.8lx\n", handle));
|
{
|
{
|
BreakNode *p, **prevp = &BreakList;
|
BreakNode *p, **prevp = &BreakList;
|
for (; (p = *prevp) != NULL; prevp = &p->next)
|
for (; (p = *prevp) != NULL; prevp = &p->next)
|
if (p == (BreakNode *) handle)
|
if (p == (BreakNode *) handle)
|
break;
|
break;
|
if (p == NULL)
|
if (p == NULL)
|
return RDIError_NoSuchPoint;
|
return RDIError_NoSuchPoint;
|
deletebreaknode (prevp);
|
deletebreaknode (prevp);
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* Internal functions for breakpoint table manipulation *
|
* Internal functions for breakpoint table manipulation *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static void
|
static void
|
deletewatchnode (WatchNode ** prevp)
|
deletewatchnode (WatchNode ** prevp)
|
{
|
{
|
WatchNode *p = *prevp;
|
WatchNode *p = *prevp;
|
if (p->datatype & Watch_AnyRead)
|
if (p->datatype & Watch_AnyRead)
|
state->MemReadDebug--;
|
state->MemReadDebug--;
|
if (p->datatype & Watch_AnyWrite)
|
if (p->datatype & Watch_AnyWrite)
|
state->MemWriteDebug--;
|
state->MemWriteDebug--;
|
*prevp = p->next;
|
*prevp = p->next;
|
free ((char *) p);
|
free ((char *) p);
|
}
|
}
|
|
|
int
|
int
|
removewatch (ARMword address, unsigned type)
|
removewatch (ARMword address, unsigned type)
|
{
|
{
|
WatchNode *p, **prevp = &WatchList;
|
WatchNode *p, **prevp = &WatchList;
|
for (; (p = *prevp) != NULL; prevp = &p->next)
|
for (; (p = *prevp) != NULL; prevp = &p->next)
|
if (p->address == address && p->type == type)
|
if (p->address == address && p->type == type)
|
{ /* found a match */
|
{ /* found a match */
|
deletewatchnode (prevp);
|
deletewatchnode (prevp);
|
return TRUE;
|
return TRUE;
|
}
|
}
|
return FALSE; /* never found a match */
|
return FALSE; /* never found a match */
|
}
|
}
|
|
|
static WatchNode *
|
static WatchNode *
|
installwatch (ARMword address, unsigned type, unsigned datatype,
|
installwatch (ARMword address, unsigned type, unsigned datatype,
|
ARMword bound)
|
ARMword bound)
|
{
|
{
|
WatchNode *p = (WatchNode *) malloc (sizeof (WatchNode));
|
WatchNode *p = (WatchNode *) malloc (sizeof (WatchNode));
|
p->next = WatchList;
|
p->next = WatchList;
|
WatchList = p;
|
WatchList = p;
|
p->address = address;
|
p->address = address;
|
p->type = type;
|
p->type = type;
|
p->datatype = datatype;
|
p->datatype = datatype;
|
p->bound = bound;
|
p->bound = bound;
|
return p;
|
return p;
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_setwatch *
|
* RDI_setwatch *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_setwatch (ARMword address, unsigned type, unsigned datatype,
|
RDI_setwatch (ARMword address, unsigned type, unsigned datatype,
|
ARMword bound, PointHandle * handle)
|
ARMword bound, PointHandle * handle)
|
{
|
{
|
WatchNode *p;
|
WatchNode *p;
|
TracePrint (
|
TracePrint (
|
(state,
|
(state,
|
"RDI_setwatch: address=%.8lx type=%d datatype=%d bound=%.8lx",
|
"RDI_setwatch: address=%.8lx type=%d datatype=%d bound=%.8lx",
|
address, type, datatype, bound));
|
address, type, datatype, bound));
|
|
|
if (!state->CanWatch)
|
if (!state->CanWatch)
|
return RDIError_UnimplementedMessage;
|
return RDIError_UnimplementedMessage;
|
|
|
removewatch (address, type);
|
removewatch (address, type);
|
p = installwatch (address, type, datatype, bound);
|
p = installwatch (address, type, datatype, bound);
|
if (datatype & Watch_AnyRead)
|
if (datatype & Watch_AnyRead)
|
state->MemReadDebug++;
|
state->MemReadDebug++;
|
if (datatype & Watch_AnyWrite)
|
if (datatype & Watch_AnyWrite)
|
state->MemWriteDebug++;
|
state->MemWriteDebug++;
|
*handle = (PointHandle) p;
|
*handle = (PointHandle) p;
|
TracePrint ((state, " returns %.8lx\n", *handle));
|
TracePrint ((state, " returns %.8lx\n", *handle));
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_clearwatch *
|
* RDI_clearwatch *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_clearwatch (PointHandle handle)
|
RDI_clearwatch (PointHandle handle)
|
{
|
{
|
TracePrint ((state, "RDI_clearwatch: address=%.8lx\n", handle));
|
TracePrint ((state, "RDI_clearwatch: address=%.8lx\n", handle));
|
{
|
{
|
WatchNode *p, **prevp = &WatchList;
|
WatchNode *p, **prevp = &WatchList;
|
for (; (p = *prevp) != NULL; prevp = &p->next)
|
for (; (p = *prevp) != NULL; prevp = &p->next)
|
if (p == (WatchNode *) handle)
|
if (p == (WatchNode *) handle)
|
break;
|
break;
|
if (p == NULL)
|
if (p == NULL)
|
return RDIError_NoSuchPoint;
|
return RDIError_NoSuchPoint;
|
deletewatchnode (prevp);
|
deletewatchnode (prevp);
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_execute *
|
* RDI_execute *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_execute (PointHandle * handle)
|
RDI_execute (PointHandle * handle)
|
{
|
{
|
TracePrint ((state, "RDI_execute\n"));
|
TracePrint ((state, "RDI_execute\n"));
|
if (rdi_log & 4)
|
if (rdi_log & 4)
|
{
|
{
|
state->CallDebug++;
|
state->CallDebug++;
|
state->Debug = TRUE;
|
state->Debug = TRUE;
|
}
|
}
|
state->EndCondition = RDIError_NoError;
|
state->EndCondition = RDIError_NoError;
|
state->StopHandle = 0;
|
state->StopHandle = 0;
|
|
|
ARMul_DoProg (state);
|
ARMul_DoProg (state);
|
|
|
*handle = state->StopHandle;
|
*handle = state->StopHandle;
|
state->Reg[15] -= 8; /* undo the pipeline */
|
state->Reg[15] -= 8; /* undo the pipeline */
|
if (rdi_log & 4)
|
if (rdi_log & 4)
|
{
|
{
|
state->CallDebug--;
|
state->CallDebug--;
|
state->Debug = FALSE;
|
state->Debug = FALSE;
|
}
|
}
|
return (state->EndCondition);
|
return (state->EndCondition);
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_step *
|
* RDI_step *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_step (unsigned ninstr, PointHandle * handle)
|
RDI_step (unsigned ninstr, PointHandle * handle)
|
{
|
{
|
|
|
TracePrint ((state, "RDI_step\n"));
|
TracePrint ((state, "RDI_step\n"));
|
if (ninstr != 1)
|
if (ninstr != 1)
|
return RDIError_UnimplementedMessage;
|
return RDIError_UnimplementedMessage;
|
if (rdi_log & 4)
|
if (rdi_log & 4)
|
{
|
{
|
state->CallDebug++;
|
state->CallDebug++;
|
state->Debug = TRUE;
|
state->Debug = TRUE;
|
}
|
}
|
state->EndCondition = RDIError_NoError;
|
state->EndCondition = RDIError_NoError;
|
state->StopHandle = 0;
|
state->StopHandle = 0;
|
ARMul_DoInstr (state);
|
ARMul_DoInstr (state);
|
*handle = state->StopHandle;
|
*handle = state->StopHandle;
|
state->Reg[15] -= 8; /* undo the pipeline */
|
state->Reg[15] -= 8; /* undo the pipeline */
|
if (rdi_log & 4)
|
if (rdi_log & 4)
|
{
|
{
|
state->CallDebug--;
|
state->CallDebug--;
|
state->Debug = FALSE;
|
state->Debug = FALSE;
|
}
|
}
|
return (state->EndCondition);
|
return (state->EndCondition);
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* RDI_info *
|
* RDI_info *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
static int
|
static int
|
RDI_info (unsigned type, ARMword * arg1, ARMword * arg2)
|
RDI_info (unsigned type, ARMword * arg1, ARMword * arg2)
|
{
|
{
|
switch (type)
|
switch (type)
|
{
|
{
|
case RDIInfo_Target:
|
case RDIInfo_Target:
|
TracePrint ((state, "RDI_Info_Target\n"));
|
TracePrint ((state, "RDI_Info_Target\n"));
|
/* Emulator, speed 10**5 IPS */
|
/* Emulator, speed 10**5 IPS */
|
*arg1 = 5 | HIGHEST_RDI_LEVEL << 5 | LOWEST_RDI_LEVEL << 8;
|
*arg1 = 5 | HIGHEST_RDI_LEVEL << 5 | LOWEST_RDI_LEVEL << 8;
|
*arg2 = 1298224434;
|
*arg2 = 1298224434;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDIInfo_Points:
|
case RDIInfo_Points:
|
{
|
{
|
ARMword n = RDIPointCapability_Comparison | RDIPointCapability_Range |
|
ARMword n = RDIPointCapability_Comparison | RDIPointCapability_Range |
|
RDIPointCapability_Mask | RDIPointCapability_Status;
|
RDIPointCapability_Mask | RDIPointCapability_Status;
|
TracePrint ((state, "RDI_Info_Points\n"));
|
TracePrint ((state, "RDI_Info_Points\n"));
|
if (state->CanWatch)
|
if (state->CanWatch)
|
n |= (Watch_AnyRead + Watch_AnyWrite) << 2;
|
n |= (Watch_AnyRead + Watch_AnyWrite) << 2;
|
*arg1 = n;
|
*arg1 = n;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
|
|
case RDIInfo_Step:
|
case RDIInfo_Step:
|
TracePrint ((state, "RDI_Info_Step\n"));
|
TracePrint ((state, "RDI_Info_Step\n"));
|
*arg1 = RDIStep_Single;
|
*arg1 = RDIStep_Single;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDIInfo_MMU:
|
case RDIInfo_MMU:
|
TracePrint ((state, "RDI_Info_MMU\n"));
|
TracePrint ((state, "RDI_Info_MMU\n"));
|
*arg1 = 1313820229;
|
*arg1 = 1313820229;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDISignal_Stop:
|
case RDISignal_Stop:
|
TracePrint ((state, "RDISignal_Stop\n"));
|
TracePrint ((state, "RDISignal_Stop\n"));
|
state->CallDebug++;
|
state->CallDebug++;
|
state->EndCondition = RDIError_UserInterrupt;
|
state->EndCondition = RDIError_UserInterrupt;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDIVector_Catch:
|
case RDIVector_Catch:
|
TracePrint ((state, "RDIVector_Catch %.8lx\n", *arg1));
|
TracePrint ((state, "RDIVector_Catch %.8lx\n", *arg1));
|
state->VectorCatch = (unsigned) *arg1;
|
state->VectorCatch = (unsigned) *arg1;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDISet_Cmdline:
|
case RDISet_Cmdline:
|
TracePrint ((state, "RDI_Set_Cmdline %s\n", (char *) arg1));
|
TracePrint ((state, "RDI_Set_Cmdline %s\n", (char *) arg1));
|
state->CommandLine =
|
state->CommandLine =
|
(char *) malloc ((unsigned) strlen ((char *) arg1) + 1);
|
(char *) malloc ((unsigned) strlen ((char *) arg1) + 1);
|
(void) strcpy (state->CommandLine, (char *) arg1);
|
(void) strcpy (state->CommandLine, (char *) arg1);
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDICycles:
|
case RDICycles:
|
TracePrint ((state, "RDI_Info_Cycles\n"));
|
TracePrint ((state, "RDI_Info_Cycles\n"));
|
arg1[0] = 0;
|
arg1[0] = 0;
|
arg1[1] = state->NumInstrs;
|
arg1[1] = state->NumInstrs;
|
arg1[2] = 0;
|
arg1[2] = 0;
|
arg1[3] = state->NumScycles;
|
arg1[3] = state->NumScycles;
|
arg1[4] = 0;
|
arg1[4] = 0;
|
arg1[5] = state->NumNcycles;
|
arg1[5] = state->NumNcycles;
|
arg1[6] = 0;
|
arg1[6] = 0;
|
arg1[7] = state->NumIcycles;
|
arg1[7] = state->NumIcycles;
|
arg1[8] = 0;
|
arg1[8] = 0;
|
arg1[9] = state->NumCcycles;
|
arg1[9] = state->NumCcycles;
|
arg1[10] = 0;
|
arg1[10] = 0;
|
arg1[11] = state->NumFcycles;
|
arg1[11] = state->NumFcycles;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDIErrorP:
|
case RDIErrorP:
|
*arg1 = ARMul_OSLastErrorP (state);
|
*arg1 = ARMul_OSLastErrorP (state);
|
TracePrint ((state, "RDI_ErrorP returns %ld\n", *arg1));
|
TracePrint ((state, "RDI_ErrorP returns %ld\n", *arg1));
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDIInfo_DescribeCoPro:
|
case RDIInfo_DescribeCoPro:
|
{
|
{
|
int cpnum = *(int *) arg1;
|
int cpnum = *(int *) arg1;
|
struct Dbg_CoProDesc *cpd = (struct Dbg_CoProDesc *) arg2;
|
struct Dbg_CoProDesc *cpd = (struct Dbg_CoProDesc *) arg2;
|
int i;
|
int i;
|
unsigned char const *map = state->CPRegWords[cpnum];
|
unsigned char const *map = state->CPRegWords[cpnum];
|
if (map == NULL)
|
if (map == NULL)
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
for (i = 0; i < cpd->entries; i++)
|
for (i = 0; i < cpd->entries; i++)
|
{
|
{
|
unsigned r, w = cpd->regdesc[i].nbytes / sizeof (ARMword);
|
unsigned r, w = cpd->regdesc[i].nbytes / sizeof (ARMword);
|
for (r = cpd->regdesc[i].rmin; r <= cpd->regdesc[i].rmax; r++)
|
for (r = cpd->regdesc[i].rmin; r <= cpd->regdesc[i].rmax; r++)
|
if (map[r] != w)
|
if (map[r] != w)
|
return RDIError_BadCoProState;
|
return RDIError_BadCoProState;
|
}
|
}
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
|
|
case RDIInfo_RequestCoProDesc:
|
case RDIInfo_RequestCoProDesc:
|
{
|
{
|
int cpnum = *(int *) arg1;
|
int cpnum = *(int *) arg1;
|
struct Dbg_CoProDesc *cpd = (struct Dbg_CoProDesc *) arg2;
|
struct Dbg_CoProDesc *cpd = (struct Dbg_CoProDesc *) arg2;
|
int i = -1, lastw = -1, r;
|
int i = -1, lastw = -1, r;
|
unsigned char const *map;
|
unsigned char const *map;
|
if ((unsigned) cpnum >= 16)
|
if ((unsigned) cpnum >= 16)
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
map = state->CPRegWords[cpnum];
|
map = state->CPRegWords[cpnum];
|
if (map == NULL)
|
if (map == NULL)
|
return RDIError_UnknownCoPro;
|
return RDIError_UnknownCoPro;
|
for (r = 0; r < map[-1]; r++)
|
for (r = 0; r < map[-1]; r++)
|
{
|
{
|
int words = map[r];
|
int words = map[r];
|
if (words == lastw)
|
if (words == lastw)
|
cpd->regdesc[i].rmax = r;
|
cpd->regdesc[i].rmax = r;
|
else
|
else
|
{
|
{
|
if (++i >= cpd->entries)
|
if (++i >= cpd->entries)
|
return RDIError_BufferFull;
|
return RDIError_BufferFull;
|
cpd->regdesc[i].rmax = cpd->regdesc[i].rmin = r;
|
cpd->regdesc[i].rmax = cpd->regdesc[i].rmin = r;
|
cpd->regdesc[i].nbytes = words * sizeof (ARMword);
|
cpd->regdesc[i].nbytes = words * sizeof (ARMword);
|
cpd->regdesc[i].access =
|
cpd->regdesc[i].access =
|
Dbg_Access_Readable + Dbg_Access_Writable;
|
Dbg_Access_Readable + Dbg_Access_Writable;
|
}
|
}
|
}
|
}
|
cpd->entries = i + 1;
|
cpd->entries = i + 1;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
|
|
case RDIInfo_Log:
|
case RDIInfo_Log:
|
*arg1 = (ARMword) rdi_log;
|
*arg1 = (ARMword) rdi_log;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDIInfo_SetLog:
|
case RDIInfo_SetLog:
|
rdi_log = (int) *arg1;
|
rdi_log = (int) *arg1;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDIInfo_CoPro:
|
case RDIInfo_CoPro:
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
case RDIPointStatus_Watch:
|
case RDIPointStatus_Watch:
|
{
|
{
|
WatchNode *p, *handle = (WatchNode *) * arg1;
|
WatchNode *p, *handle = (WatchNode *) * arg1;
|
for (p = WatchList; p != NULL; p = p->next)
|
for (p = WatchList; p != NULL; p = p->next)
|
if (p == handle)
|
if (p == handle)
|
{
|
{
|
*arg1 = -1;
|
*arg1 = -1;
|
*arg2 = 1;
|
*arg2 = 1;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
return RDIError_NoSuchPoint;
|
return RDIError_NoSuchPoint;
|
}
|
}
|
|
|
case RDIPointStatus_Break:
|
case RDIPointStatus_Break:
|
{
|
{
|
BreakNode *p, *handle = (BreakNode *) * arg1;
|
BreakNode *p, *handle = (BreakNode *) * arg1;
|
for (p = BreakList; p != NULL; p = p->next)
|
for (p = BreakList; p != NULL; p = p->next)
|
if (p == handle)
|
if (p == handle)
|
{
|
{
|
*arg1 = -1;
|
*arg1 = -1;
|
*arg2 = 1;
|
*arg2 = 1;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
}
|
}
|
return RDIError_NoSuchPoint;
|
return RDIError_NoSuchPoint;
|
}
|
}
|
|
|
case RDISet_RDILevel:
|
case RDISet_RDILevel:
|
if (*arg1 < LOWEST_RDI_LEVEL || *arg1 > HIGHEST_RDI_LEVEL)
|
if (*arg1 < LOWEST_RDI_LEVEL || *arg1 > HIGHEST_RDI_LEVEL)
|
return RDIError_IncompatibleRDILevels;
|
return RDIError_IncompatibleRDILevels;
|
MYrdi_level = *arg1;
|
MYrdi_level = *arg1;
|
return RDIError_NoError;
|
return RDIError_NoError;
|
|
|
default:
|
default:
|
return RDIError_UnimplementedMessage;
|
return RDIError_UnimplementedMessage;
|
|
|
}
|
}
|
}
|
}
|
|
|
/***************************************************************************\
|
/***************************************************************************\
|
* The emulator calls this routine at the beginning of every cycle when the *
|
* The emulator calls this routine at the beginning of every cycle when the *
|
* CallDebug flag is set. The second parameter passed is the address of the *
|
* CallDebug flag is set. The second parameter passed is the address of the *
|
* currently executing instruction (i.e Program Counter - 8), the third *
|
* currently executing instruction (i.e Program Counter - 8), the third *
|
* parameter is the instruction being executed. *
|
* parameter is the instruction being executed. *
|
\***************************************************************************/
|
\***************************************************************************/
|
|
|
ARMword
|
ARMword
|
ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr)
|
ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr)
|
{
|
{
|
|
|
if (state->EndCondition == RDIError_UserInterrupt)
|
if (state->EndCondition == RDIError_UserInterrupt)
|
{
|
{
|
TracePrint ((state, "User interrupt at %.8lx\n", pc));
|
TracePrint ((state, "User interrupt at %.8lx\n", pc));
|
state->CallDebug--;
|
state->CallDebug--;
|
state->Emulate = STOP;
|
state->Emulate = STOP;
|
}
|
}
|
else
|
else
|
{
|
{
|
BreakNode *p = BreakList;
|
BreakNode *p = BreakList;
|
for (; p != NULL; p = p->next)
|
for (; p != NULL; p = p->next)
|
{
|
{
|
switch (p->type)
|
switch (p->type)
|
{
|
{
|
case RDIPoint_EQ:
|
case RDIPoint_EQ:
|
if (pc == p->address)
|
if (pc == p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_GT:
|
case RDIPoint_GT:
|
if (pc > p->address)
|
if (pc > p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_GE:
|
case RDIPoint_GE:
|
if (pc >= p->address)
|
if (pc >= p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_LT:
|
case RDIPoint_LT:
|
if (pc < p->address)
|
if (pc < p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_LE:
|
case RDIPoint_LE:
|
if (pc <= p->address)
|
if (pc <= p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_IN:
|
case RDIPoint_IN:
|
if (p->address <= pc && pc < p->address + p->bound)
|
if (p->address <= pc && pc < p->address + p->bound)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_OUT:
|
case RDIPoint_OUT:
|
if (p->address > pc || pc >= p->address + p->bound)
|
if (p->address > pc || pc >= p->address + p->bound)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_MASK:
|
case RDIPoint_MASK:
|
if ((pc & p->bound) == p->address)
|
if ((pc & p->bound) == p->address)
|
break;
|
break;
|
continue;
|
continue;
|
}
|
}
|
/* found a match */
|
/* found a match */
|
TracePrint ((state, "Breakpoint reached at %.8lx\n", pc));
|
TracePrint ((state, "Breakpoint reached at %.8lx\n", pc));
|
state->EndCondition = RDIError_BreakpointReached;
|
state->EndCondition = RDIError_BreakpointReached;
|
state->Emulate = STOP;
|
state->Emulate = STOP;
|
state->StopHandle = (ARMword) p;
|
state->StopHandle = (ARMword) p;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
return instr;
|
return instr;
|
}
|
}
|
|
|
void
|
void
|
ARMul_CheckWatch (ARMul_State * state, ARMword addr, int access)
|
ARMul_CheckWatch (ARMul_State * state, ARMword addr, int access)
|
{
|
{
|
WatchNode *p;
|
WatchNode *p;
|
for (p = WatchList; p != NULL; p = p->next)
|
for (p = WatchList; p != NULL; p = p->next)
|
if (p->datatype & access)
|
if (p->datatype & access)
|
{
|
{
|
switch (p->type)
|
switch (p->type)
|
{
|
{
|
case RDIPoint_EQ:
|
case RDIPoint_EQ:
|
if (addr == p->address)
|
if (addr == p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_GT:
|
case RDIPoint_GT:
|
if (addr > p->address)
|
if (addr > p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_GE:
|
case RDIPoint_GE:
|
if (addr >= p->address)
|
if (addr >= p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_LT:
|
case RDIPoint_LT:
|
if (addr < p->address)
|
if (addr < p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_LE:
|
case RDIPoint_LE:
|
if (addr <= p->address)
|
if (addr <= p->address)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_IN:
|
case RDIPoint_IN:
|
if (p->address <= addr && addr < p->address + p->bound)
|
if (p->address <= addr && addr < p->address + p->bound)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_OUT:
|
case RDIPoint_OUT:
|
if (p->address > addr || addr >= p->address + p->bound)
|
if (p->address > addr || addr >= p->address + p->bound)
|
break;
|
break;
|
continue;
|
continue;
|
case RDIPoint_MASK:
|
case RDIPoint_MASK:
|
if ((addr & p->bound) == p->address)
|
if ((addr & p->bound) == p->address)
|
break;
|
break;
|
continue;
|
continue;
|
}
|
}
|
/* found a match */
|
/* found a match */
|
TracePrint ((state, "Watchpoint at %.8lx accessed\n", addr));
|
TracePrint ((state, "Watchpoint at %.8lx accessed\n", addr));
|
state->EndCondition = RDIError_WatchpointAccessed;
|
state->EndCondition = RDIError_WatchpointAccessed;
|
state->Emulate = STOP;
|
state->Emulate = STOP;
|
state->StopHandle = (ARMword) p;
|
state->StopHandle = (ARMword) p;
|
return;
|
return;
|
}
|
}
|
}
|
}
|
|
|
static RDI_NameList const *
|
static RDI_NameList const *
|
RDI_cpunames ()
|
RDI_cpunames ()
|
{
|
{
|
return (RDI_NameList const *) &processorconfig.count;
|
return (RDI_NameList const *) &processorconfig.count;
|
}
|
}
|
|
|
const struct RDIProcVec armul_rdi = {
|
const struct RDIProcVec armul_rdi = {
|
"ARMUL",
|
"ARMUL",
|
RDI_open,
|
RDI_open,
|
RDI_close,
|
RDI_close,
|
RDI_read,
|
RDI_read,
|
RDI_write,
|
RDI_write,
|
RDI_CPUread,
|
RDI_CPUread,
|
RDI_CPUwrite,
|
RDI_CPUwrite,
|
RDI_CPread,
|
RDI_CPread,
|
RDI_CPwrite,
|
RDI_CPwrite,
|
RDI_setbreak,
|
RDI_setbreak,
|
RDI_clearbreak,
|
RDI_clearbreak,
|
RDI_setwatch,
|
RDI_setwatch,
|
RDI_clearwatch,
|
RDI_clearwatch,
|
RDI_execute,
|
RDI_execute,
|
RDI_step,
|
RDI_step,
|
RDI_info,
|
RDI_info,
|
|
|
0, /*pointinq */
|
0, /*pointinq */
|
0, /*addconfig */
|
0, /*addconfig */
|
0, /*loadconfigdata */
|
0, /*loadconfigdata */
|
0, /*selectconfig */
|
0, /*selectconfig */
|
0, /*drivernames */
|
0, /*drivernames */
|
|
|
RDI_cpunames
|
RDI_cpunames
|
};
|
};
|
|
|
