/* run front end support for arm
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/* run front end support for arm
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Copyright (C) 1995, 1996, 1997, 2000, 2001, 2002, 2007, 2008
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Copyright (C) 1995, 1996, 1997, 2000, 2001, 2002, 2007, 2008
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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This file is part of ARM SIM.
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This file is part of ARM SIM.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This file provides the interface between the simulator and
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/* This file provides the interface between the simulator and
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run.c and gdb (when the simulator is linked with gdb).
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run.c and gdb (when the simulator is linked with gdb).
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All simulator interaction should go through this file. */
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All simulator interaction should go through this file. */
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#include <stdio.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <stdarg.h>
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#include <string.h>
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#include <string.h>
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#include <bfd.h>
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#include <bfd.h>
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#include <signal.h>
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#include <signal.h>
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#include "gdb/callback.h"
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#include "gdb/callback.h"
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#include "gdb/remote-sim.h"
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#include "gdb/remote-sim.h"
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#include "armdefs.h"
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#include "armdefs.h"
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#include "armemu.h"
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#include "armemu.h"
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#include "dbg_rdi.h"
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#include "dbg_rdi.h"
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#include "ansidecl.h"
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#include "ansidecl.h"
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#include "sim-utils.h"
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#include "sim-utils.h"
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#include "run-sim.h"
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#include "run-sim.h"
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#include "gdb/sim-arm.h"
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#include "gdb/sim-arm.h"
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#include "gdb/signals.h"
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#include "gdb/signals.h"
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host_callback *sim_callback;
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host_callback *sim_callback;
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static struct ARMul_State *state;
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static struct ARMul_State *state;
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/* Who is using the simulator. */
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/* Who is using the simulator. */
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static SIM_OPEN_KIND sim_kind;
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static SIM_OPEN_KIND sim_kind;
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/* argv[0] */
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/* argv[0] */
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static char *myname;
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static char *myname;
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/* Memory size in bytes. */
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/* Memory size in bytes. */
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static int mem_size = (1 << 21);
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static int mem_size = (1 << 21);
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/* Non-zero to display start up banner, and maybe other things. */
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/* Non-zero to display start up banner, and maybe other things. */
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static int verbosity;
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static int verbosity;
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/* Non-zero to set big endian mode. */
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/* Non-zero to set big endian mode. */
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static int big_endian;
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static int big_endian;
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int stop_simulator;
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int stop_simulator;
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/* Cirrus DSP registers.
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/* Cirrus DSP registers.
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We need to define these registers outside of maverick.c because
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We need to define these registers outside of maverick.c because
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maverick.c might not be linked in unless --target=arm9e-* in which
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maverick.c might not be linked in unless --target=arm9e-* in which
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case wrapper.c will not compile because it tries to access Cirrus
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case wrapper.c will not compile because it tries to access Cirrus
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registers. This should all go away once we get the Cirrus and ARM
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registers. This should all go away once we get the Cirrus and ARM
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Coprocessor to coexist in armcopro.c-- aldyh. */
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Coprocessor to coexist in armcopro.c-- aldyh. */
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struct maverick_regs
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struct maverick_regs
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{
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{
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union
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union
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{
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{
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int i;
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int i;
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float f;
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float f;
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} upper;
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} upper;
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union
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union
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{
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{
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int i;
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int i;
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float f;
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float f;
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} lower;
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} lower;
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};
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};
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union maverick_acc_regs
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union maverick_acc_regs
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{
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{
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long double ld; /* Acc registers are 72-bits. */
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long double ld; /* Acc registers are 72-bits. */
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};
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};
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struct maverick_regs DSPregs[16];
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struct maverick_regs DSPregs[16];
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union maverick_acc_regs DSPacc[4];
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union maverick_acc_regs DSPacc[4];
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ARMword DSPsc;
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ARMword DSPsc;
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static void
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static void
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init ()
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init ()
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{
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{
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static int done;
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static int done;
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if (!done)
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if (!done)
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{
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{
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ARMul_EmulateInit ();
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ARMul_EmulateInit ();
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state = ARMul_NewState ();
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state = ARMul_NewState ();
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state->bigendSig = (big_endian ? HIGH : LOW);
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state->bigendSig = (big_endian ? HIGH : LOW);
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ARMul_MemoryInit (state, mem_size);
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ARMul_MemoryInit (state, mem_size);
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ARMul_OSInit (state);
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ARMul_OSInit (state);
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state->verbose = verbosity;
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state->verbose = verbosity;
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done = 1;
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done = 1;
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}
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}
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}
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}
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/* Set verbosity level of simulator.
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/* Set verbosity level of simulator.
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This is not intended to produce detailed tracing or debugging information.
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This is not intended to produce detailed tracing or debugging information.
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Just summaries. */
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Just summaries. */
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/* FIXME: common/run.c doesn't do this yet. */
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/* FIXME: common/run.c doesn't do this yet. */
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void
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void
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sim_set_verbose (v)
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sim_set_verbose (v)
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int v;
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int v;
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{
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{
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verbosity = v;
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verbosity = v;
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}
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}
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/* Set the memory size to SIZE bytes.
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/* Set the memory size to SIZE bytes.
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Must be called before initializing simulator. */
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Must be called before initializing simulator. */
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/* FIXME: Rename to sim_set_mem_size. */
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/* FIXME: Rename to sim_set_mem_size. */
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void
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void
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sim_size (size)
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sim_size (size)
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int size;
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int size;
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{
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{
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mem_size = size;
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mem_size = size;
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}
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}
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void
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void
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ARMul_ConsolePrint VPARAMS ((ARMul_State * state,
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ARMul_ConsolePrint VPARAMS ((ARMul_State * state,
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const char * format,
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const char * format,
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...))
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...))
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{
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{
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va_list ap;
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va_list ap;
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if (state->verbose)
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if (state->verbose)
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{
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{
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va_start (ap, format);
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va_start (ap, format);
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vprintf (format, ap);
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vprintf (format, ap);
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va_end (ap);
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va_end (ap);
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}
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}
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}
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}
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ARMword
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ARMword
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ARMul_Debug (state, pc, instr)
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ARMul_Debug (state, pc, instr)
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ARMul_State * state ATTRIBUTE_UNUSED;
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ARMul_State * state ATTRIBUTE_UNUSED;
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ARMword pc ATTRIBUTE_UNUSED;
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ARMword pc ATTRIBUTE_UNUSED;
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ARMword instr ATTRIBUTE_UNUSED;
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ARMword instr ATTRIBUTE_UNUSED;
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{
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{
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return 0;
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return 0;
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}
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}
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int
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int
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sim_write (sd, addr, buffer, size)
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sim_write (sd, addr, buffer, size)
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SIM_DESC sd ATTRIBUTE_UNUSED;
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SIM_DESC sd ATTRIBUTE_UNUSED;
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SIM_ADDR addr;
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SIM_ADDR addr;
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unsigned char * buffer;
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unsigned char * buffer;
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int size;
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int size;
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{
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{
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int i;
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int i;
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init ();
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init ();
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for (i = 0; i < size; i++)
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for (i = 0; i < size; i++)
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ARMul_SafeWriteByte (state, addr + i, buffer[i]);
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ARMul_SafeWriteByte (state, addr + i, buffer[i]);
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return size;
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return size;
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}
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}
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int
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int
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sim_read (sd, addr, buffer, size)
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sim_read (sd, addr, buffer, size)
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SIM_DESC sd ATTRIBUTE_UNUSED;
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SIM_DESC sd ATTRIBUTE_UNUSED;
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SIM_ADDR addr;
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SIM_ADDR addr;
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unsigned char * buffer;
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unsigned char * buffer;
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int size;
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int size;
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{
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{
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int i;
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int i;
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init ();
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init ();
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for (i = 0; i < size; i++)
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for (i = 0; i < size; i++)
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buffer[i] = ARMul_SafeReadByte (state, addr + i);
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buffer[i] = ARMul_SafeReadByte (state, addr + i);
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return size;
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return size;
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}
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}
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int
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int
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sim_trace (sd)
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sim_trace (sd)
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SIM_DESC sd ATTRIBUTE_UNUSED;
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SIM_DESC sd ATTRIBUTE_UNUSED;
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{
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{
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(*sim_callback->printf_filtered)
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(*sim_callback->printf_filtered)
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(sim_callback,
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(sim_callback,
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"This simulator does not support tracing\n");
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"This simulator does not support tracing\n");
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return 1;
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return 1;
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}
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}
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int
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int
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sim_stop (sd)
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sim_stop (sd)
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SIM_DESC sd ATTRIBUTE_UNUSED;
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SIM_DESC sd ATTRIBUTE_UNUSED;
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{
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{
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state->Emulate = STOP;
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state->Emulate = STOP;
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stop_simulator = 1;
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stop_simulator = 1;
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return 1;
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return 1;
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}
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}
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void
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void
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sim_resume (sd, step, siggnal)
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sim_resume (sd, step, siggnal)
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SIM_DESC sd ATTRIBUTE_UNUSED;
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SIM_DESC sd ATTRIBUTE_UNUSED;
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int step;
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int step;
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int siggnal ATTRIBUTE_UNUSED;
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int siggnal ATTRIBUTE_UNUSED;
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{
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{
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state->EndCondition = 0;
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state->EndCondition = 0;
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stop_simulator = 0;
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stop_simulator = 0;
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if (step)
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if (step)
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{
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{
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state->Reg[15] = ARMul_DoInstr (state);
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state->Reg[15] = ARMul_DoInstr (state);
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if (state->EndCondition == 0)
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if (state->EndCondition == 0)
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state->EndCondition = RDIError_BreakpointReached;
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state->EndCondition = RDIError_BreakpointReached;
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}
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}
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else
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else
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{
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{
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state->NextInstr = RESUME; /* treat as PC change */
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state->NextInstr = RESUME; /* treat as PC change */
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state->Reg[15] = ARMul_DoProg (state);
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state->Reg[15] = ARMul_DoProg (state);
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}
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}
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FLUSHPIPE;
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FLUSHPIPE;
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}
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}
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SIM_RC
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SIM_RC
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sim_create_inferior (sd, abfd, argv, env)
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sim_create_inferior (sd, abfd, argv, env)
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SIM_DESC sd ATTRIBUTE_UNUSED;
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SIM_DESC sd ATTRIBUTE_UNUSED;
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struct bfd * abfd;
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struct bfd * abfd;
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char ** argv;
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char ** argv;
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char ** env;
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char ** env;
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{
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{
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int argvlen = 0;
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int argvlen = 0;
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int mach;
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int mach;
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char **arg;
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char **arg;
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if (abfd != NULL)
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if (abfd != NULL)
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ARMul_SetPC (state, bfd_get_start_address (abfd));
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ARMul_SetPC (state, bfd_get_start_address (abfd));
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else
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else
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ARMul_SetPC (state, 0); /* ??? */
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ARMul_SetPC (state, 0); /* ??? */
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mach = bfd_get_mach (abfd);
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mach = bfd_get_mach (abfd);
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switch (mach)
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switch (mach)
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{
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{
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default:
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default:
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(*sim_callback->printf_filtered)
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(*sim_callback->printf_filtered)
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(sim_callback,
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(sim_callback,
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"Unknown machine type '%d'; please update sim_create_inferior.\n",
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"Unknown machine type '%d'; please update sim_create_inferior.\n",
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mach);
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mach);
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/* fall through */
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/* fall through */
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case 0:
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case 0:
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/* We wouldn't set the machine type with earlier toolchains, so we
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/* We wouldn't set the machine type with earlier toolchains, so we
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explicitly select a processor capable of supporting all ARMs in
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explicitly select a processor capable of supporting all ARMs in
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32bit mode. */
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32bit mode. */
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/* We choose the XScale rather than the iWMMXt, because the iWMMXt
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/* We choose the XScale rather than the iWMMXt, because the iWMMXt
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removes the FPE emulator, since it conflicts with its coprocessors.
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removes the FPE emulator, since it conflicts with its coprocessors.
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For the most generic ARM support, we want the FPE emulator in place. */
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For the most generic ARM support, we want the FPE emulator in place. */
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case bfd_mach_arm_XScale:
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case bfd_mach_arm_XScale:
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
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break;
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break;
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case bfd_mach_arm_iWMMXt:
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case bfd_mach_arm_iWMMXt:
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{
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{
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extern int SWI_vector_installed;
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extern int SWI_vector_installed;
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ARMword i;
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ARMword i;
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if (! SWI_vector_installed)
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if (! SWI_vector_installed)
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{
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{
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/* Intialise the hardware vectors to zero. */
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/* Intialise the hardware vectors to zero. */
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if (! SWI_vector_installed)
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if (! SWI_vector_installed)
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for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
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for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
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ARMul_WriteWord (state, i, 0);
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ARMul_WriteWord (state, i, 0);
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/* ARM_WriteWord will have detected the write to the SWI vector,
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/* ARM_WriteWord will have detected the write to the SWI vector,
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but we want SWI_vector_installed to remain at 0 so that thumb
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but we want SWI_vector_installed to remain at 0 so that thumb
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mode breakpoints will work. */
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mode breakpoints will work. */
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SWI_vector_installed = 0;
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SWI_vector_installed = 0;
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}
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}
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}
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}
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
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break;
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break;
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case bfd_mach_arm_ep9312:
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case bfd_mach_arm_ep9312:
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ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
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ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
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break;
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break;
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case bfd_mach_arm_5:
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case bfd_mach_arm_5:
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if (bfd_family_coff (abfd))
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if (bfd_family_coff (abfd))
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{
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{
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/* This is a special case in order to support COFF based ARM toolchains.
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/* This is a special case in order to support COFF based ARM toolchains.
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The COFF header does not have enough room to store all the different
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The COFF header does not have enough room to store all the different
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kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
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kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
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to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
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to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
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machine type here, we assume it could be any of the above architectures
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machine type here, we assume it could be any of the above architectures
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and so select the most feature-full. */
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and so select the most feature-full. */
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
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break;
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break;
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}
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}
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/* Otherwise drop through. */
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/* Otherwise drop through. */
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|
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case bfd_mach_arm_5T:
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case bfd_mach_arm_5T:
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ARMul_SelectProcessor (state, ARM_v5_Prop);
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ARMul_SelectProcessor (state, ARM_v5_Prop);
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break;
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break;
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|
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case bfd_mach_arm_5TE:
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case bfd_mach_arm_5TE:
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
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break;
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break;
|
|
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case bfd_mach_arm_4:
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case bfd_mach_arm_4:
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case bfd_mach_arm_4T:
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case bfd_mach_arm_4T:
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ARMul_SelectProcessor (state, ARM_v4_Prop);
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ARMul_SelectProcessor (state, ARM_v4_Prop);
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break;
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break;
|
|
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case bfd_mach_arm_3:
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case bfd_mach_arm_3:
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case bfd_mach_arm_3M:
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case bfd_mach_arm_3M:
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ARMul_SelectProcessor (state, ARM_Lock_Prop);
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ARMul_SelectProcessor (state, ARM_Lock_Prop);
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break;
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break;
|
|
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case bfd_mach_arm_2:
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case bfd_mach_arm_2:
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case bfd_mach_arm_2a:
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case bfd_mach_arm_2a:
|
ARMul_SelectProcessor (state, ARM_Fix26_Prop);
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ARMul_SelectProcessor (state, ARM_Fix26_Prop);
|
break;
|
break;
|
}
|
}
|
|
|
if ( mach != bfd_mach_arm_3
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if ( mach != bfd_mach_arm_3
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&& mach != bfd_mach_arm_3M
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&& mach != bfd_mach_arm_3M
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&& mach != bfd_mach_arm_2
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&& mach != bfd_mach_arm_2
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&& mach != bfd_mach_arm_2a)
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&& mach != bfd_mach_arm_2a)
|
{
|
{
|
/* Reset mode to ARM. A gdb user may rerun a program that had entered
|
/* Reset mode to ARM. A gdb user may rerun a program that had entered
|
THUMB mode from the start and cause the ARM-mode startup code to be
|
THUMB mode from the start and cause the ARM-mode startup code to be
|
executed in THUMB mode. */
|
executed in THUMB mode. */
|
ARMul_SetCPSR (state, SVC32MODE);
|
ARMul_SetCPSR (state, SVC32MODE);
|
}
|
}
|
|
|
if (argv != NULL)
|
if (argv != NULL)
|
{
|
{
|
/* Set up the command line by laboriously stringing together
|
/* Set up the command line by laboriously stringing together
|
the environment carefully picked apart by our caller. */
|
the environment carefully picked apart by our caller. */
|
|
|
/* Free any old stuff. */
|
/* Free any old stuff. */
|
if (state->CommandLine != NULL)
|
if (state->CommandLine != NULL)
|
{
|
{
|
free (state->CommandLine);
|
free (state->CommandLine);
|
state->CommandLine = NULL;
|
state->CommandLine = NULL;
|
}
|
}
|
|
|
/* See how much we need. */
|
/* See how much we need. */
|
for (arg = argv; *arg != NULL; arg++)
|
for (arg = argv; *arg != NULL; arg++)
|
argvlen += strlen (*arg) + 1;
|
argvlen += strlen (*arg) + 1;
|
|
|
/* Allocate it. */
|
/* Allocate it. */
|
state->CommandLine = malloc (argvlen + 1);
|
state->CommandLine = malloc (argvlen + 1);
|
if (state->CommandLine != NULL)
|
if (state->CommandLine != NULL)
|
{
|
{
|
arg = argv;
|
arg = argv;
|
state->CommandLine[0] = '\0';
|
state->CommandLine[0] = '\0';
|
|
|
for (arg = argv; *arg != NULL; arg++)
|
for (arg = argv; *arg != NULL; arg++)
|
{
|
{
|
strcat (state->CommandLine, *arg);
|
strcat (state->CommandLine, *arg);
|
strcat (state->CommandLine, " ");
|
strcat (state->CommandLine, " ");
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
if (env != NULL)
|
if (env != NULL)
|
{
|
{
|
/* Now see if there's a MEMSIZE spec in the environment. */
|
/* Now see if there's a MEMSIZE spec in the environment. */
|
while (*env)
|
while (*env)
|
{
|
{
|
if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
|
if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
|
{
|
{
|
char *end_of_num;
|
char *end_of_num;
|
|
|
/* Set up memory limit. */
|
/* Set up memory limit. */
|
state->MemSize =
|
state->MemSize =
|
strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
|
strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
|
}
|
}
|
env++;
|
env++;
|
}
|
}
|
}
|
}
|
|
|
return SIM_RC_OK;
|
return SIM_RC_OK;
|
}
|
}
|
|
|
void
|
void
|
sim_info (sd, verbose)
|
sim_info (sd, verbose)
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
int verbose ATTRIBUTE_UNUSED;
|
int verbose ATTRIBUTE_UNUSED;
|
{
|
{
|
}
|
}
|
|
|
static int
|
static int
|
frommem (state, memory)
|
frommem (state, memory)
|
struct ARMul_State *state;
|
struct ARMul_State *state;
|
unsigned char *memory;
|
unsigned char *memory;
|
{
|
{
|
if (state->bigendSig == HIGH)
|
if (state->bigendSig == HIGH)
|
return (memory[0] << 24) | (memory[1] << 16)
|
return (memory[0] << 24) | (memory[1] << 16)
|
| (memory[2] << 8) | (memory[3] << 0);
|
| (memory[2] << 8) | (memory[3] << 0);
|
else
|
else
|
return (memory[3] << 24) | (memory[2] << 16)
|
return (memory[3] << 24) | (memory[2] << 16)
|
| (memory[1] << 8) | (memory[0] << 0);
|
| (memory[1] << 8) | (memory[0] << 0);
|
}
|
}
|
|
|
static void
|
static void
|
tomem (state, memory, val)
|
tomem (state, memory, val)
|
struct ARMul_State *state;
|
struct ARMul_State *state;
|
unsigned char *memory;
|
unsigned char *memory;
|
int val;
|
int val;
|
{
|
{
|
if (state->bigendSig == HIGH)
|
if (state->bigendSig == HIGH)
|
{
|
{
|
memory[0] = val >> 24;
|
memory[0] = val >> 24;
|
memory[1] = val >> 16;
|
memory[1] = val >> 16;
|
memory[2] = val >> 8;
|
memory[2] = val >> 8;
|
memory[3] = val >> 0;
|
memory[3] = val >> 0;
|
}
|
}
|
else
|
else
|
{
|
{
|
memory[3] = val >> 24;
|
memory[3] = val >> 24;
|
memory[2] = val >> 16;
|
memory[2] = val >> 16;
|
memory[1] = val >> 8;
|
memory[1] = val >> 8;
|
memory[0] = val >> 0;
|
memory[0] = val >> 0;
|
}
|
}
|
}
|
}
|
|
|
int
|
int
|
sim_store_register (sd, rn, memory, length)
|
sim_store_register (sd, rn, memory, length)
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
int rn;
|
int rn;
|
unsigned char *memory;
|
unsigned char *memory;
|
int length ATTRIBUTE_UNUSED;
|
int length ATTRIBUTE_UNUSED;
|
{
|
{
|
init ();
|
init ();
|
|
|
switch ((enum sim_arm_regs) rn)
|
switch ((enum sim_arm_regs) rn)
|
{
|
{
|
case SIM_ARM_R0_REGNUM:
|
case SIM_ARM_R0_REGNUM:
|
case SIM_ARM_R1_REGNUM:
|
case SIM_ARM_R1_REGNUM:
|
case SIM_ARM_R2_REGNUM:
|
case SIM_ARM_R2_REGNUM:
|
case SIM_ARM_R3_REGNUM:
|
case SIM_ARM_R3_REGNUM:
|
case SIM_ARM_R4_REGNUM:
|
case SIM_ARM_R4_REGNUM:
|
case SIM_ARM_R5_REGNUM:
|
case SIM_ARM_R5_REGNUM:
|
case SIM_ARM_R6_REGNUM:
|
case SIM_ARM_R6_REGNUM:
|
case SIM_ARM_R7_REGNUM:
|
case SIM_ARM_R7_REGNUM:
|
case SIM_ARM_R8_REGNUM:
|
case SIM_ARM_R8_REGNUM:
|
case SIM_ARM_R9_REGNUM:
|
case SIM_ARM_R9_REGNUM:
|
case SIM_ARM_R10_REGNUM:
|
case SIM_ARM_R10_REGNUM:
|
case SIM_ARM_R11_REGNUM:
|
case SIM_ARM_R11_REGNUM:
|
case SIM_ARM_R12_REGNUM:
|
case SIM_ARM_R12_REGNUM:
|
case SIM_ARM_R13_REGNUM:
|
case SIM_ARM_R13_REGNUM:
|
case SIM_ARM_R14_REGNUM:
|
case SIM_ARM_R14_REGNUM:
|
case SIM_ARM_R15_REGNUM: /* PC */
|
case SIM_ARM_R15_REGNUM: /* PC */
|
case SIM_ARM_FP0_REGNUM:
|
case SIM_ARM_FP0_REGNUM:
|
case SIM_ARM_FP1_REGNUM:
|
case SIM_ARM_FP1_REGNUM:
|
case SIM_ARM_FP2_REGNUM:
|
case SIM_ARM_FP2_REGNUM:
|
case SIM_ARM_FP3_REGNUM:
|
case SIM_ARM_FP3_REGNUM:
|
case SIM_ARM_FP4_REGNUM:
|
case SIM_ARM_FP4_REGNUM:
|
case SIM_ARM_FP5_REGNUM:
|
case SIM_ARM_FP5_REGNUM:
|
case SIM_ARM_FP6_REGNUM:
|
case SIM_ARM_FP6_REGNUM:
|
case SIM_ARM_FP7_REGNUM:
|
case SIM_ARM_FP7_REGNUM:
|
case SIM_ARM_FPS_REGNUM:
|
case SIM_ARM_FPS_REGNUM:
|
ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
|
ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
|
break;
|
break;
|
|
|
case SIM_ARM_PS_REGNUM:
|
case SIM_ARM_PS_REGNUM:
|
state->Cpsr = frommem (state, memory);
|
state->Cpsr = frommem (state, memory);
|
ARMul_CPSRAltered (state);
|
ARMul_CPSRAltered (state);
|
break;
|
break;
|
|
|
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
|
memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
|
memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
|
memory, sizeof (struct maverick_regs));
|
memory, sizeof (struct maverick_regs));
|
return sizeof (struct maverick_regs);
|
return sizeof (struct maverick_regs);
|
|
|
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
|
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
|
memcpy (&DSPsc, memory, sizeof DSPsc);
|
memcpy (&DSPsc, memory, sizeof DSPsc);
|
return sizeof DSPsc;
|
return sizeof DSPsc;
|
|
|
case SIM_ARM_IWMMXT_COP0R0_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R0_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R1_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R1_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R2_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R2_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R3_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R3_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R4_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R4_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R5_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R5_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R6_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R6_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R7_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R7_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R8_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R8_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R9_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R9_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R10_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R10_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R11_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R11_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R12_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R12_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R13_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R13_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R14_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R14_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R15_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R15_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R0_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R0_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R1_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R1_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R2_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R2_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R3_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R3_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R4_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R4_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R5_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R5_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R6_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R6_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R7_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R7_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R8_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R8_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R9_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R9_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R10_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R10_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R11_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R11_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R12_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R12_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R13_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R13_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R14_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R14_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R15_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R15_REGNUM:
|
return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
|
return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
|
|
|
default:
|
default:
|
return 0;
|
return 0;
|
}
|
}
|
|
|
return -1;
|
return -1;
|
}
|
}
|
|
|
int
|
int
|
sim_fetch_register (sd, rn, memory, length)
|
sim_fetch_register (sd, rn, memory, length)
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
int rn;
|
int rn;
|
unsigned char *memory;
|
unsigned char *memory;
|
int length ATTRIBUTE_UNUSED;
|
int length ATTRIBUTE_UNUSED;
|
{
|
{
|
ARMword regval;
|
ARMword regval;
|
|
|
init ();
|
init ();
|
|
|
switch ((enum sim_arm_regs) rn)
|
switch ((enum sim_arm_regs) rn)
|
{
|
{
|
case SIM_ARM_R0_REGNUM:
|
case SIM_ARM_R0_REGNUM:
|
case SIM_ARM_R1_REGNUM:
|
case SIM_ARM_R1_REGNUM:
|
case SIM_ARM_R2_REGNUM:
|
case SIM_ARM_R2_REGNUM:
|
case SIM_ARM_R3_REGNUM:
|
case SIM_ARM_R3_REGNUM:
|
case SIM_ARM_R4_REGNUM:
|
case SIM_ARM_R4_REGNUM:
|
case SIM_ARM_R5_REGNUM:
|
case SIM_ARM_R5_REGNUM:
|
case SIM_ARM_R6_REGNUM:
|
case SIM_ARM_R6_REGNUM:
|
case SIM_ARM_R7_REGNUM:
|
case SIM_ARM_R7_REGNUM:
|
case SIM_ARM_R8_REGNUM:
|
case SIM_ARM_R8_REGNUM:
|
case SIM_ARM_R9_REGNUM:
|
case SIM_ARM_R9_REGNUM:
|
case SIM_ARM_R10_REGNUM:
|
case SIM_ARM_R10_REGNUM:
|
case SIM_ARM_R11_REGNUM:
|
case SIM_ARM_R11_REGNUM:
|
case SIM_ARM_R12_REGNUM:
|
case SIM_ARM_R12_REGNUM:
|
case SIM_ARM_R13_REGNUM:
|
case SIM_ARM_R13_REGNUM:
|
case SIM_ARM_R14_REGNUM:
|
case SIM_ARM_R14_REGNUM:
|
case SIM_ARM_R15_REGNUM: /* PC */
|
case SIM_ARM_R15_REGNUM: /* PC */
|
regval = ARMul_GetReg (state, state->Mode, rn);
|
regval = ARMul_GetReg (state, state->Mode, rn);
|
break;
|
break;
|
|
|
case SIM_ARM_FP0_REGNUM:
|
case SIM_ARM_FP0_REGNUM:
|
case SIM_ARM_FP1_REGNUM:
|
case SIM_ARM_FP1_REGNUM:
|
case SIM_ARM_FP2_REGNUM:
|
case SIM_ARM_FP2_REGNUM:
|
case SIM_ARM_FP3_REGNUM:
|
case SIM_ARM_FP3_REGNUM:
|
case SIM_ARM_FP4_REGNUM:
|
case SIM_ARM_FP4_REGNUM:
|
case SIM_ARM_FP5_REGNUM:
|
case SIM_ARM_FP5_REGNUM:
|
case SIM_ARM_FP6_REGNUM:
|
case SIM_ARM_FP6_REGNUM:
|
case SIM_ARM_FP7_REGNUM:
|
case SIM_ARM_FP7_REGNUM:
|
case SIM_ARM_FPS_REGNUM:
|
case SIM_ARM_FPS_REGNUM:
|
memset (memory, 0, length);
|
memset (memory, 0, length);
|
return 0;
|
return 0;
|
|
|
case SIM_ARM_PS_REGNUM:
|
case SIM_ARM_PS_REGNUM:
|
regval = ARMul_GetCPSR (state);
|
regval = ARMul_GetCPSR (state);
|
break;
|
break;
|
|
|
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
|
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
|
memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
|
memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
|
sizeof (struct maverick_regs));
|
sizeof (struct maverick_regs));
|
return sizeof (struct maverick_regs);
|
return sizeof (struct maverick_regs);
|
|
|
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
|
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
|
memcpy (memory, & DSPsc, sizeof DSPsc);
|
memcpy (memory, & DSPsc, sizeof DSPsc);
|
return sizeof DSPsc;
|
return sizeof DSPsc;
|
|
|
case SIM_ARM_IWMMXT_COP0R0_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R0_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R1_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R1_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R2_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R2_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R3_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R3_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R4_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R4_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R5_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R5_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R6_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R6_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R7_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R7_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R8_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R8_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R9_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R9_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R10_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R10_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R11_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R11_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R12_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R12_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R13_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R13_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R14_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R14_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R15_REGNUM:
|
case SIM_ARM_IWMMXT_COP0R15_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R0_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R0_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R1_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R1_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R2_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R2_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R3_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R3_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R4_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R4_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R5_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R5_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R6_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R6_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R7_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R7_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R8_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R8_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R9_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R9_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R10_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R10_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R11_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R11_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R12_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R12_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R13_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R13_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R14_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R14_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R15_REGNUM:
|
case SIM_ARM_IWMMXT_COP1R15_REGNUM:
|
return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
|
return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
|
|
|
default:
|
default:
|
return 0;
|
return 0;
|
}
|
}
|
|
|
while (length)
|
while (length)
|
{
|
{
|
tomem (state, memory, regval);
|
tomem (state, memory, regval);
|
|
|
length -= 4;
|
length -= 4;
|
memory += 4;
|
memory += 4;
|
regval = 0;
|
regval = 0;
|
}
|
}
|
|
|
return -1;
|
return -1;
|
}
|
}
|
|
|
#ifdef SIM_TARGET_SWITCHES
|
#ifdef SIM_TARGET_SWITCHES
|
|
|
static void sim_target_parse_arg_array PARAMS ((char **));
|
static void sim_target_parse_arg_array PARAMS ((char **));
|
|
|
typedef struct
|
typedef struct
|
{
|
{
|
char * swi_option;
|
char * swi_option;
|
unsigned int swi_mask;
|
unsigned int swi_mask;
|
} swi_options;
|
} swi_options;
|
|
|
#define SWI_SWITCH "--swi-support"
|
#define SWI_SWITCH "--swi-support"
|
|
|
static swi_options options[] =
|
static swi_options options[] =
|
{
|
{
|
{ "none", 0 },
|
{ "none", 0 },
|
{ "demon", SWI_MASK_DEMON },
|
{ "demon", SWI_MASK_DEMON },
|
{ "angel", SWI_MASK_ANGEL },
|
{ "angel", SWI_MASK_ANGEL },
|
{ "redboot", SWI_MASK_REDBOOT },
|
{ "redboot", SWI_MASK_REDBOOT },
|
{ "all", -1 },
|
{ "all", -1 },
|
{ "NONE", 0 },
|
{ "NONE", 0 },
|
{ "DEMON", SWI_MASK_DEMON },
|
{ "DEMON", SWI_MASK_DEMON },
|
{ "ANGEL", SWI_MASK_ANGEL },
|
{ "ANGEL", SWI_MASK_ANGEL },
|
{ "REDBOOT", SWI_MASK_REDBOOT },
|
{ "REDBOOT", SWI_MASK_REDBOOT },
|
{ "ALL", -1 }
|
{ "ALL", -1 }
|
};
|
};
|
|
|
|
|
int
|
int
|
sim_target_parse_command_line (argc, argv)
|
sim_target_parse_command_line (argc, argv)
|
int argc;
|
int argc;
|
char ** argv;
|
char ** argv;
|
{
|
{
|
int i;
|
int i;
|
|
|
for (i = 1; i < argc; i++)
|
for (i = 1; i < argc; i++)
|
{
|
{
|
char * ptr = argv[i];
|
char * ptr = argv[i];
|
int arg;
|
int arg;
|
|
|
if ((ptr == NULL) || (* ptr != '-'))
|
if ((ptr == NULL) || (* ptr != '-'))
|
break;
|
break;
|
|
|
if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
|
if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
|
continue;
|
continue;
|
|
|
if (ptr[sizeof SWI_SWITCH - 1] == 0)
|
if (ptr[sizeof SWI_SWITCH - 1] == 0)
|
{
|
{
|
/* Remove this option from the argv array. */
|
/* Remove this option from the argv array. */
|
for (arg = i; arg < argc; arg ++)
|
for (arg = i; arg < argc; arg ++)
|
argv[arg] = argv[arg + 1];
|
argv[arg] = argv[arg + 1];
|
argc --;
|
argc --;
|
|
|
ptr = argv[i];
|
ptr = argv[i];
|
}
|
}
|
else
|
else
|
ptr += sizeof SWI_SWITCH;
|
ptr += sizeof SWI_SWITCH;
|
|
|
swi_mask = 0;
|
swi_mask = 0;
|
|
|
while (* ptr)
|
while (* ptr)
|
{
|
{
|
int i;
|
int i;
|
|
|
for (i = sizeof options / sizeof options[0]; i--;)
|
for (i = sizeof options / sizeof options[0]; i--;)
|
if (strncmp (ptr, options[i].swi_option,
|
if (strncmp (ptr, options[i].swi_option,
|
strlen (options[i].swi_option)) == 0)
|
strlen (options[i].swi_option)) == 0)
|
{
|
{
|
swi_mask |= options[i].swi_mask;
|
swi_mask |= options[i].swi_mask;
|
ptr += strlen (options[i].swi_option);
|
ptr += strlen (options[i].swi_option);
|
|
|
if (* ptr == ',')
|
if (* ptr == ',')
|
++ ptr;
|
++ ptr;
|
|
|
break;
|
break;
|
}
|
}
|
|
|
if (i < 0)
|
if (i < 0)
|
break;
|
break;
|
}
|
}
|
|
|
if (* ptr != 0)
|
if (* ptr != 0)
|
fprintf (stderr, "Ignoring swi options: %s\n", ptr);
|
fprintf (stderr, "Ignoring swi options: %s\n", ptr);
|
|
|
/* Remove this option from the argv array. */
|
/* Remove this option from the argv array. */
|
for (arg = i; arg < argc; arg ++)
|
for (arg = i; arg < argc; arg ++)
|
argv[arg] = argv[arg + 1];
|
argv[arg] = argv[arg + 1];
|
argc --;
|
argc --;
|
i --;
|
i --;
|
}
|
}
|
return argc;
|
return argc;
|
}
|
}
|
|
|
static void
|
static void
|
sim_target_parse_arg_array (argv)
|
sim_target_parse_arg_array (argv)
|
char ** argv;
|
char ** argv;
|
{
|
{
|
int i;
|
int i;
|
|
|
for (i = 0; argv[i]; i++)
|
for (i = 0; argv[i]; i++)
|
;
|
;
|
|
|
sim_target_parse_command_line (i, argv);
|
sim_target_parse_command_line (i, argv);
|
}
|
}
|
|
|
void
|
void
|
sim_target_display_usage ()
|
sim_target_display_usage ()
|
{
|
{
|
fprintf (stderr, "%s=<list> Comma seperated list of SWI protocols to supoport.\n\
|
fprintf (stderr, "%s=<list> Comma seperated list of SWI protocols to supoport.\n\
|
This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n",
|
This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n",
|
SWI_SWITCH);
|
SWI_SWITCH);
|
}
|
}
|
#endif
|
#endif
|
|
|
SIM_DESC
|
SIM_DESC
|
sim_open (kind, ptr, abfd, argv)
|
sim_open (kind, ptr, abfd, argv)
|
SIM_OPEN_KIND kind;
|
SIM_OPEN_KIND kind;
|
host_callback *ptr;
|
host_callback *ptr;
|
struct bfd *abfd;
|
struct bfd *abfd;
|
char **argv;
|
char **argv;
|
{
|
{
|
sim_kind = kind;
|
sim_kind = kind;
|
if (myname) free (myname);
|
if (myname) free (myname);
|
myname = (char *) xstrdup (argv[0]);
|
myname = (char *) xstrdup (argv[0]);
|
sim_callback = ptr;
|
sim_callback = ptr;
|
|
|
#ifdef SIM_TARGET_SWITCHES
|
#ifdef SIM_TARGET_SWITCHES
|
sim_target_parse_arg_array (argv);
|
sim_target_parse_arg_array (argv);
|
#endif
|
#endif
|
|
|
/* Decide upon the endian-ness of the processor.
|
/* Decide upon the endian-ness of the processor.
|
If we can, get the information from the bfd itself.
|
If we can, get the information from the bfd itself.
|
Otherwise look to see if we have been given a command
|
Otherwise look to see if we have been given a command
|
line switch that tells us. Otherwise default to little endian. */
|
line switch that tells us. Otherwise default to little endian. */
|
if (abfd != NULL)
|
if (abfd != NULL)
|
big_endian = bfd_big_endian (abfd);
|
big_endian = bfd_big_endian (abfd);
|
else if (argv[1] != NULL)
|
else if (argv[1] != NULL)
|
{
|
{
|
int i;
|
int i;
|
|
|
/* Scan for endian-ness and memory-size switches. */
|
/* Scan for endian-ness and memory-size switches. */
|
for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
|
for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
|
if (argv[i][0] == '-' && argv[i][1] == 'E')
|
if (argv[i][0] == '-' && argv[i][1] == 'E')
|
{
|
{
|
char c;
|
char c;
|
|
|
if ((c = argv[i][2]) == 0)
|
if ((c = argv[i][2]) == 0)
|
{
|
{
|
++i;
|
++i;
|
c = argv[i][0];
|
c = argv[i][0];
|
}
|
}
|
|
|
switch (c)
|
switch (c)
|
{
|
{
|
case 0:
|
case 0:
|
sim_callback->printf_filtered
|
sim_callback->printf_filtered
|
(sim_callback, "No argument to -E option provided\n");
|
(sim_callback, "No argument to -E option provided\n");
|
break;
|
break;
|
|
|
case 'b':
|
case 'b':
|
case 'B':
|
case 'B':
|
big_endian = 1;
|
big_endian = 1;
|
break;
|
break;
|
|
|
case 'l':
|
case 'l':
|
case 'L':
|
case 'L':
|
big_endian = 0;
|
big_endian = 0;
|
break;
|
break;
|
|
|
default:
|
default:
|
sim_callback->printf_filtered
|
sim_callback->printf_filtered
|
(sim_callback, "Unrecognised argument to -E option\n");
|
(sim_callback, "Unrecognised argument to -E option\n");
|
break;
|
break;
|
}
|
}
|
}
|
}
|
else if (argv[i][0] == '-' && argv[i][1] == 'm')
|
else if (argv[i][0] == '-' && argv[i][1] == 'm')
|
{
|
{
|
if (argv[i][2] != '\0')
|
if (argv[i][2] != '\0')
|
sim_size (atoi (&argv[i][2]));
|
sim_size (atoi (&argv[i][2]));
|
else if (argv[i + 1] != NULL)
|
else if (argv[i + 1] != NULL)
|
{
|
{
|
sim_size (atoi (argv[i + 1]));
|
sim_size (atoi (argv[i + 1]));
|
i++;
|
i++;
|
}
|
}
|
else
|
else
|
{
|
{
|
sim_callback->printf_filtered (sim_callback,
|
sim_callback->printf_filtered (sim_callback,
|
"Missing argument to -m option\n");
|
"Missing argument to -m option\n");
|
return NULL;
|
return NULL;
|
}
|
}
|
|
|
}
|
}
|
}
|
}
|
|
|
return (SIM_DESC) 1;
|
return (SIM_DESC) 1;
|
}
|
}
|
|
|
void
|
void
|
sim_close (sd, quitting)
|
sim_close (sd, quitting)
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
int quitting ATTRIBUTE_UNUSED;
|
int quitting ATTRIBUTE_UNUSED;
|
{
|
{
|
if (myname)
|
if (myname)
|
free (myname);
|
free (myname);
|
myname = NULL;
|
myname = NULL;
|
}
|
}
|
|
|
SIM_RC
|
SIM_RC
|
sim_load (sd, prog, abfd, from_tty)
|
sim_load (sd, prog, abfd, from_tty)
|
SIM_DESC sd;
|
SIM_DESC sd;
|
char *prog;
|
char *prog;
|
bfd *abfd;
|
bfd *abfd;
|
int from_tty ATTRIBUTE_UNUSED;
|
int from_tty ATTRIBUTE_UNUSED;
|
{
|
{
|
bfd *prog_bfd;
|
bfd *prog_bfd;
|
|
|
prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd,
|
prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd,
|
sim_kind == SIM_OPEN_DEBUG, 0, sim_write);
|
sim_kind == SIM_OPEN_DEBUG, 0, sim_write);
|
if (prog_bfd == NULL)
|
if (prog_bfd == NULL)
|
return SIM_RC_FAIL;
|
return SIM_RC_FAIL;
|
ARMul_SetPC (state, bfd_get_start_address (prog_bfd));
|
ARMul_SetPC (state, bfd_get_start_address (prog_bfd));
|
if (abfd == NULL)
|
if (abfd == NULL)
|
bfd_close (prog_bfd);
|
bfd_close (prog_bfd);
|
return SIM_RC_OK;
|
return SIM_RC_OK;
|
}
|
}
|
|
|
void
|
void
|
sim_stop_reason (sd, reason, sigrc)
|
sim_stop_reason (sd, reason, sigrc)
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
enum sim_stop *reason;
|
enum sim_stop *reason;
|
int *sigrc;
|
int *sigrc;
|
{
|
{
|
if (stop_simulator)
|
if (stop_simulator)
|
{
|
{
|
*reason = sim_stopped;
|
*reason = sim_stopped;
|
*sigrc = TARGET_SIGNAL_INT;
|
*sigrc = TARGET_SIGNAL_INT;
|
}
|
}
|
else if (state->EndCondition == 0)
|
else if (state->EndCondition == 0)
|
{
|
{
|
*reason = sim_exited;
|
*reason = sim_exited;
|
*sigrc = state->Reg[0] & 255;
|
*sigrc = state->Reg[0] & 255;
|
}
|
}
|
else
|
else
|
{
|
{
|
*reason = sim_stopped;
|
*reason = sim_stopped;
|
if (state->EndCondition == RDIError_BreakpointReached)
|
if (state->EndCondition == RDIError_BreakpointReached)
|
*sigrc = TARGET_SIGNAL_TRAP;
|
*sigrc = TARGET_SIGNAL_TRAP;
|
else if ( state->EndCondition == RDIError_DataAbort
|
else if ( state->EndCondition == RDIError_DataAbort
|
|| state->EndCondition == RDIError_AddressException)
|
|| state->EndCondition == RDIError_AddressException)
|
*sigrc = TARGET_SIGNAL_BUS;
|
*sigrc = TARGET_SIGNAL_BUS;
|
else
|
else
|
*sigrc = 0;
|
*sigrc = 0;
|
}
|
}
|
}
|
}
|
|
|
void
|
void
|
sim_do_command (sd, cmd)
|
sim_do_command (sd, cmd)
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
SIM_DESC sd ATTRIBUTE_UNUSED;
|
char *cmd ATTRIBUTE_UNUSED;
|
char *cmd ATTRIBUTE_UNUSED;
|
{
|
{
|
(*sim_callback->printf_filtered)
|
(*sim_callback->printf_filtered)
|
(sim_callback,
|
(sim_callback,
|
"This simulator does not accept any commands.\n");
|
"This simulator does not accept any commands.\n");
|
}
|
}
|
|
|
void
|
void
|
sim_set_callbacks (ptr)
|
sim_set_callbacks (ptr)
|
host_callback *ptr;
|
host_callback *ptr;
|
{
|
{
|
sim_callback = ptr;
|
sim_callback = ptr;
|
}
|
}
|
|
|
