OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [m32c/] [load.c] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
/* load.c --- loading object files into the M32C simulator.
/* load.c --- loading object files into the M32C simulator.
 
 
Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
Contributed by Red Hat, Inc.
 
 
This file is part of the GNU simulators.
This file is part of the GNU simulators.
 
 
This program is free software; you can redistribute it and/or modify
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
(at your option) any later version.
 
 
This program is distributed in the hope that it will be useful,
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
GNU General Public License for more details.
 
 
You should have received a copy of the GNU General Public License
You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 
 
 
#include <stdlib.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdio.h>
#include <string.h>
#include <string.h>
 
 
#include "bfd.h"
#include "bfd.h"
 
 
#include "cpu.h"
#include "cpu.h"
#include "mem.h"
#include "mem.h"
 
 
int (*decode_opcode) () = 0;
int (*decode_opcode) () = 0;
int default_machine = 0;
int default_machine = 0;
 
 
void
void
m32c_set_mach (unsigned long mach)
m32c_set_mach (unsigned long mach)
{
{
  switch (mach)
  switch (mach)
    {
    {
    case bfd_mach_m16c:
    case bfd_mach_m16c:
      m32c_set_cpu (CPU_M16C);
      m32c_set_cpu (CPU_M16C);
      if (verbose)
      if (verbose)
        fprintf (stderr, "[cpu: r8c/m16c]\n");
        fprintf (stderr, "[cpu: r8c/m16c]\n");
      break;
      break;
    case bfd_mach_m32c:
    case bfd_mach_m32c:
      m32c_set_cpu (CPU_M32C);
      m32c_set_cpu (CPU_M32C);
      if (verbose)
      if (verbose)
        fprintf (stderr, "[cpu: m32cm/m32c]\n");
        fprintf (stderr, "[cpu: m32cm/m32c]\n");
      break;
      break;
    default:
    default:
      fprintf (stderr, "unknown m32c machine type 0x%lx\n", mach);
      fprintf (stderr, "unknown m32c machine type 0x%lx\n", mach);
      decode_opcode = 0;
      decode_opcode = 0;
      break;
      break;
    }
    }
}
}
 
 
void
void
m32c_load (bfd *prog)
m32c_load (bfd *prog)
{
{
  asection *s;
  asection *s;
  unsigned long mach = bfd_get_mach (prog);
  unsigned long mach = bfd_get_mach (prog);
  unsigned long highest_addr_loaded = 0;
  unsigned long highest_addr_loaded = 0;
 
 
  if (mach == 0 && default_machine != 0)
  if (mach == 0 && default_machine != 0)
    mach = default_machine;
    mach = default_machine;
 
 
  m32c_set_mach (mach);
  m32c_set_mach (mach);
 
 
  for (s = prog->sections; s; s = s->next)
  for (s = prog->sections; s; s = s->next)
    {
    {
#if 0
#if 0
      /* This was a good idea until we started storing the RAM data in
      /* This was a good idea until we started storing the RAM data in
         ROM, at which point everything was all messed up.  The code
         ROM, at which point everything was all messed up.  The code
         remains as a reminder.  */
         remains as a reminder.  */
      if ((s->flags & SEC_ALLOC) && !(s->flags & SEC_READONLY))
      if ((s->flags & SEC_ALLOC) && !(s->flags & SEC_READONLY))
        {
        {
          if (strcmp (bfd_get_section_name (prog, s), ".stack"))
          if (strcmp (bfd_get_section_name (prog, s), ".stack"))
            {
            {
              int secend =
              int secend =
                bfd_get_section_size (s) + bfd_section_lma (prog, s);
                bfd_get_section_size (s) + bfd_section_lma (prog, s);
              if (heaptop < secend && bfd_section_lma (prog, s) < 0x10000)
              if (heaptop < secend && bfd_section_lma (prog, s) < 0x10000)
                {
                {
                  heaptop = heapbottom = secend;
                  heaptop = heapbottom = secend;
                }
                }
            }
            }
        }
        }
#endif
#endif
      if (s->flags & SEC_LOAD)
      if (s->flags & SEC_LOAD)
        {
        {
          char *buf;
          char *buf;
          bfd_size_type size;
          bfd_size_type size;
 
 
          size = bfd_get_section_size (s);
          size = bfd_get_section_size (s);
          if (size <= 0)
          if (size <= 0)
            continue;
            continue;
 
 
          bfd_vma base = bfd_section_lma (prog, s);
          bfd_vma base = bfd_section_lma (prog, s);
          if (verbose)
          if (verbose)
            fprintf (stderr, "[load a=%08x s=%08x %s]\n",
            fprintf (stderr, "[load a=%08x s=%08x %s]\n",
                     (int) base, (int) size, bfd_get_section_name (prog, s));
                     (int) base, (int) size, bfd_get_section_name (prog, s));
          buf = (char *) malloc (size);
          buf = (char *) malloc (size);
          bfd_get_section_contents (prog, s, buf, 0, size);
          bfd_get_section_contents (prog, s, buf, 0, size);
          mem_put_blk (base, buf, size);
          mem_put_blk (base, buf, size);
          free (buf);
          free (buf);
          if (highest_addr_loaded < base + size - 1 && size >= 4)
          if (highest_addr_loaded < base + size - 1 && size >= 4)
            highest_addr_loaded = base + size - 1;
            highest_addr_loaded = base + size - 1;
        }
        }
    }
    }
 
 
  if (strcmp (bfd_get_target (prog), "srec") == 0)
  if (strcmp (bfd_get_target (prog), "srec") == 0)
    {
    {
      heaptop = heapbottom = 0;
      heaptop = heapbottom = 0;
      switch (mach)
      switch (mach)
        {
        {
        case bfd_mach_m16c:
        case bfd_mach_m16c:
          if (highest_addr_loaded > 0x10000)
          if (highest_addr_loaded > 0x10000)
            regs.r_pc = mem_get_si (0x000ffffc) & membus_mask;
            regs.r_pc = mem_get_si (0x000ffffc) & membus_mask;
          else
          else
            regs.r_pc = mem_get_si (0x000fffc) & membus_mask;
            regs.r_pc = mem_get_si (0x000fffc) & membus_mask;
          break;
          break;
        case bfd_mach_m32c:
        case bfd_mach_m32c:
          regs.r_pc = mem_get_si (0x00fffffc) & membus_mask;
          regs.r_pc = mem_get_si (0x00fffffc) & membus_mask;
          break;
          break;
        }
        }
    }
    }
  else
  else
    regs.r_pc = prog->start_address;
    regs.r_pc = prog->start_address;
  if (verbose)
  if (verbose)
    fprintf (stderr, "[start pc=%08x]\n", (unsigned int) regs.r_pc);
    fprintf (stderr, "[start pc=%08x]\n", (unsigned int) regs.r_pc);
}
}
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.