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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [m32r/] [sim-main.h] - Diff between revs 24 and 33

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Rev 24 Rev 33
/* Main header for the m32r.  */
/* Main header for the m32r.  */
 
 
#ifndef SIM_MAIN_H
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
#define SIM_MAIN_H
 
 
#define USING_SIM_BASE_H /* FIXME: quick hack */
#define USING_SIM_BASE_H /* FIXME: quick hack */
 
 
struct _sim_cpu; /* FIXME: should be in sim-basics.h */
struct _sim_cpu; /* FIXME: should be in sim-basics.h */
typedef struct _sim_cpu SIM_CPU;
typedef struct _sim_cpu SIM_CPU;
 
 
#include "symcat.h"
#include "symcat.h"
#include "sim-basics.h"
#include "sim-basics.h"
#include "cgen-types.h"
#include "cgen-types.h"
#include "m32r-desc.h"
#include "m32r-desc.h"
#include "m32r-opc.h"
#include "m32r-opc.h"
#include "arch.h"
#include "arch.h"
 
 
/* These must be defined before sim-base.h.  */
/* These must be defined before sim-base.h.  */
typedef USI sim_cia;
typedef USI sim_cia;
 
 
#define CIA_GET(cpu)     CPU_PC_GET (cpu)
#define CIA_GET(cpu)     CPU_PC_GET (cpu)
#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
 
 
#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
do { \
do { \
  if (cpu) /* null if ctrl-c */ \
  if (cpu) /* null if ctrl-c */ \
    sim_pc_set ((cpu), (cia)); \
    sim_pc_set ((cpu), (cia)); \
} while (0)
} while (0)
#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
do { \
do { \
  sim_pc_set ((cpu), (cia)); \
  sim_pc_set ((cpu), (cia)); \
} while (0)
} while (0)
 
 
#include "sim-base.h"
#include "sim-base.h"
#include "cgen-sim.h"
#include "cgen-sim.h"
#include "m32r-sim.h"
#include "m32r-sim.h"
#include "opcode/cgen.h"
#include "opcode/cgen.h"


/* The _sim_cpu struct.  */
/* The _sim_cpu struct.  */
 
 
struct _sim_cpu {
struct _sim_cpu {
  /* sim/common cpu base.  */
  /* sim/common cpu base.  */
  sim_cpu_base base;
  sim_cpu_base base;
 
 
  /* Static parts of cgen.  */
  /* Static parts of cgen.  */
  CGEN_CPU cgen_cpu;
  CGEN_CPU cgen_cpu;
 
 
  M32R_MISC_PROFILE m32r_misc_profile;
  M32R_MISC_PROFILE m32r_misc_profile;
#define CPU_M32R_MISC_PROFILE(cpu) (& (cpu)->m32r_misc_profile)
#define CPU_M32R_MISC_PROFILE(cpu) (& (cpu)->m32r_misc_profile)
 
 
  /* CPU specific parts go here.
  /* CPU specific parts go here.
     Note that in files that don't need to access these pieces WANT_CPU_FOO
     Note that in files that don't need to access these pieces WANT_CPU_FOO
     won't be defined and thus these parts won't appear.  This is ok in the
     won't be defined and thus these parts won't appear.  This is ok in the
     sense that things work.  It is a source of bugs though.
     sense that things work.  It is a source of bugs though.
     One has to of course be careful to not take the size of this
     One has to of course be careful to not take the size of this
     struct and no structure members accessed in non-cpu specific files can
     struct and no structure members accessed in non-cpu specific files can
     go after here.  Oh for a better language.  */
     go after here.  Oh for a better language.  */
#if defined (WANT_CPU_M32RBF)
#if defined (WANT_CPU_M32RBF)
  M32RBF_CPU_DATA cpu_data;
  M32RBF_CPU_DATA cpu_data;
#endif
#endif
#if defined (WANT_CPU_M32RXF)
#if defined (WANT_CPU_M32RXF)
  M32RXF_CPU_DATA cpu_data;
  M32RXF_CPU_DATA cpu_data;
#elif defined (WANT_CPU_M32R2F)
#elif defined (WANT_CPU_M32R2F)
  M32R2F_CPU_DATA cpu_data;
  M32R2F_CPU_DATA cpu_data;
#endif
#endif
};
};


/* The sim_state struct.  */
/* The sim_state struct.  */
 
 
struct sim_state {
struct sim_state {
  sim_cpu *cpu;
  sim_cpu *cpu;
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
 
 
  CGEN_STATE cgen_state;
  CGEN_STATE cgen_state;
 
 
  sim_state_base base;
  sim_state_base base;
};
};


/* Misc.  */
/* Misc.  */
 
 
/* Catch address exceptions.  */
/* Catch address exceptions.  */
extern SIM_CORE_SIGNAL_FN m32r_core_signal;
extern SIM_CORE_SIGNAL_FN m32r_core_signal;
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
                  (TRANSFER), (ERROR))
                  (TRANSFER), (ERROR))
 
 
/* Default memory size.  */
/* Default memory size.  */
#ifdef M32R_LINUX
#ifdef M32R_LINUX
#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
#else
#else
#define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */
#define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */
#endif
#endif
 
 
#endif /* SIM_MAIN_H */
#endif /* SIM_MAIN_H */
 
 

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