/* This file is part of the program GDB, the GNU debugger.
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/* This file is part of the program GDB, the GNU debugger.
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Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc.
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Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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Contributed by Cygnus Solutions.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include "sim-main.h"
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#include "sim-main.h"
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#include "hw-main.h"
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#include "hw-main.h"
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/* DEVICE
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/* DEVICE
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tx3904cpu - tx3904 cpu virtual device
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tx3904cpu - tx3904 cpu virtual device
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DESCRIPTION
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DESCRIPTION
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Implements the external tx3904 functionality. This includes the
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Implements the external tx3904 functionality. This includes the
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delivery of of interrupts generated from other devices and the
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delivery of of interrupts generated from other devices and the
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handling of device specific registers.
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handling of device specific registers.
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PROPERTIES
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PROPERTIES
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none
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none
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PORTS
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PORTS
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reset (input)
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reset (input)
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Currently ignored.
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Currently ignored.
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nmi (input)
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nmi (input)
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Deliver a non-maskable interrupt to the processor.
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Deliver a non-maskable interrupt to the processor.
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level (input)
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level (input)
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Deliver a maskable interrupt of given level, corresponding to
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Deliver a maskable interrupt of given level, corresponding to
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IP[5:0], to processor.
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IP[5:0], to processor.
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BUGS
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BUGS
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When delivering an interrupt, this code assumes that there is only
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When delivering an interrupt, this code assumes that there is only
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one processor (number 0).
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one processor (number 0).
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This code does not attempt to be efficient at handling pending
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This code does not attempt to be efficient at handling pending
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interrupts. It simply schedules the interrupt delivery handler
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interrupts. It simply schedules the interrupt delivery handler
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every instruction cycle until all pending interrupts go away. An
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every instruction cycle until all pending interrupts go away. An
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alternative implementation might modify instructions that change
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alternative implementation might modify instructions that change
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the PSW and have them check to see if the change makes an interrupt
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the PSW and have them check to see if the change makes an interrupt
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delivery possible.
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delivery possible.
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*/
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*/
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struct tx3904cpu {
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struct tx3904cpu {
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/* Pending interrupts for delivery by event handler */
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/* Pending interrupts for delivery by event handler */
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int pending_reset, pending_nmi, pending_level;
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int pending_reset, pending_nmi, pending_level;
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struct hw_event* event;
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struct hw_event* event;
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};
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};
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/* input port ID's */
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/* input port ID's */
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enum {
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enum {
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RESET_PORT,
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RESET_PORT,
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NMI_PORT,
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NMI_PORT,
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LEVEL_PORT,
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LEVEL_PORT,
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};
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};
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static const struct hw_port_descriptor tx3904cpu_ports[] = {
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static const struct hw_port_descriptor tx3904cpu_ports[] = {
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/* interrupt inputs */
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/* interrupt inputs */
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{ "reset", RESET_PORT, 0, input_port, },
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{ "reset", RESET_PORT, 0, input_port, },
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{ "nmi", NMI_PORT, 0, input_port, },
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{ "nmi", NMI_PORT, 0, input_port, },
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{ "level", LEVEL_PORT, 0, input_port, },
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{ "level", LEVEL_PORT, 0, input_port, },
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{ NULL, },
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{ NULL, },
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};
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};
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/* Finish off the partially created hw device. Attach our local
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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callbacks. Wire up our port names etc */
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static hw_port_event_method tx3904cpu_port_event;
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static hw_port_event_method tx3904cpu_port_event;
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static void
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static void
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tx3904cpu_finish (struct hw *me)
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tx3904cpu_finish (struct hw *me)
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{
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{
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struct tx3904cpu *controller;
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struct tx3904cpu *controller;
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controller = HW_ZALLOC (me, struct tx3904cpu);
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controller = HW_ZALLOC (me, struct tx3904cpu);
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set_hw_data (me, controller);
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set_hw_data (me, controller);
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set_hw_ports (me, tx3904cpu_ports);
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set_hw_ports (me, tx3904cpu_ports);
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set_hw_port_event (me, tx3904cpu_port_event);
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set_hw_port_event (me, tx3904cpu_port_event);
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/* Initialize the pending interrupt flags */
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/* Initialize the pending interrupt flags */
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controller->pending_level = 0;
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controller->pending_level = 0;
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controller->pending_reset = 0;
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controller->pending_reset = 0;
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controller->pending_nmi = 0;
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controller->pending_nmi = 0;
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controller->event = NULL;
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controller->event = NULL;
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}
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}
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/* An event arrives on an interrupt port */
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/* An event arrives on an interrupt port */
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static void
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static void
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deliver_tx3904cpu_interrupt (struct hw *me,
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deliver_tx3904cpu_interrupt (struct hw *me,
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void *data)
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void *data)
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{
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{
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struct tx3904cpu *controller = hw_data (me);
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struct tx3904cpu *controller = hw_data (me);
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SIM_DESC sd = hw_system (me);
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SIM_DESC sd = hw_system (me);
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sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */
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sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */
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address_word cia = CIA_GET (cpu);
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address_word cia = CIA_GET (cpu);
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#define CPU cpu
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#define CPU cpu
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#define SD current_state
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#define SD current_state
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if (controller->pending_reset)
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if (controller->pending_reset)
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{
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{
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controller->pending_reset = 0;
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controller->pending_reset = 0;
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HW_TRACE ((me, "reset pc=0x%08lx", (long) CIA_GET (cpu)));
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HW_TRACE ((me, "reset pc=0x%08lx", (long) CIA_GET (cpu)));
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SignalExceptionNMIReset();
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SignalExceptionNMIReset();
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}
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}
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else if (controller->pending_nmi)
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else if (controller->pending_nmi)
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{
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{
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controller->pending_nmi = 0;
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controller->pending_nmi = 0;
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HW_TRACE ((me, "nmi pc=0x%08lx", (long) CIA_GET (cpu)));
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HW_TRACE ((me, "nmi pc=0x%08lx", (long) CIA_GET (cpu)));
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SignalExceptionNMIReset();
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SignalExceptionNMIReset();
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}
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}
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else if (controller->pending_level)
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else if (controller->pending_level)
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{
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{
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HW_TRACE ((me, "interrupt level=%d pc=0x%08lx sr=0x%08lx",
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HW_TRACE ((me, "interrupt level=%d pc=0x%08lx sr=0x%08lx",
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controller->pending_level,
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controller->pending_level,
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(long) CIA_GET (cpu), (long) SR));
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(long) CIA_GET (cpu), (long) SR));
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/* Clear CAUSE register. It may stay this way if the interrupt
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/* Clear CAUSE register. It may stay this way if the interrupt
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was cleared with a negative pending_level. */
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was cleared with a negative pending_level. */
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CAUSE &= ~ (cause_IP_mask << cause_IP_shift);
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CAUSE &= ~ (cause_IP_mask << cause_IP_shift);
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if(controller->pending_level > 0) /* interrupt set */
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if(controller->pending_level > 0) /* interrupt set */
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{
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{
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/* set hardware-interrupt subfields of CAUSE register */
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/* set hardware-interrupt subfields of CAUSE register */
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CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift;
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CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift;
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/* check for enabled / unmasked interrupts */
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/* check for enabled / unmasked interrupts */
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if((SR & status_IEc) &&
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if((SR & status_IEc) &&
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(controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask)))
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(controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask)))
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{
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{
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controller->pending_level = 0;
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controller->pending_level = 0;
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SignalExceptionInterrupt(0 /* dummy value */);
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SignalExceptionInterrupt(0 /* dummy value */);
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}
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}
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else
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else
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{
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{
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/* reschedule soon */
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/* reschedule soon */
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if(controller->event != NULL)
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if(controller->event != NULL)
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hw_event_queue_deschedule(me, controller->event);
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hw_event_queue_deschedule(me, controller->event);
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controller->event =
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controller->event =
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hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL);
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hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL);
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}
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}
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} /* interrupt set */
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} /* interrupt set */
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}
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}
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#undef CPU cpu
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#undef CPU cpu
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#undef SD current_state
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#undef SD current_state
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}
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}
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static void
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static void
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tx3904cpu_port_event (struct hw *me,
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tx3904cpu_port_event (struct hw *me,
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int my_port,
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int my_port,
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struct hw *source,
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struct hw *source,
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int source_port,
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int source_port,
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int level)
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int level)
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{
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{
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struct tx3904cpu *controller = hw_data (me);
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struct tx3904cpu *controller = hw_data (me);
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switch (my_port)
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switch (my_port)
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{
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{
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case RESET_PORT:
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case RESET_PORT:
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controller->pending_reset = 1;
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controller->pending_reset = 1;
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HW_TRACE ((me, "port-in reset"));
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HW_TRACE ((me, "port-in reset"));
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break;
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break;
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case NMI_PORT:
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case NMI_PORT:
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controller->pending_nmi = 1;
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controller->pending_nmi = 1;
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HW_TRACE ((me, "port-in nmi"));
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HW_TRACE ((me, "port-in nmi"));
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break;
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break;
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case LEVEL_PORT:
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case LEVEL_PORT:
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/* level == 0 means that the interrupt was cleared */
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/* level == 0 means that the interrupt was cleared */
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if(level == 0)
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if(level == 0)
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controller->pending_level = -1; /* signal end of interrupt */
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controller->pending_level = -1; /* signal end of interrupt */
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else
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else
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controller->pending_level = level;
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controller->pending_level = level;
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HW_TRACE ((me, "port-in level=%d", level));
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HW_TRACE ((me, "port-in level=%d", level));
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break;
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break;
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default:
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default:
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hw_abort (me, "bad switch");
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hw_abort (me, "bad switch");
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break;
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break;
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}
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}
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/* Schedule an event to be delivered immediately after current
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/* Schedule an event to be delivered immediately after current
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instruction. */
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instruction. */
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if(controller->event != NULL)
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if(controller->event != NULL)
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hw_event_queue_deschedule(me, controller->event);
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hw_event_queue_deschedule(me, controller->event);
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controller->event =
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controller->event =
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hw_event_queue_schedule (me, 0, deliver_tx3904cpu_interrupt, NULL);
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hw_event_queue_schedule (me, 0, deliver_tx3904cpu_interrupt, NULL);
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}
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}
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const struct hw_descriptor dv_tx3904cpu_descriptor[] = {
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const struct hw_descriptor dv_tx3904cpu_descriptor[] = {
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{ "tx3904cpu", tx3904cpu_finish, },
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{ "tx3904cpu", tx3904cpu_finish, },
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{ NULL },
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{ NULL },
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};
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};
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