/* This file is part of the program GDB, the GNU debugger.
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/* This file is part of the program GDB, the GNU debugger.
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Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc.
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Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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Contributed by Cygnus Solutions.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include "sim-main.h"
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#include "sim-main.h"
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#include "hw-main.h"
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#include "hw-main.h"
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/* DEVICE
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/* DEVICE
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tx3904tmr - tx3904 timer
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tx3904tmr - tx3904 timer
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DESCRIPTION
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DESCRIPTION
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Implements one tx3904 timer/counter described in the tx3904
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Implements one tx3904 timer/counter described in the tx3904
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user guide. Three instances are required for TMR0, TMR1, and
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user guide. Three instances are required for TMR0, TMR1, and
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TMR3 within the tx3904, at different base addresses.
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TMR3 within the tx3904, at different base addresses.
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Both internal and system clocks are synthesized as divided versions
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Both internal and system clocks are synthesized as divided versions
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of the simulator clock.
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of the simulator clock.
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There is no support for:
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There is no support for:
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- edge sensitivity of external clock
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- edge sensitivity of external clock
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- different mode restrictions for TMR0..2
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- different mode restrictions for TMR0..2
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- level interrupts (interrupts are treated as events that occur at edges)
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- level interrupts (interrupts are treated as events that occur at edges)
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PROPERTIES
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PROPERTIES
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reg <base> <length>
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reg <base> <length>
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Base of TMR control register bank. <length> must equal 0x100.
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Base of TMR control register bank. <length> must equal 0x100.
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Register offsets: 0: TCR: timer control register
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Register offsets: 0: TCR: timer control register
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4: TISR: timer interrupt status register
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4: TISR: timer interrupt status register
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8: CPRA: compare register A
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8: CPRA: compare register A
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12: CPRB: compare register B
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12: CPRB: compare register B
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16: ITMR: interval timer mode register
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16: ITMR: interval timer mode register
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32: CCDR: divider register
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32: CCDR: divider register
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48: PMGR: pulse generator mode register
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48: PMGR: pulse generator mode register
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64: WTMR: watchdog timer mode register
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64: WTMR: watchdog timer mode register
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240: TRR: timer read register
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240: TRR: timer read register
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clock <ticks>
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clock <ticks>
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Rate of timer clock signal. This number is the number of simulator
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Rate of timer clock signal. This number is the number of simulator
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ticks per clock signal tick. Default 1.
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ticks per clock signal tick. Default 1.
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ext <ticks>
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ext <ticks>
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Rate of "external input clock signal", the other clock input of the
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Rate of "external input clock signal", the other clock input of the
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timer. It uses the same scale as above. Default 100.
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timer. It uses the same scale as above. Default 100.
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PORTS
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PORTS
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int (output)
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int (output)
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Interrupt port. An event is generated when a timer interrupt
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Interrupt port. An event is generated when a timer interrupt
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occurs.
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occurs.
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ff (output)
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ff (output)
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Flip-flop output, corresponds to the TMFFOUT port. An event is
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Flip-flop output, corresponds to the TMFFOUT port. An event is
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generated when flip-flop changes value. The integer associated
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generated when flip-flop changes value. The integer associated
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with the event is 1/0 according to flip-flop value.
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with the event is 1/0 according to flip-flop value.
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reset (input)
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reset (input)
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Reset port.
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Reset port.
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*/
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*/
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/* static functions */
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/* static functions */
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static void deliver_tx3904tmr_tick (struct hw *me, void *data);
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static void deliver_tx3904tmr_tick (struct hw *me, void *data);
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/* register numbers; each is one word long */
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/* register numbers; each is one word long */
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enum
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enum
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{
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{
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TCR_REG = 0,
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TCR_REG = 0,
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TISR_REG = 1,
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TISR_REG = 1,
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CPRA_REG = 2,
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CPRA_REG = 2,
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CPRB_REG = 3,
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CPRB_REG = 3,
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ITMR_REG = 4,
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ITMR_REG = 4,
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CCDR_REG = 8,
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CCDR_REG = 8,
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PMGR_REG = 12,
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PMGR_REG = 12,
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WTMR_REG = 16,
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WTMR_REG = 16,
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TRR_REG = 60
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TRR_REG = 60
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};
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};
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/* port ID's */
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/* port ID's */
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enum
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enum
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{
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{
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RESET_PORT,
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RESET_PORT,
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INT_PORT,
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INT_PORT,
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FF_PORT
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FF_PORT
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};
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};
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static const struct hw_port_descriptor tx3904tmr_ports[] =
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static const struct hw_port_descriptor tx3904tmr_ports[] =
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{
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{
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{ "int", INT_PORT, 0, output_port, },
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{ "int", INT_PORT, 0, output_port, },
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{ "ff", FF_PORT, 0, output_port, },
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{ "ff", FF_PORT, 0, output_port, },
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{ "reset", RESET_PORT, 0, input_port, },
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{ "reset", RESET_PORT, 0, input_port, },
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{ NULL, },
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{ NULL, },
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};
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};
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/* The timer/counter register internal state. Note that we store
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/* The timer/counter register internal state. Note that we store
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state using the control register images, in host endian order. */
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state using the control register images, in host endian order. */
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struct tx3904tmr {
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struct tx3904tmr {
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address_word base_address; /* control register base */
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address_word base_address; /* control register base */
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unsigned_4 clock_ticks, ext_ticks; /* clock frequencies */
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unsigned_4 clock_ticks, ext_ticks; /* clock frequencies */
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signed_8 last_ticks; /* time at last deliver_*_tick call */
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signed_8 last_ticks; /* time at last deliver_*_tick call */
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signed_8 roundoff_ticks; /* sim ticks unprocessed during last tick call */
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signed_8 roundoff_ticks; /* sim ticks unprocessed during last tick call */
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int ff; /* pulse generator flip-flop value: 1/0 */
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int ff; /* pulse generator flip-flop value: 1/0 */
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struct hw_event* event; /* last scheduled event */
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struct hw_event* event; /* last scheduled event */
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unsigned_4 tcr;
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unsigned_4 tcr;
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#define GET_TCR_TCE(c) (((c)->tcr & 0x80) >> 7)
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#define GET_TCR_TCE(c) (((c)->tcr & 0x80) >> 7)
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#define GET_TCR_CCDE(c) (((c)->tcr & 0x40) >> 6)
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#define GET_TCR_CCDE(c) (((c)->tcr & 0x40) >> 6)
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#define GET_TCR_CRE(c) (((c)->tcr & 0x20) >> 5)
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#define GET_TCR_CRE(c) (((c)->tcr & 0x20) >> 5)
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#define GET_TCR_CCS(c) (((c)->tcr & 0x04) >> 2)
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#define GET_TCR_CCS(c) (((c)->tcr & 0x04) >> 2)
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#define GET_TCR_TMODE(c) (((c)->tcr & 0x03) >> 0)
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#define GET_TCR_TMODE(c) (((c)->tcr & 0x03) >> 0)
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unsigned_4 tisr;
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unsigned_4 tisr;
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#define SET_TISR_TWIS(c) ((c)->tisr |= 0x08)
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#define SET_TISR_TWIS(c) ((c)->tisr |= 0x08)
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#define SET_TISR_TPIBS(c) ((c)->tisr |= 0x04)
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#define SET_TISR_TPIBS(c) ((c)->tisr |= 0x04)
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#define SET_TISR_TPIAS(c) ((c)->tisr |= 0x02)
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#define SET_TISR_TPIAS(c) ((c)->tisr |= 0x02)
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#define SET_TISR_TIIS(c) ((c)->tisr |= 0x01)
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#define SET_TISR_TIIS(c) ((c)->tisr |= 0x01)
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unsigned_4 cpra;
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unsigned_4 cpra;
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unsigned_4 cprb;
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unsigned_4 cprb;
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unsigned_4 itmr;
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unsigned_4 itmr;
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#define GET_ITMR_TIIE(c) (((c)->itmr & 0x8000) >> 15)
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#define GET_ITMR_TIIE(c) (((c)->itmr & 0x8000) >> 15)
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#define SET_ITMR_TIIE(c,v) BLIT32((c)->itmr, 15, (v) ? 1 : 0)
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#define SET_ITMR_TIIE(c,v) BLIT32((c)->itmr, 15, (v) ? 1 : 0)
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#define GET_ITMR_TZCE(c) (((c)->itmr & 0x0001) >> 0)
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#define GET_ITMR_TZCE(c) (((c)->itmr & 0x0001) >> 0)
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#define SET_ITMR_TZCE(c,v) BLIT32((c)->itmr, 0, (v) ? 1 : 0)
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#define SET_ITMR_TZCE(c,v) BLIT32((c)->itmr, 0, (v) ? 1 : 0)
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unsigned_4 ccdr;
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unsigned_4 ccdr;
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#define GET_CCDR_CDR(c) (((c)->ccdr & 0x07) >> 0)
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#define GET_CCDR_CDR(c) (((c)->ccdr & 0x07) >> 0)
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unsigned_4 pmgr;
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unsigned_4 pmgr;
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#define GET_PMGR_TPIBE(c) (((c)->pmgr & 0x8000) >> 15)
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#define GET_PMGR_TPIBE(c) (((c)->pmgr & 0x8000) >> 15)
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#define SET_PMGR_TPIBE(c,v) BLIT32((c)->pmgr, 15, (v) ? 1 : 0)
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#define SET_PMGR_TPIBE(c,v) BLIT32((c)->pmgr, 15, (v) ? 1 : 0)
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#define GET_PMGR_TPIAE(c) (((c)->pmgr & 0x4000) >> 14)
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#define GET_PMGR_TPIAE(c) (((c)->pmgr & 0x4000) >> 14)
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#define SET_PMGR_TPIAE(c,v) BLIT32((c)->pmgr, 14, (v) ? 1 : 0)
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#define SET_PMGR_TPIAE(c,v) BLIT32((c)->pmgr, 14, (v) ? 1 : 0)
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#define GET_PMGR_FFI(c) (((c)->pmgr & 0x0001) >> 0)
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#define GET_PMGR_FFI(c) (((c)->pmgr & 0x0001) >> 0)
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#define SET_PMGR_FFI(c,v) BLIT32((c)->pmgr, 0, (v) ? 1 : 0)
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#define SET_PMGR_FFI(c,v) BLIT32((c)->pmgr, 0, (v) ? 1 : 0)
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unsigned_4 wtmr;
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unsigned_4 wtmr;
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#define GET_WTMR_TWIE(c) (((c)->wtmr & 0x8000) >> 15)
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#define GET_WTMR_TWIE(c) (((c)->wtmr & 0x8000) >> 15)
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#define SET_WTMR_TWIE(c,v) BLIT32((c)->wtmr, 15, (v) ? 1 : 0)
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#define SET_WTMR_TWIE(c,v) BLIT32((c)->wtmr, 15, (v) ? 1 : 0)
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#define GET_WTMR_WDIS(c) (((c)->wtmr & 0x0080) >> 7)
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#define GET_WTMR_WDIS(c) (((c)->wtmr & 0x0080) >> 7)
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#define SET_WTMR_WDIS(c,v) BLIT32((c)->wtmr, 7, (v) ? 1 : 0)
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#define SET_WTMR_WDIS(c,v) BLIT32((c)->wtmr, 7, (v) ? 1 : 0)
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#define GET_WTMR_TWC(c) (((c)->wtmr & 0x0001) >> 0)
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#define GET_WTMR_TWC(c) (((c)->wtmr & 0x0001) >> 0)
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#define SET_WTMR_TWC(c,v) BLIT32((c)->wtmr, 0, (v) ? 1 : 0)
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#define SET_WTMR_TWC(c,v) BLIT32((c)->wtmr, 0, (v) ? 1 : 0)
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unsigned_4 trr;
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unsigned_4 trr;
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};
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};
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/* Finish off the partially created hw device. Attach our local
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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callbacks. Wire up our port names etc */
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static hw_io_read_buffer_method tx3904tmr_io_read_buffer;
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static hw_io_read_buffer_method tx3904tmr_io_read_buffer;
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static hw_io_write_buffer_method tx3904tmr_io_write_buffer;
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static hw_io_write_buffer_method tx3904tmr_io_write_buffer;
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static hw_port_event_method tx3904tmr_port_event;
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static hw_port_event_method tx3904tmr_port_event;
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static void
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static void
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attach_tx3904tmr_regs (struct hw *me,
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attach_tx3904tmr_regs (struct hw *me,
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struct tx3904tmr *controller)
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struct tx3904tmr *controller)
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{
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{
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unsigned_word attach_address;
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unsigned_word attach_address;
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int attach_space;
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int attach_space;
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unsigned attach_size;
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unsigned attach_size;
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reg_property_spec reg;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain one addr/size entry");
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hw_abort (me, "\"reg\" property must contain one addr/size entry");
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hw_unit_address_to_attach_address (hw_parent (me),
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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®.address,
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&attach_space,
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&attach_space,
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&attach_address,
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&attach_address,
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me);
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me);
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hw_unit_size_to_attach_size (hw_parent (me),
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hw_unit_size_to_attach_size (hw_parent (me),
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®.size,
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®.size,
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&attach_size, me);
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&attach_size, me);
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hw_attach_address (hw_parent (me), 0,
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hw_attach_address (hw_parent (me), 0,
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attach_space, attach_address, attach_size,
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attach_space, attach_address, attach_size,
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me);
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me);
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if(hw_find_property(me, "clock") != NULL)
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if(hw_find_property(me, "clock") != NULL)
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controller->clock_ticks = (unsigned_4) hw_find_integer_property(me, "clock");
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controller->clock_ticks = (unsigned_4) hw_find_integer_property(me, "clock");
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if(hw_find_property(me, "ext") != NULL)
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if(hw_find_property(me, "ext") != NULL)
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controller->ext_ticks = (unsigned_4) hw_find_integer_property(me, "ext");
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controller->ext_ticks = (unsigned_4) hw_find_integer_property(me, "ext");
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controller->base_address = attach_address;
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controller->base_address = attach_address;
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}
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}
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static void
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static void
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tx3904tmr_finish (struct hw *me)
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tx3904tmr_finish (struct hw *me)
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{
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{
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struct tx3904tmr *controller;
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struct tx3904tmr *controller;
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controller = HW_ZALLOC (me, struct tx3904tmr);
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controller = HW_ZALLOC (me, struct tx3904tmr);
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set_hw_data (me, controller);
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set_hw_data (me, controller);
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set_hw_io_read_buffer (me, tx3904tmr_io_read_buffer);
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set_hw_io_read_buffer (me, tx3904tmr_io_read_buffer);
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set_hw_io_write_buffer (me, tx3904tmr_io_write_buffer);
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set_hw_io_write_buffer (me, tx3904tmr_io_write_buffer);
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set_hw_ports (me, tx3904tmr_ports);
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set_hw_ports (me, tx3904tmr_ports);
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set_hw_port_event (me, tx3904tmr_port_event);
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set_hw_port_event (me, tx3904tmr_port_event);
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/* Preset clock dividers */
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/* Preset clock dividers */
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controller->clock_ticks = 1;
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controller->clock_ticks = 1;
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controller->ext_ticks = 100;
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controller->ext_ticks = 100;
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/* Attach ourself to our parent bus */
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/* Attach ourself to our parent bus */
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attach_tx3904tmr_regs (me, controller);
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attach_tx3904tmr_regs (me, controller);
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/* Initialize to reset state */
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/* Initialize to reset state */
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controller->tcr =
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controller->tcr =
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controller->itmr =
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controller->itmr =
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controller->ccdr =
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controller->ccdr =
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controller->pmgr =
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controller->pmgr =
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controller->wtmr =
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controller->wtmr =
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controller->tisr =
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controller->tisr =
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controller->trr = 0;
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controller->trr = 0;
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controller->cpra = controller->cprb = 0x00FFFFFF;
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controller->cpra = controller->cprb = 0x00FFFFFF;
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controller->ff = 0;
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controller->ff = 0;
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controller->last_ticks = controller->roundoff_ticks = 0;
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controller->last_ticks = controller->roundoff_ticks = 0;
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controller->event = NULL;
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controller->event = NULL;
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}
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}
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/* An event arrives on an interrupt port */
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/* An event arrives on an interrupt port */
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static void
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static void
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tx3904tmr_port_event (struct hw *me,
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tx3904tmr_port_event (struct hw *me,
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int my_port,
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int my_port,
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struct hw *source,
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struct hw *source,
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int source_port,
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int source_port,
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int level)
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int level)
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{
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{
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struct tx3904tmr *controller = hw_data (me);
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struct tx3904tmr *controller = hw_data (me);
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switch (my_port)
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switch (my_port)
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{
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{
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case RESET_PORT:
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case RESET_PORT:
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{
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{
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HW_TRACE ((me, "reset"));
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HW_TRACE ((me, "reset"));
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/* preset flip-flop to FFI value */
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/* preset flip-flop to FFI value */
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controller->ff = GET_PMGR_FFI(controller);
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controller->ff = GET_PMGR_FFI(controller);
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controller->tcr =
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controller->tcr =
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controller->itmr =
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controller->itmr =
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controller->ccdr =
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controller->ccdr =
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controller->pmgr =
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controller->pmgr =
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controller->wtmr =
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controller->wtmr =
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controller->tisr =
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controller->tisr =
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controller->trr = 0;
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controller->trr = 0;
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controller->cpra = controller->cprb = 0x00FFFFFF;
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controller->cpra = controller->cprb = 0x00FFFFFF;
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controller->last_ticks = controller->roundoff_ticks = 0;
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controller->last_ticks = controller->roundoff_ticks = 0;
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if(controller->event != NULL)
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if(controller->event != NULL)
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hw_event_queue_deschedule(me, controller->event);
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hw_event_queue_deschedule(me, controller->event);
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controller->event = NULL;
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controller->event = NULL;
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break;
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break;
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}
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}
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default:
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default:
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hw_abort (me, "Event on unknown port %d", my_port);
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hw_abort (me, "Event on unknown port %d", my_port);
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break;
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break;
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}
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}
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}
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}
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/* generic read/write */
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/* generic read/write */
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static unsigned
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static unsigned
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tx3904tmr_io_read_buffer (struct hw *me,
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tx3904tmr_io_read_buffer (struct hw *me,
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void *dest,
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void *dest,
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int space,
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int space,
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unsigned_word base,
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unsigned_word base,
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unsigned nr_bytes)
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unsigned nr_bytes)
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{
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{
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struct tx3904tmr *controller = hw_data (me);
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struct tx3904tmr *controller = hw_data (me);
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unsigned byte;
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unsigned byte;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
|
for (byte = 0; byte < nr_bytes; byte++)
|
for (byte = 0; byte < nr_bytes; byte++)
|
{
|
{
|
address_word address = base + byte;
|
address_word address = base + byte;
|
int reg_number = (address - controller->base_address) / 4;
|
int reg_number = (address - controller->base_address) / 4;
|
int reg_offset = 3 - (address - controller->base_address) % 4;
|
int reg_offset = 3 - (address - controller->base_address) % 4;
|
unsigned_4 register_value; /* in target byte order */
|
unsigned_4 register_value; /* in target byte order */
|
|
|
/* fill in entire register_value word */
|
/* fill in entire register_value word */
|
switch (reg_number)
|
switch (reg_number)
|
{
|
{
|
case TCR_REG: register_value = controller->tcr; break;
|
case TCR_REG: register_value = controller->tcr; break;
|
case TISR_REG: register_value = controller->tisr; break;
|
case TISR_REG: register_value = controller->tisr; break;
|
case CPRA_REG: register_value = controller->cpra; break;
|
case CPRA_REG: register_value = controller->cpra; break;
|
case CPRB_REG: register_value = controller->cprb; break;
|
case CPRB_REG: register_value = controller->cprb; break;
|
case ITMR_REG: register_value = controller->itmr; break;
|
case ITMR_REG: register_value = controller->itmr; break;
|
case CCDR_REG: register_value = controller->ccdr; break;
|
case CCDR_REG: register_value = controller->ccdr; break;
|
case PMGR_REG: register_value = controller->pmgr; break;
|
case PMGR_REG: register_value = controller->pmgr; break;
|
case WTMR_REG: register_value = controller->wtmr; break;
|
case WTMR_REG: register_value = controller->wtmr; break;
|
case TRR_REG: register_value = controller->trr; break;
|
case TRR_REG: register_value = controller->trr; break;
|
default: register_value = 0;
|
default: register_value = 0;
|
}
|
}
|
|
|
/* write requested byte out */
|
/* write requested byte out */
|
memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1);
|
memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1);
|
}
|
}
|
|
|
return nr_bytes;
|
return nr_bytes;
|
}
|
}
|
|
|
|
|
|
|
static unsigned
|
static unsigned
|
tx3904tmr_io_write_buffer (struct hw *me,
|
tx3904tmr_io_write_buffer (struct hw *me,
|
const void *source,
|
const void *source,
|
int space,
|
int space,
|
unsigned_word base,
|
unsigned_word base,
|
unsigned nr_bytes)
|
unsigned nr_bytes)
|
{
|
{
|
struct tx3904tmr *controller = hw_data (me);
|
struct tx3904tmr *controller = hw_data (me);
|
unsigned byte;
|
unsigned byte;
|
|
|
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
|
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
|
for (byte = 0; byte < nr_bytes; byte++)
|
for (byte = 0; byte < nr_bytes; byte++)
|
{
|
{
|
address_word address = base + byte;
|
address_word address = base + byte;
|
unsigned_1 write_byte = ((const char*) source)[byte];
|
unsigned_1 write_byte = ((const char*) source)[byte];
|
int reg_number = (address - controller->base_address) / 4;
|
int reg_number = (address - controller->base_address) / 4;
|
int reg_offset = 3 - (address - controller->base_address) % 4;
|
int reg_offset = 3 - (address - controller->base_address) % 4;
|
|
|
/* fill in entire register_value word */
|
/* fill in entire register_value word */
|
switch (reg_number)
|
switch (reg_number)
|
{
|
{
|
case TCR_REG:
|
case TCR_REG:
|
if(reg_offset == 0) /* first byte */
|
if(reg_offset == 0) /* first byte */
|
{
|
{
|
/* update register, but mask out NOP bits */
|
/* update register, but mask out NOP bits */
|
controller->tcr = (unsigned_4) (write_byte & 0xef);
|
controller->tcr = (unsigned_4) (write_byte & 0xef);
|
|
|
/* Reset counter value if timer suspended and CRE is set. */
|
/* Reset counter value if timer suspended and CRE is set. */
|
if(GET_TCR_TCE(controller) == 0 &&
|
if(GET_TCR_TCE(controller) == 0 &&
|
GET_TCR_CRE(controller) == 1)
|
GET_TCR_CRE(controller) == 1)
|
controller->trr = 0;
|
controller->trr = 0;
|
}
|
}
|
/* HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr)); */
|
/* HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr)); */
|
break;
|
break;
|
|
|
case ITMR_REG:
|
case ITMR_REG:
|
if(reg_offset == 1) /* second byte */
|
if(reg_offset == 1) /* second byte */
|
{
|
{
|
SET_ITMR_TIIE(controller, write_byte & 0x80);
|
SET_ITMR_TIIE(controller, write_byte & 0x80);
|
}
|
}
|
else if(reg_offset == 0) /* first byte */
|
else if(reg_offset == 0) /* first byte */
|
{
|
{
|
SET_ITMR_TZCE(controller, write_byte & 0x01);
|
SET_ITMR_TZCE(controller, write_byte & 0x01);
|
}
|
}
|
/* HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr)); */
|
/* HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr)); */
|
break;
|
break;
|
|
|
case CCDR_REG:
|
case CCDR_REG:
|
if(reg_offset == 0) /* first byte */
|
if(reg_offset == 0) /* first byte */
|
{
|
{
|
controller->ccdr = write_byte & 0x07;
|
controller->ccdr = write_byte & 0x07;
|
}
|
}
|
/* HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr)); */
|
/* HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr)); */
|
break;
|
break;
|
|
|
case PMGR_REG:
|
case PMGR_REG:
|
if(reg_offset == 1) /* second byte */
|
if(reg_offset == 1) /* second byte */
|
{
|
{
|
SET_PMGR_TPIBE(controller, write_byte & 0x80);
|
SET_PMGR_TPIBE(controller, write_byte & 0x80);
|
SET_PMGR_TPIAE(controller, write_byte & 0x40);
|
SET_PMGR_TPIAE(controller, write_byte & 0x40);
|
}
|
}
|
else if(reg_offset == 0) /* first byte */
|
else if(reg_offset == 0) /* first byte */
|
{
|
{
|
SET_PMGR_FFI(controller, write_byte & 0x01);
|
SET_PMGR_FFI(controller, write_byte & 0x01);
|
}
|
}
|
/* HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr)); */
|
/* HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr)); */
|
break;
|
break;
|
|
|
case WTMR_REG:
|
case WTMR_REG:
|
if(reg_offset == 1) /* second byte */
|
if(reg_offset == 1) /* second byte */
|
{
|
{
|
SET_WTMR_TWIE(controller, write_byte & 0x80);
|
SET_WTMR_TWIE(controller, write_byte & 0x80);
|
}
|
}
|
else if(reg_offset == 0) /* first byte */
|
else if(reg_offset == 0) /* first byte */
|
{
|
{
|
SET_WTMR_WDIS(controller, write_byte & 0x80);
|
SET_WTMR_WDIS(controller, write_byte & 0x80);
|
SET_WTMR_TWC(controller, write_byte & 0x01);
|
SET_WTMR_TWC(controller, write_byte & 0x01);
|
}
|
}
|
/* HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr)); */
|
/* HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr)); */
|
break;
|
break;
|
|
|
case TISR_REG:
|
case TISR_REG:
|
if(reg_offset == 0) /* first byte */
|
if(reg_offset == 0) /* first byte */
|
{
|
{
|
/* All bits must be zero in given byte, according to
|
/* All bits must be zero in given byte, according to
|
spec. */
|
spec. */
|
|
|
/* Send an "interrupt off" event on the interrupt port */
|
/* Send an "interrupt off" event on the interrupt port */
|
if(controller->tisr != 0) /* any interrupts active? */
|
if(controller->tisr != 0) /* any interrupts active? */
|
{
|
{
|
hw_port_event(me, INT_PORT, 0);
|
hw_port_event(me, INT_PORT, 0);
|
}
|
}
|
|
|
/* clear interrupt status register */
|
/* clear interrupt status register */
|
controller->tisr = 0;
|
controller->tisr = 0;
|
}
|
}
|
/* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */
|
/* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */
|
break;
|
break;
|
|
|
case CPRA_REG:
|
case CPRA_REG:
|
if(reg_offset < 3) /* first, second, or third byte */
|
if(reg_offset < 3) /* first, second, or third byte */
|
{
|
{
|
MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte);
|
MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte);
|
}
|
}
|
/* HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra)); */
|
/* HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra)); */
|
break;
|
break;
|
|
|
case CPRB_REG:
|
case CPRB_REG:
|
if(reg_offset < 3) /* first, second, or third byte */
|
if(reg_offset < 3) /* first, second, or third byte */
|
{
|
{
|
MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
|
MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
|
}
|
}
|
/* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */
|
/* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */
|
break;
|
break;
|
|
|
default:
|
default:
|
HW_TRACE ((me, "write to illegal register %d", reg_number));
|
HW_TRACE ((me, "write to illegal register %d", reg_number));
|
}
|
}
|
} /* loop over bytes */
|
} /* loop over bytes */
|
|
|
/* Schedule a timer event in near future, so we can increment or
|
/* Schedule a timer event in near future, so we can increment or
|
stop the counter, to respond to register updates. */
|
stop the counter, to respond to register updates. */
|
hw_event_queue_schedule(me, 1, deliver_tx3904tmr_tick, NULL);
|
hw_event_queue_schedule(me, 1, deliver_tx3904tmr_tick, NULL);
|
|
|
return nr_bytes;
|
return nr_bytes;
|
}
|
}
|
|
|
|
|
|
|
/* Deliver a clock tick to the counter. */
|
/* Deliver a clock tick to the counter. */
|
static void
|
static void
|
deliver_tx3904tmr_tick (struct hw *me,
|
deliver_tx3904tmr_tick (struct hw *me,
|
void *data)
|
void *data)
|
{
|
{
|
struct tx3904tmr *controller = hw_data (me);
|
struct tx3904tmr *controller = hw_data (me);
|
SIM_DESC sd = hw_system (me);
|
SIM_DESC sd = hw_system (me);
|
signed_8 this_ticks = sim_events_time(sd);
|
signed_8 this_ticks = sim_events_time(sd);
|
|
|
signed_8 warp;
|
signed_8 warp;
|
signed_8 divisor;
|
signed_8 divisor;
|
signed_8 quotient, remainder;
|
signed_8 quotient, remainder;
|
|
|
/* compute simulation ticks between last tick and this tick */
|
/* compute simulation ticks between last tick and this tick */
|
if(controller->last_ticks != 0)
|
if(controller->last_ticks != 0)
|
warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
|
warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
|
else
|
else
|
{
|
{
|
controller->last_ticks = this_ticks; /* initialize */
|
controller->last_ticks = this_ticks; /* initialize */
|
warp = controller->roundoff_ticks;
|
warp = controller->roundoff_ticks;
|
}
|
}
|
|
|
if(controller->event != NULL)
|
if(controller->event != NULL)
|
hw_event_queue_deschedule(me, controller->event);
|
hw_event_queue_deschedule(me, controller->event);
|
controller->event = NULL;
|
controller->event = NULL;
|
|
|
/* Check whether the timer ticking is enabled at this moment. This
|
/* Check whether the timer ticking is enabled at this moment. This
|
largely a function of the TCE bit, but is also slightly
|
largely a function of the TCE bit, but is also slightly
|
mode-dependent. */
|
mode-dependent. */
|
switch((int) GET_TCR_TMODE(controller))
|
switch((int) GET_TCR_TMODE(controller))
|
{
|
{
|
case 0: /* interval */
|
case 0: /* interval */
|
/* do not advance counter if TCE = 0 or if holding at count = CPRA */
|
/* do not advance counter if TCE = 0 or if holding at count = CPRA */
|
if(GET_TCR_TCE(controller) == 0 ||
|
if(GET_TCR_TCE(controller) == 0 ||
|
controller->trr == controller->cpra)
|
controller->trr == controller->cpra)
|
return;
|
return;
|
break;
|
break;
|
|
|
case 1: /* pulse generator */
|
case 1: /* pulse generator */
|
/* do not advance counter if TCE = 0 */
|
/* do not advance counter if TCE = 0 */
|
if(GET_TCR_TCE(controller) == 0)
|
if(GET_TCR_TCE(controller) == 0)
|
return;
|
return;
|
break;
|
break;
|
|
|
case 2: /* watchdog */
|
case 2: /* watchdog */
|
/* do not advance counter if TCE = 0 and WDIS = 1 */
|
/* do not advance counter if TCE = 0 and WDIS = 1 */
|
if(GET_TCR_TCE(controller) == 0 &&
|
if(GET_TCR_TCE(controller) == 0 &&
|
GET_WTMR_WDIS(controller) == 1)
|
GET_WTMR_WDIS(controller) == 1)
|
return;
|
return;
|
break;
|
break;
|
|
|
case 3: /* disabled */
|
case 3: /* disabled */
|
/* regardless of TCE, do not advance counter */
|
/* regardless of TCE, do not advance counter */
|
return;
|
return;
|
}
|
}
|
|
|
/* In any of the above cases that return, a subsequent register
|
/* In any of the above cases that return, a subsequent register
|
write will be needed to restart the timer. A tick event is
|
write will be needed to restart the timer. A tick event is
|
scheduled by any register write, so it is more efficient not to
|
scheduled by any register write, so it is more efficient not to
|
reschedule dummy events here. */
|
reschedule dummy events here. */
|
|
|
|
|
/* find appropriate divisor etc. */
|
/* find appropriate divisor etc. */
|
if(GET_TCR_CCS(controller) == 0) /* internal system clock */
|
if(GET_TCR_CCS(controller) == 0) /* internal system clock */
|
{
|
{
|
/* apply internal clock divider */
|
/* apply internal clock divider */
|
if(GET_TCR_CCDE(controller)) /* divisor circuit enabled? */
|
if(GET_TCR_CCDE(controller)) /* divisor circuit enabled? */
|
divisor = controller->clock_ticks * (1 << (1 + GET_CCDR_CDR(controller)));
|
divisor = controller->clock_ticks * (1 << (1 + GET_CCDR_CDR(controller)));
|
else
|
else
|
divisor = controller->clock_ticks;
|
divisor = controller->clock_ticks;
|
}
|
}
|
else
|
else
|
{
|
{
|
divisor = controller->ext_ticks;
|
divisor = controller->ext_ticks;
|
}
|
}
|
|
|
/* how many times to increase counter? */
|
/* how many times to increase counter? */
|
quotient = warp / divisor;
|
quotient = warp / divisor;
|
remainder = warp % divisor;
|
remainder = warp % divisor;
|
|
|
/* NOTE: If the event rescheduling code works properly, the quotient
|
/* NOTE: If the event rescheduling code works properly, the quotient
|
should never be larger than 1. That is, we should receive events
|
should never be larger than 1. That is, we should receive events
|
here at least as frequently as the simulated counter is supposed
|
here at least as frequently as the simulated counter is supposed
|
to decrement. So the remainder (-> roundoff_ticks) will slowly
|
to decrement. So the remainder (-> roundoff_ticks) will slowly
|
accumulate, with the quotient == 0. Once in a while, quotient
|
accumulate, with the quotient == 0. Once in a while, quotient
|
will equal 1. */
|
will equal 1. */
|
|
|
controller->roundoff_ticks = remainder;
|
controller->roundoff_ticks = remainder;
|
controller->last_ticks = this_ticks;
|
controller->last_ticks = this_ticks;
|
while(quotient > 0) /* Is it time to increment counter? */
|
while(quotient > 0) /* Is it time to increment counter? */
|
{
|
{
|
/* next 24-bit counter value */
|
/* next 24-bit counter value */
|
unsigned_4 next_trr = (controller->trr + 1) % (1 << 24);
|
unsigned_4 next_trr = (controller->trr + 1) % (1 << 24);
|
quotient --;
|
quotient --;
|
|
|
switch((int) GET_TCR_TMODE(controller))
|
switch((int) GET_TCR_TMODE(controller))
|
{
|
{
|
case 0: /* interval timer mode */
|
case 0: /* interval timer mode */
|
{
|
{
|
/* Current or next counter value matches CPRA value? The
|
/* Current or next counter value matches CPRA value? The
|
first case covers counter holding at maximum before
|
first case covers counter holding at maximum before
|
reset. The second case covers normal counting
|
reset. The second case covers normal counting
|
behavior. */
|
behavior. */
|
if(controller->trr == controller->cpra ||
|
if(controller->trr == controller->cpra ||
|
next_trr == controller->cpra)
|
next_trr == controller->cpra)
|
{
|
{
|
/* likely hold CPRA value */
|
/* likely hold CPRA value */
|
if(controller->trr == controller->cpra)
|
if(controller->trr == controller->cpra)
|
next_trr = controller->cpra;
|
next_trr = controller->cpra;
|
|
|
SET_TISR_TIIS(controller);
|
SET_TISR_TIIS(controller);
|
|
|
/* Signal an interrupt if it is enabled with TIIE,
|
/* Signal an interrupt if it is enabled with TIIE,
|
and if we just arrived at CPRA. Don't repeatedly
|
and if we just arrived at CPRA. Don't repeatedly
|
interrupt if holding due to TZCE=0 */
|
interrupt if holding due to TZCE=0 */
|
if(GET_ITMR_TIIE(controller) &&
|
if(GET_ITMR_TIIE(controller) &&
|
next_trr != controller->trr)
|
next_trr != controller->trr)
|
{
|
{
|
hw_port_event(me, INT_PORT, 1);
|
hw_port_event(me, INT_PORT, 1);
|
}
|
}
|
|
|
/* Reset counter? */
|
/* Reset counter? */
|
if(GET_ITMR_TZCE(controller))
|
if(GET_ITMR_TZCE(controller))
|
{
|
{
|
next_trr = 0;
|
next_trr = 0;
|
}
|
}
|
}
|
}
|
}
|
}
|
break;
|
break;
|
|
|
case 1: /* pulse generator mode */
|
case 1: /* pulse generator mode */
|
{
|
{
|
/* first trip point */
|
/* first trip point */
|
if(next_trr == controller->cpra)
|
if(next_trr == controller->cpra)
|
{
|
{
|
/* flip flip-flop & report */
|
/* flip flip-flop & report */
|
controller->ff ^= 1;
|
controller->ff ^= 1;
|
hw_port_event(me, FF_PORT, controller->ff);
|
hw_port_event(me, FF_PORT, controller->ff);
|
SET_TISR_TPIAS(controller);
|
SET_TISR_TPIAS(controller);
|
|
|
/* signal interrupt */
|
/* signal interrupt */
|
if(GET_PMGR_TPIAE(controller))
|
if(GET_PMGR_TPIAE(controller))
|
{
|
{
|
hw_port_event(me, INT_PORT, 1);
|
hw_port_event(me, INT_PORT, 1);
|
}
|
}
|
|
|
}
|
}
|
/* second trip point */
|
/* second trip point */
|
else if(next_trr == controller->cprb)
|
else if(next_trr == controller->cprb)
|
{
|
{
|
/* flip flip-flop & report */
|
/* flip flip-flop & report */
|
controller->ff ^= 1;
|
controller->ff ^= 1;
|
hw_port_event(me, FF_PORT, controller->ff);
|
hw_port_event(me, FF_PORT, controller->ff);
|
SET_TISR_TPIBS(controller);
|
SET_TISR_TPIBS(controller);
|
|
|
/* signal interrupt */
|
/* signal interrupt */
|
if(GET_PMGR_TPIBE(controller))
|
if(GET_PMGR_TPIBE(controller))
|
{
|
{
|
hw_port_event(me, INT_PORT, 1);
|
hw_port_event(me, INT_PORT, 1);
|
}
|
}
|
|
|
/* clear counter */
|
/* clear counter */
|
next_trr = 0;
|
next_trr = 0;
|
}
|
}
|
}
|
}
|
break;
|
break;
|
|
|
case 2: /* watchdog timer mode */
|
case 2: /* watchdog timer mode */
|
{
|
{
|
/* watchdog timer expiry */
|
/* watchdog timer expiry */
|
if(next_trr == controller->cpra)
|
if(next_trr == controller->cpra)
|
{
|
{
|
SET_TISR_TWIS(controller);
|
SET_TISR_TWIS(controller);
|
|
|
/* signal interrupt */
|
/* signal interrupt */
|
if(GET_WTMR_TWIE(controller))
|
if(GET_WTMR_TWIE(controller))
|
{
|
{
|
hw_port_event(me, INT_PORT, 1);
|
hw_port_event(me, INT_PORT, 1);
|
}
|
}
|
|
|
/* clear counter */
|
/* clear counter */
|
next_trr = 0;
|
next_trr = 0;
|
}
|
}
|
}
|
}
|
break;
|
break;
|
|
|
case 3: /* disabled */
|
case 3: /* disabled */
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
|
|
/* update counter and report */
|
/* update counter and report */
|
controller->trr = next_trr;
|
controller->trr = next_trr;
|
/* HW_TRACE ((me, "counter trr %ld tisr %lx",
|
/* HW_TRACE ((me, "counter trr %ld tisr %lx",
|
(long) controller->trr, (long) controller->tisr)); */
|
(long) controller->trr, (long) controller->tisr)); */
|
} /* end quotient loop */
|
} /* end quotient loop */
|
|
|
/* Reschedule a timer event in near future, so we can increment the
|
/* Reschedule a timer event in near future, so we can increment the
|
counter again. Set the event about 75% of divisor time away, so
|
counter again. Set the event about 75% of divisor time away, so
|
we will experience roughly 1.3 events per counter increment. */
|
we will experience roughly 1.3 events per counter increment. */
|
controller->event = hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);
|
controller->event = hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);
|
}
|
}
|
|
|
|
|
|
|
|
|
const struct hw_descriptor dv_tx3904tmr_descriptor[] = {
|
const struct hw_descriptor dv_tx3904tmr_descriptor[] = {
|
{ "tx3904tmr", tx3904tmr_finish, },
|
{ "tx3904tmr", tx3904tmr_finish, },
|
{ NULL },
|
{ NULL },
|
};
|
};
|
|
|
