URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [adc.cgs] - Diff between revs 24 and 33

Rev 24	Rev 33
`# arm testcase for adc`	`# arm testcase for adc`
`# mach: all`	`# mach: all`

`# ??? Unfinished, more tests needed.`	`# ??? Unfinished, more tests needed.`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`# adc$cond${set-cc?} $rd,$rn,$imm12`	`# adc$cond${set-cc?} $rd,$rn,$imm12`

`.global adc_imm`	`.global adc_imm`
`adc_imm:`	`adc_imm:`
`mvi_h_gr r4,1`	`mvi_h_gr r4,1`
`mvi_h_cnvz 0,0,0,0`	`mvi_h_cnvz 0,0,0,0`
`adc r5,r4,#1`	`adc r5,r4,#1`
`test_h_cnvz 0,0,0,0`	`test_h_cnvz 0,0,0,0`
`test_h_gr r5,2`	`test_h_gr r5,2`

`# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}`	`# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}`

`.global adc_reg_imm_shift`	`.global adc_reg_imm_shift`
`adc_reg_imm_shift:`	`adc_reg_imm_shift:`
`mvi_h_gr r4,1`	`mvi_h_gr r4,1`
`mvi_h_gr r5,1`	`mvi_h_gr r5,1`
`mvi_h_cnvz 0,0,0,0`	`mvi_h_cnvz 0,0,0,0`
`adc r6,r4,r5,lsl #2`	`adc r6,r4,r5,lsl #2`
`test_h_cnvz 0,0,0,0`	`test_h_cnvz 0,0,0,0`
`test_h_gr r6,5`	`test_h_gr r6,5`

`# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}`	`# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}`

`.global adc_reg_reg_shift`	`.global adc_reg_reg_shift`
`adc_reg_reg_shift:`	`adc_reg_reg_shift:`
`mvi_h_gr r4,1`	`mvi_h_gr r4,1`
`mvi_h_gr r5,1`	`mvi_h_gr r5,1`
`mvi_h_gr r6,2`	`mvi_h_gr r6,2`
`mvi_h_cnvz 0,0,0,0`	`mvi_h_cnvz 0,0,0,0`
`adc r7,r4,r5,lsl r6`	`adc r7,r4,r5,lsl r6`
`test_h_cnvz 0,0,0,0`	`test_h_cnvz 0,0,0,0`
`test_h_gr r7,5`	`test_h_gr r7,5`

`pass`	`pass`